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302 lines
7.7 KiB
302 lines
7.7 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef DW_SPI_HEADER_H |
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#define DW_SPI_HEADER_H |
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#include <linux/bits.h> |
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#include <linux/completion.h> |
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#include <linux/debugfs.h> |
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#include <linux/irqreturn.h> |
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#include <linux/io.h> |
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#include <linux/scatterlist.h> |
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#include <linux/spi/spi-mem.h> |
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#include <linux/bitfield.h> |
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/* Register offsets */ |
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#define DW_SPI_CTRLR0 0x00 |
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#define DW_SPI_CTRLR1 0x04 |
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#define DW_SPI_SSIENR 0x08 |
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#define DW_SPI_MWCR 0x0c |
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#define DW_SPI_SER 0x10 |
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#define DW_SPI_BAUDR 0x14 |
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#define DW_SPI_TXFTLR 0x18 |
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#define DW_SPI_RXFTLR 0x1c |
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#define DW_SPI_TXFLR 0x20 |
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#define DW_SPI_RXFLR 0x24 |
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#define DW_SPI_SR 0x28 |
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#define DW_SPI_IMR 0x2c |
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#define DW_SPI_ISR 0x30 |
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#define DW_SPI_RISR 0x34 |
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#define DW_SPI_TXOICR 0x38 |
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#define DW_SPI_RXOICR 0x3c |
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#define DW_SPI_RXUICR 0x40 |
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#define DW_SPI_MSTICR 0x44 |
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#define DW_SPI_ICR 0x48 |
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#define DW_SPI_DMACR 0x4c |
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#define DW_SPI_DMATDLR 0x50 |
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#define DW_SPI_DMARDLR 0x54 |
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#define DW_SPI_IDR 0x58 |
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#define DW_SPI_VERSION 0x5c |
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#define DW_SPI_DR 0x60 |
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#define DW_SPI_RX_SAMPLE_DLY 0xf0 |
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#define DW_SPI_CS_OVERRIDE 0xf4 |
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/* Bit fields in CTRLR0 */ |
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#define SPI_DFS_OFFSET 0 |
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#define SPI_DFS_MASK GENMASK(3, 0) |
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#define SPI_DFS32_OFFSET 16 |
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#define SPI_FRF_OFFSET 4 |
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#define SPI_FRF_SPI 0x0 |
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#define SPI_FRF_SSP 0x1 |
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#define SPI_FRF_MICROWIRE 0x2 |
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#define SPI_FRF_RESV 0x3 |
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#define SPI_MODE_OFFSET 6 |
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#define SPI_SCPH_OFFSET 6 |
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#define SPI_SCOL_OFFSET 7 |
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#define SPI_TMOD_OFFSET 8 |
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#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET) |
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#define SPI_TMOD_TR 0x0 /* xmit & recv */ |
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#define SPI_TMOD_TO 0x1 /* xmit only */ |
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#define SPI_TMOD_RO 0x2 /* recv only */ |
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#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */ |
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#define SPI_SLVOE_OFFSET 10 |
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#define SPI_SRL_OFFSET 11 |
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#define SPI_CFS_OFFSET 12 |
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/* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */ |
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#define DWC_SSI_CTRLR0_SRL_OFFSET 13 |
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#define DWC_SSI_CTRLR0_TMOD_OFFSET 10 |
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#define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10) |
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#define DWC_SSI_CTRLR0_SCPOL_OFFSET 9 |
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#define DWC_SSI_CTRLR0_SCPH_OFFSET 8 |
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#define DWC_SSI_CTRLR0_FRF_OFFSET 6 |
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#define DWC_SSI_CTRLR0_DFS_OFFSET 0 |
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/* |
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* For Keem Bay, CTRLR0[31] is used to select controller mode. |
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* 0: SSI is slave |
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* 1: SSI is master |
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*/ |
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#define DWC_SSI_CTRLR0_KEEMBAY_MST BIT(31) |
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/* Bit fields in CTRLR1 */ |
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#define SPI_NDF_MASK GENMASK(15, 0) |
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/* Bit fields in SR, 7 bits */ |
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#define SR_MASK 0x7f /* cover 7 bits */ |
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#define SR_BUSY (1 << 0) |
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#define SR_TF_NOT_FULL (1 << 1) |
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#define SR_TF_EMPT (1 << 2) |
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#define SR_RF_NOT_EMPT (1 << 3) |
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#define SR_RF_FULL (1 << 4) |
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#define SR_TX_ERR (1 << 5) |
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#define SR_DCOL (1 << 6) |
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/* Bit fields in ISR, IMR, RISR, 7 bits */ |
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#define SPI_INT_TXEI (1 << 0) |
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#define SPI_INT_TXOI (1 << 1) |
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#define SPI_INT_RXUI (1 << 2) |
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#define SPI_INT_RXOI (1 << 3) |
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#define SPI_INT_RXFI (1 << 4) |
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#define SPI_INT_MSTI (1 << 5) |
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/* Bit fields in DMACR */ |
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#define SPI_DMA_RDMAE (1 << 0) |
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#define SPI_DMA_TDMAE (1 << 1) |
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#define SPI_WAIT_RETRIES 5 |
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#define SPI_BUF_SIZE \ |
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(sizeof_field(struct spi_mem_op, cmd.opcode) + \ |
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sizeof_field(struct spi_mem_op, addr.val) + 256) |
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#define SPI_GET_BYTE(_val, _idx) \ |
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((_val) >> (BITS_PER_BYTE * (_idx)) & 0xff) |
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enum dw_ssi_type { |
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SSI_MOTO_SPI = 0, |
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SSI_TI_SSP, |
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SSI_NS_MICROWIRE, |
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}; |
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/* DW SPI capabilities */ |
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#define DW_SPI_CAP_CS_OVERRIDE BIT(0) |
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#define DW_SPI_CAP_KEEMBAY_MST BIT(1) |
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#define DW_SPI_CAP_DWC_SSI BIT(2) |
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#define DW_SPI_CAP_DFS32 BIT(3) |
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/* Slave spi_transfer/spi_mem_op related */ |
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struct dw_spi_cfg { |
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u8 tmode; |
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u8 dfs; |
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u32 ndf; |
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u32 freq; |
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}; |
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struct dw_spi; |
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struct dw_spi_dma_ops { |
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int (*dma_init)(struct device *dev, struct dw_spi *dws); |
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void (*dma_exit)(struct dw_spi *dws); |
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int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer); |
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bool (*can_dma)(struct spi_controller *master, struct spi_device *spi, |
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struct spi_transfer *xfer); |
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int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer); |
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void (*dma_stop)(struct dw_spi *dws); |
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}; |
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struct dw_spi { |
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struct spi_controller *master; |
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void __iomem *regs; |
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unsigned long paddr; |
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int irq; |
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u32 fifo_len; /* depth of the FIFO buffer */ |
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unsigned int dfs_offset; /* CTRLR0 DFS field offset */ |
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u32 max_mem_freq; /* max mem-ops bus freq */ |
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u32 max_freq; /* max bus freq supported */ |
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u32 caps; /* DW SPI capabilities */ |
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u32 reg_io_width; /* DR I/O width in bytes */ |
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u16 bus_num; |
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u16 num_cs; /* supported slave numbers */ |
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void (*set_cs)(struct spi_device *spi, bool enable); |
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/* Current message transfer state info */ |
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void *tx; |
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unsigned int tx_len; |
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void *rx; |
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unsigned int rx_len; |
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u8 buf[SPI_BUF_SIZE]; |
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int dma_mapped; |
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u8 n_bytes; /* current is a 1/2 bytes op */ |
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irqreturn_t (*transfer_handler)(struct dw_spi *dws); |
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u32 current_freq; /* frequency in hz */ |
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u32 cur_rx_sample_dly; |
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u32 def_rx_sample_dly_ns; |
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/* Custom memory operations */ |
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struct spi_controller_mem_ops mem_ops; |
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/* DMA info */ |
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struct dma_chan *txchan; |
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u32 txburst; |
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struct dma_chan *rxchan; |
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u32 rxburst; |
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u32 dma_sg_burst; |
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unsigned long dma_chan_busy; |
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dma_addr_t dma_addr; /* phy address of the Data register */ |
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const struct dw_spi_dma_ops *dma_ops; |
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struct completion dma_completion; |
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#ifdef CONFIG_DEBUG_FS |
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struct dentry *debugfs; |
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struct debugfs_regset32 regset; |
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#endif |
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}; |
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static inline u32 dw_readl(struct dw_spi *dws, u32 offset) |
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{ |
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return __raw_readl(dws->regs + offset); |
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} |
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static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) |
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{ |
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__raw_writel(val, dws->regs + offset); |
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} |
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static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset) |
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{ |
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switch (dws->reg_io_width) { |
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case 2: |
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return readw_relaxed(dws->regs + offset); |
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case 4: |
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default: |
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return readl_relaxed(dws->regs + offset); |
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} |
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} |
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static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val) |
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{ |
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switch (dws->reg_io_width) { |
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case 2: |
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writew_relaxed(val, dws->regs + offset); |
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break; |
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case 4: |
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default: |
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writel_relaxed(val, dws->regs + offset); |
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break; |
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} |
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} |
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static inline void spi_enable_chip(struct dw_spi *dws, int enable) |
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{ |
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dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); |
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} |
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static inline void spi_set_clk(struct dw_spi *dws, u16 div) |
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{ |
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dw_writel(dws, DW_SPI_BAUDR, div); |
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} |
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/* Disable IRQ bits */ |
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static inline void spi_mask_intr(struct dw_spi *dws, u32 mask) |
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{ |
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u32 new_mask; |
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new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask; |
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dw_writel(dws, DW_SPI_IMR, new_mask); |
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} |
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/* Enable IRQ bits */ |
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static inline void spi_umask_intr(struct dw_spi *dws, u32 mask) |
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{ |
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u32 new_mask; |
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new_mask = dw_readl(dws, DW_SPI_IMR) | mask; |
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dw_writel(dws, DW_SPI_IMR, new_mask); |
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} |
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/* |
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* This disables the SPI controller, interrupts, clears the interrupts status |
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* and CS, then re-enables the controller back. Transmit and receive FIFO |
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* buffers are cleared when the device is disabled. |
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*/ |
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static inline void spi_reset_chip(struct dw_spi *dws) |
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{ |
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spi_enable_chip(dws, 0); |
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spi_mask_intr(dws, 0xff); |
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dw_readl(dws, DW_SPI_ICR); |
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dw_writel(dws, DW_SPI_SER, 0); |
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spi_enable_chip(dws, 1); |
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} |
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static inline void spi_shutdown_chip(struct dw_spi *dws) |
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{ |
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spi_enable_chip(dws, 0); |
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spi_set_clk(dws, 0); |
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} |
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extern void dw_spi_set_cs(struct spi_device *spi, bool enable); |
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extern void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, |
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struct dw_spi_cfg *cfg); |
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extern int dw_spi_check_status(struct dw_spi *dws, bool raw); |
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extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws); |
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extern void dw_spi_remove_host(struct dw_spi *dws); |
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extern int dw_spi_suspend_host(struct dw_spi *dws); |
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extern int dw_spi_resume_host(struct dw_spi *dws); |
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#ifdef CONFIG_SPI_DW_DMA |
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extern void dw_spi_dma_setup_mfld(struct dw_spi *dws); |
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extern void dw_spi_dma_setup_generic(struct dw_spi *dws); |
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#else |
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static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {} |
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static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {} |
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#endif /* !CONFIG_SPI_DW_DMA */ |
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#endif /* DW_SPI_HEADER_H */
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