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202 lines
4.8 KiB
202 lines
4.8 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// |
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// DFL bus driver for Altera SPI Master |
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// |
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// Copyright (C) 2020 Intel Corporation, Inc. |
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// |
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// Authors: |
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// Matthew Gerlach <[email protected]> |
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// |
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#include <linux/types.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/stddef.h> |
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#include <linux/errno.h> |
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#include <linux/platform_device.h> |
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#include <linux/io.h> |
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#include <linux/bitfield.h> |
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#include <linux/io-64-nonatomic-lo-hi.h> |
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#include <linux/regmap.h> |
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#include <linux/spi/spi.h> |
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#include <linux/spi/altera.h> |
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#include <linux/dfl.h> |
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#define FME_FEATURE_ID_MAX10_SPI 0xe |
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#define FME_FEATURE_REV_MAX10_SPI_N5010 0x1 |
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#define SPI_CORE_PARAMETER 0x8 |
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#define SHIFT_MODE BIT_ULL(1) |
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#define SHIFT_MODE_MSB 0 |
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#define SHIFT_MODE_LSB 1 |
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#define DATA_WIDTH GENMASK_ULL(7, 2) |
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#define NUM_CHIPSELECT GENMASK_ULL(13, 8) |
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#define CLK_POLARITY BIT_ULL(14) |
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#define CLK_PHASE BIT_ULL(15) |
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#define PERIPHERAL_ID GENMASK_ULL(47, 32) |
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#define SPI_CLK GENMASK_ULL(31, 22) |
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#define SPI_INDIRECT_ACC_OFST 0x10 |
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#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0) |
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#define INDIRECT_WR BIT_ULL(8) |
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#define INDIRECT_RD BIT_ULL(9) |
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#define INDIRECT_RD_DATA (SPI_INDIRECT_ACC_OFST+0x8) |
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#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0) |
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#define INDIRECT_DEBUG BIT_ULL(32) |
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#define INDIRECT_WR_DATA (SPI_INDIRECT_ACC_OFST+0x10) |
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#define INDIRECT_TIMEOUT 10000 |
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static int indirect_bus_reg_read(void *context, unsigned int reg, |
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unsigned int *val) |
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{ |
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void __iomem *base = context; |
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int loops; |
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u64 v; |
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writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR); |
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loops = 0; |
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while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) && |
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(loops++ < INDIRECT_TIMEOUT)) |
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cpu_relax(); |
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if (loops >= INDIRECT_TIMEOUT) { |
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pr_err("%s timed out %d\n", __func__, loops); |
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return -ETIME; |
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} |
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v = readq(base + INDIRECT_RD_DATA); |
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*val = v & INDIRECT_DATA_MASK; |
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return 0; |
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} |
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static int indirect_bus_reg_write(void *context, unsigned int reg, |
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unsigned int val) |
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{ |
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void __iomem *base = context; |
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int loops; |
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writeq(val, base + INDIRECT_WR_DATA); |
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writeq((reg >> 2) | INDIRECT_WR, base + INDIRECT_ADDR); |
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loops = 0; |
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while ((readq(base + INDIRECT_ADDR) & INDIRECT_WR) && |
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(loops++ < INDIRECT_TIMEOUT)) |
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cpu_relax(); |
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if (loops >= INDIRECT_TIMEOUT) { |
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pr_err("%s timed out %d\n", __func__, loops); |
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return -ETIME; |
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} |
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return 0; |
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} |
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static const struct regmap_config indirect_regbus_cfg = { |
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.reg_bits = 32, |
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.reg_stride = 4, |
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.val_bits = 32, |
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.fast_io = true, |
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.max_register = 24, |
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.reg_write = indirect_bus_reg_write, |
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.reg_read = indirect_bus_reg_read, |
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}; |
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static struct spi_board_info m10_bmc_info = { |
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.modalias = "m10-d5005", |
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.max_speed_hz = 12500000, |
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.bus_num = 0, |
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.chip_select = 0, |
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}; |
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static void config_spi_master(void __iomem *base, struct spi_master *master) |
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{ |
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u64 v; |
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v = readq(base + SPI_CORE_PARAMETER); |
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master->mode_bits = SPI_CS_HIGH; |
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if (FIELD_GET(CLK_POLARITY, v)) |
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master->mode_bits |= SPI_CPOL; |
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if (FIELD_GET(CLK_PHASE, v)) |
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master->mode_bits |= SPI_CPHA; |
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master->num_chipselect = FIELD_GET(NUM_CHIPSELECT, v); |
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master->bits_per_word_mask = |
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SPI_BPW_RANGE_MASK(1, FIELD_GET(DATA_WIDTH, v)); |
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} |
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static int dfl_spi_altera_probe(struct dfl_device *dfl_dev) |
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{ |
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struct device *dev = &dfl_dev->dev; |
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struct spi_master *master; |
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struct altera_spi *hw; |
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void __iomem *base; |
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int err = -ENODEV; |
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master = spi_alloc_master(dev, sizeof(struct altera_spi)); |
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if (!master) |
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return -ENOMEM; |
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master->bus_num = dfl_dev->id; |
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hw = spi_master_get_devdata(master); |
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hw->dev = dev; |
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base = devm_ioremap_resource(dev, &dfl_dev->mmio_res); |
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if (IS_ERR(base)) |
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return PTR_ERR(base); |
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config_spi_master(base, master); |
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dev_dbg(dev, "%s cs %u bpm 0x%x mode 0x%x\n", __func__, |
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master->num_chipselect, master->bits_per_word_mask, |
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master->mode_bits); |
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hw->regmap = devm_regmap_init(dev, NULL, base, &indirect_regbus_cfg); |
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if (IS_ERR(hw->regmap)) |
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return PTR_ERR(hw->regmap); |
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hw->irq = -EINVAL; |
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altera_spi_init_master(master); |
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err = devm_spi_register_master(dev, master); |
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if (err) { |
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dev_err(dev, "%s failed to register spi master %d\n", __func__, err); |
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goto exit; |
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} |
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if (!spi_new_device(master, &m10_bmc_info)) { |
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dev_err(dev, "%s failed to create SPI device: %s\n", |
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__func__, m10_bmc_info.modalias); |
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} |
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return 0; |
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exit: |
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spi_master_put(master); |
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return err; |
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} |
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static const struct dfl_device_id dfl_spi_altera_ids[] = { |
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{ FME_ID, FME_FEATURE_ID_MAX10_SPI }, |
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{ } |
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}; |
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static struct dfl_driver dfl_spi_altera_driver = { |
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.drv = { |
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.name = "dfl-spi-altera", |
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}, |
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.id_table = dfl_spi_altera_ids, |
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.probe = dfl_spi_altera_probe, |
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}; |
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module_dfl_driver(dfl_spi_altera_driver); |
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MODULE_DEVICE_TABLE(dfl, dfl_spi_altera_ids); |
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MODULE_DESCRIPTION("DFL spi altera driver"); |
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MODULE_AUTHOR("Intel Corporation"); |
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MODULE_LICENSE("GPL v2");
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