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372 lines
9.6 KiB
372 lines
9.6 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2020, The Linux Foundation. All rights reserved. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <linux/regulator/consumer.h> |
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#include <linux/reset.h> |
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#include <linux/slab.h> |
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#define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c) |
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#define SLEEPM BIT(0) |
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#define OPMODE_MASK GENMASK(4, 3) |
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#define OPMODE_NORMAL (0x00) |
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#define OPMODE_NONDRIVING BIT(3) |
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#define TERMSEL BIT(5) |
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#define USB2_PHY_USB_PHY_UTMI_CTRL1 (0x40) |
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#define XCVRSEL BIT(0) |
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#define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50) |
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#define POR BIT(1) |
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#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) |
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#define RETENABLEN BIT(3) |
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#define FSEL_MASK GENMASK(7, 5) |
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#define FSEL_DEFAULT (0x3 << 4) |
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#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58) |
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#define VBUSVLDEXTSEL0 BIT(4) |
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#define PLLBTUNE BIT(5) |
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#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2 (0x5c) |
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#define VREGBYPASS BIT(0) |
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#define USB2_PHY_USB_PHY_HS_PHY_CTRL1 (0x60) |
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#define VBUSVLDEXT0 BIT(0) |
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#define USB2_PHY_USB_PHY_HS_PHY_CTRL2 (0x64) |
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#define USB2_AUTO_RESUME BIT(0) |
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#define USB2_SUSPEND_N BIT(2) |
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#define USB2_SUSPEND_N_SEL BIT(3) |
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#define USB2_PHY_USB_PHY_CFG0 (0x94) |
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#define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0) |
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#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1) |
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#define USB2_PHY_USB_PHY_REFCLK_CTRL (0xa0) |
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#define REFCLK_SEL_MASK GENMASK(1, 0) |
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#define REFCLK_SEL_DEFAULT (0x2 << 0) |
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static const char * const qcom_snps_hsphy_vreg_names[] = { |
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"vdda-pll", "vdda33", "vdda18", |
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}; |
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#define SNPS_HS_NUM_VREGS ARRAY_SIZE(qcom_snps_hsphy_vreg_names) |
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/** |
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* struct qcom_snps_hsphy - snps hs phy attributes |
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* |
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* @phy: generic phy |
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* @base: iomapped memory space for snps hs phy |
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* |
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* @cfg_ahb_clk: AHB2PHY interface clock |
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* @ref_clk: phy reference clock |
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* @iface_clk: phy interface clock |
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* @phy_reset: phy reset control |
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* @vregs: regulator supplies bulk data |
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* @phy_initialized: if PHY has been initialized correctly |
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* @mode: contains the current mode the PHY is in |
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*/ |
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struct qcom_snps_hsphy { |
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struct phy *phy; |
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void __iomem *base; |
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struct clk *cfg_ahb_clk; |
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struct clk *ref_clk; |
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struct reset_control *phy_reset; |
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struct regulator_bulk_data vregs[SNPS_HS_NUM_VREGS]; |
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bool phy_initialized; |
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enum phy_mode mode; |
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}; |
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static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset, |
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u32 mask, u32 val) |
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{ |
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u32 reg; |
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reg = readl_relaxed(base + offset); |
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reg &= ~mask; |
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reg |= val & mask; |
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writel_relaxed(reg, base + offset); |
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/* Ensure above write is completed */ |
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readl_relaxed(base + offset); |
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} |
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static int qcom_snps_hsphy_suspend(struct qcom_snps_hsphy *hsphy) |
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{ |
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dev_dbg(&hsphy->phy->dev, "Suspend QCOM SNPS PHY\n"); |
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if (hsphy->mode == PHY_MODE_USB_HOST) { |
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/* Enable auto-resume to meet remote wakeup timing */ |
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qcom_snps_hsphy_write_mask(hsphy->base, |
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USB2_PHY_USB_PHY_HS_PHY_CTRL2, |
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USB2_AUTO_RESUME, |
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USB2_AUTO_RESUME); |
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usleep_range(500, 1000); |
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qcom_snps_hsphy_write_mask(hsphy->base, |
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USB2_PHY_USB_PHY_HS_PHY_CTRL2, |
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0, USB2_AUTO_RESUME); |
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} |
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clk_disable_unprepare(hsphy->cfg_ahb_clk); |
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return 0; |
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} |
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static int qcom_snps_hsphy_resume(struct qcom_snps_hsphy *hsphy) |
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{ |
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int ret; |
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dev_dbg(&hsphy->phy->dev, "Resume QCOM SNPS PHY, mode\n"); |
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ret = clk_prepare_enable(hsphy->cfg_ahb_clk); |
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if (ret) { |
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dev_err(&hsphy->phy->dev, "failed to enable cfg ahb clock\n"); |
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return ret; |
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} |
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return 0; |
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} |
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static int __maybe_unused qcom_snps_hsphy_runtime_suspend(struct device *dev) |
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{ |
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struct qcom_snps_hsphy *hsphy = dev_get_drvdata(dev); |
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if (!hsphy->phy_initialized) |
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return 0; |
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qcom_snps_hsphy_suspend(hsphy); |
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return 0; |
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} |
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static int __maybe_unused qcom_snps_hsphy_runtime_resume(struct device *dev) |
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{ |
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struct qcom_snps_hsphy *hsphy = dev_get_drvdata(dev); |
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if (!hsphy->phy_initialized) |
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return 0; |
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qcom_snps_hsphy_resume(hsphy); |
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return 0; |
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} |
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static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode, |
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int submode) |
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{ |
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struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy); |
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hsphy->mode = mode; |
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return 0; |
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} |
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static int qcom_snps_hsphy_init(struct phy *phy) |
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{ |
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struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy); |
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int ret; |
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dev_vdbg(&phy->dev, "%s(): Initializing SNPS HS phy\n", __func__); |
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ret = regulator_bulk_enable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); |
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if (ret) |
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return ret; |
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ret = clk_prepare_enable(hsphy->cfg_ahb_clk); |
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if (ret) { |
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dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); |
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goto poweroff_phy; |
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} |
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ret = reset_control_assert(hsphy->phy_reset); |
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if (ret) { |
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dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret); |
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goto disable_ahb_clk; |
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} |
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usleep_range(100, 150); |
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ret = reset_control_deassert(hsphy->phy_reset); |
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if (ret) { |
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dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret); |
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goto disable_ahb_clk; |
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} |
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qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0, |
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UTMI_PHY_CMN_CTRL_OVERRIDE_EN, |
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UTMI_PHY_CMN_CTRL_OVERRIDE_EN); |
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qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5, |
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POR, POR); |
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qcom_snps_hsphy_write_mask(hsphy->base, |
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USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, |
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FSEL_MASK, 0); |
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qcom_snps_hsphy_write_mask(hsphy->base, |
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USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, |
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PLLBTUNE, PLLBTUNE); |
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qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_REFCLK_CTRL, |
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REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK); |
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qcom_snps_hsphy_write_mask(hsphy->base, |
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USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, |
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VBUSVLDEXTSEL0, VBUSVLDEXTSEL0); |
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qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1, |
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VBUSVLDEXT0, VBUSVLDEXT0); |
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qcom_snps_hsphy_write_mask(hsphy->base, |
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USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, |
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VREGBYPASS, VREGBYPASS); |
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qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, |
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USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, |
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USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); |
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qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL0, |
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SLEEPM, SLEEPM); |
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qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5, |
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POR, 0); |
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qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, |
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USB2_SUSPEND_N_SEL, 0); |
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qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0, |
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UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0); |
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hsphy->phy_initialized = true; |
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return 0; |
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disable_ahb_clk: |
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clk_disable_unprepare(hsphy->cfg_ahb_clk); |
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poweroff_phy: |
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regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); |
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return ret; |
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} |
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static int qcom_snps_hsphy_exit(struct phy *phy) |
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{ |
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struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy); |
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reset_control_assert(hsphy->phy_reset); |
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clk_disable_unprepare(hsphy->cfg_ahb_clk); |
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regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); |
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hsphy->phy_initialized = false; |
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return 0; |
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} |
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static const struct phy_ops qcom_snps_hsphy_gen_ops = { |
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.init = qcom_snps_hsphy_init, |
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.exit = qcom_snps_hsphy_exit, |
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.set_mode = qcom_snps_hsphy_set_mode, |
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.owner = THIS_MODULE, |
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}; |
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static const struct of_device_id qcom_snps_hsphy_of_match_table[] = { |
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{ .compatible = "qcom,sm8150-usb-hs-phy", }, |
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{ .compatible = "qcom,usb-snps-hs-7nm-phy", }, |
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{ .compatible = "qcom,usb-snps-femto-v2-phy", }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_of_match_table); |
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static const struct dev_pm_ops qcom_snps_hsphy_pm_ops = { |
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SET_RUNTIME_PM_OPS(qcom_snps_hsphy_runtime_suspend, |
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qcom_snps_hsphy_runtime_resume, NULL) |
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}; |
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static int qcom_snps_hsphy_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct qcom_snps_hsphy *hsphy; |
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struct phy_provider *phy_provider; |
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struct phy *generic_phy; |
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int ret, i; |
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int num; |
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hsphy = devm_kzalloc(dev, sizeof(*hsphy), GFP_KERNEL); |
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if (!hsphy) |
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return -ENOMEM; |
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hsphy->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(hsphy->base)) |
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return PTR_ERR(hsphy->base); |
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hsphy->ref_clk = devm_clk_get(dev, "ref"); |
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if (IS_ERR(hsphy->ref_clk)) { |
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ret = PTR_ERR(hsphy->ref_clk); |
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if (ret != -EPROBE_DEFER) |
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dev_err(dev, "failed to get ref clk, %d\n", ret); |
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return ret; |
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} |
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hsphy->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL); |
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if (IS_ERR(hsphy->phy_reset)) { |
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dev_err(dev, "failed to get phy core reset\n"); |
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return PTR_ERR(hsphy->phy_reset); |
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} |
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num = ARRAY_SIZE(hsphy->vregs); |
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for (i = 0; i < num; i++) |
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hsphy->vregs[i].supply = qcom_snps_hsphy_vreg_names[i]; |
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ret = devm_regulator_bulk_get(dev, num, hsphy->vregs); |
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if (ret) { |
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if (ret != -EPROBE_DEFER) |
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dev_err(dev, "failed to get regulator supplies: %d\n", |
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ret); |
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return ret; |
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} |
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pm_runtime_set_active(dev); |
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pm_runtime_enable(dev); |
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/* |
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* Prevent runtime pm from being ON by default. Users can enable |
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* it using power/control in sysfs. |
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*/ |
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pm_runtime_forbid(dev); |
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generic_phy = devm_phy_create(dev, NULL, &qcom_snps_hsphy_gen_ops); |
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if (IS_ERR(generic_phy)) { |
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ret = PTR_ERR(generic_phy); |
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dev_err(dev, "failed to create phy, %d\n", ret); |
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return ret; |
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} |
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hsphy->phy = generic_phy; |
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dev_set_drvdata(dev, hsphy); |
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phy_set_drvdata(generic_phy, hsphy); |
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
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if (!IS_ERR(phy_provider)) |
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dev_dbg(dev, "Registered Qcom-SNPS HS phy\n"); |
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else |
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pm_runtime_disable(dev); |
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return PTR_ERR_OR_ZERO(phy_provider); |
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} |
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static struct platform_driver qcom_snps_hsphy_driver = { |
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.probe = qcom_snps_hsphy_probe, |
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.driver = { |
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.name = "qcom-snps-hs-femto-v2-phy", |
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.pm = &qcom_snps_hsphy_pm_ops, |
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.of_match_table = qcom_snps_hsphy_of_match_table, |
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}, |
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}; |
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module_platform_driver(qcom_snps_hsphy_driver); |
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MODULE_DESCRIPTION("Qualcomm SNPS FEMTO USB HS PHY V2 driver"); |
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MODULE_LICENSE("GPL v2");
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