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53 lines
1.5 KiB
53 lines
1.5 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright (c) 2019 MediaTek Inc. |
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* Author: Jitao Shi <[email protected]> |
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*/ |
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#ifndef _MTK_MIPI_TX_H |
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#define _MTK_MIPI_TX_H |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/nvmem-consumer.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/phy/phy.h> |
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#include <linux/slab.h> |
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struct mtk_mipitx_data { |
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const u32 mppll_preserve; |
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const struct clk_ops *mipi_tx_clk_ops; |
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void (*mipi_tx_enable_signal)(struct phy *phy); |
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void (*mipi_tx_disable_signal)(struct phy *phy); |
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}; |
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struct mtk_mipi_tx { |
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struct device *dev; |
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void __iomem *regs; |
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u32 data_rate; |
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u32 mipitx_drive; |
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u32 rt_code[5]; |
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const struct mtk_mipitx_data *driver_data; |
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struct clk_hw pll_hw; |
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struct clk *pll; |
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}; |
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struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw); |
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void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 bits); |
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void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 bits); |
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void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 mask, |
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u32 data); |
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int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate); |
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unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate); |
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extern const struct mtk_mipitx_data mt2701_mipitx_data; |
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extern const struct mtk_mipitx_data mt8173_mipitx_data; |
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extern const struct mtk_mipitx_data mt8183_mipitx_data; |
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#endif
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