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288 lines
8.3 KiB
288 lines
8.3 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2019 MediaTek Inc. |
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* Author: jitao.shi <[email protected]> |
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*/ |
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#include "phy-mtk-mipi-dsi.h" |
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#define MIPITX_DSI_CON 0x00 |
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#define RG_DSI_LDOCORE_EN BIT(0) |
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#define RG_DSI_CKG_LDOOUT_EN BIT(1) |
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#define RG_DSI_BCLK_SEL (3 << 2) |
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#define RG_DSI_LD_IDX_SEL (7 << 4) |
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#define RG_DSI_PHYCLK_SEL (2 << 8) |
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#define RG_DSI_DSICLK_FREQ_SEL BIT(10) |
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#define RG_DSI_LPTX_CLMP_EN BIT(11) |
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#define MIPITX_DSI_CLOCK_LANE 0x04 |
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#define MIPITX_DSI_DATA_LANE0 0x08 |
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#define MIPITX_DSI_DATA_LANE1 0x0c |
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#define MIPITX_DSI_DATA_LANE2 0x10 |
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#define MIPITX_DSI_DATA_LANE3 0x14 |
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#define RG_DSI_LNTx_LDOOUT_EN BIT(0) |
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#define RG_DSI_LNTx_CKLANE_EN BIT(1) |
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#define RG_DSI_LNTx_LPTX_IPLUS1 BIT(2) |
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#define RG_DSI_LNTx_LPTX_IPLUS2 BIT(3) |
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#define RG_DSI_LNTx_LPTX_IMINUS BIT(4) |
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#define RG_DSI_LNTx_LPCD_IPLUS BIT(5) |
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#define RG_DSI_LNTx_LPCD_IMINUS BIT(6) |
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#define RG_DSI_LNTx_RT_CODE (0xf << 8) |
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#define MIPITX_DSI_TOP_CON 0x40 |
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#define RG_DSI_LNT_INTR_EN BIT(0) |
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#define RG_DSI_LNT_HS_BIAS_EN BIT(1) |
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#define RG_DSI_LNT_IMP_CAL_EN BIT(2) |
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#define RG_DSI_LNT_TESTMODE_EN BIT(3) |
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#define RG_DSI_LNT_IMP_CAL_CODE (0xf << 4) |
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#define RG_DSI_LNT_AIO_SEL (7 << 8) |
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#define RG_DSI_PAD_TIE_LOW_EN BIT(11) |
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#define RG_DSI_DEBUG_INPUT_EN BIT(12) |
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#define RG_DSI_PRESERVE (7 << 13) |
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#define MIPITX_DSI_BG_CON 0x44 |
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#define RG_DSI_BG_CORE_EN BIT(0) |
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#define RG_DSI_BG_CKEN BIT(1) |
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#define RG_DSI_BG_DIV (0x3 << 2) |
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#define RG_DSI_BG_FAST_CHARGE BIT(4) |
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#define RG_DSI_VOUT_MSK (0x3ffff << 5) |
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#define RG_DSI_V12_SEL (7 << 5) |
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#define RG_DSI_V10_SEL (7 << 8) |
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#define RG_DSI_V072_SEL (7 << 11) |
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#define RG_DSI_V04_SEL (7 << 14) |
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#define RG_DSI_V032_SEL (7 << 17) |
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#define RG_DSI_V02_SEL (7 << 20) |
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#define RG_DSI_BG_R1_TRIM (0xf << 24) |
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#define RG_DSI_BG_R2_TRIM (0xf << 28) |
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#define MIPITX_DSI_PLL_CON0 0x50 |
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#define RG_DSI_MPPLL_PLL_EN BIT(0) |
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#define RG_DSI_MPPLL_DIV_MSK (0x1ff << 1) |
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#define RG_DSI_MPPLL_PREDIV (3 << 1) |
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#define RG_DSI_MPPLL_TXDIV0 (3 << 3) |
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#define RG_DSI_MPPLL_TXDIV1 (3 << 5) |
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#define RG_DSI_MPPLL_POSDIV (7 << 7) |
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#define RG_DSI_MPPLL_MONVC_EN BIT(10) |
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#define RG_DSI_MPPLL_MONREF_EN BIT(11) |
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#define RG_DSI_MPPLL_VOD_EN BIT(12) |
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#define MIPITX_DSI_PLL_CON1 0x54 |
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#define RG_DSI_MPPLL_SDM_FRA_EN BIT(0) |
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#define RG_DSI_MPPLL_SDM_SSC_PH_INIT BIT(1) |
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#define RG_DSI_MPPLL_SDM_SSC_EN BIT(2) |
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#define RG_DSI_MPPLL_SDM_SSC_PRD (0xffff << 16) |
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#define MIPITX_DSI_PLL_CON2 0x58 |
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#define MIPITX_DSI_PLL_TOP 0x64 |
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#define RG_DSI_MPPLL_PRESERVE (0xff << 8) |
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#define MIPITX_DSI_PLL_PWR 0x68 |
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#define RG_DSI_MPPLL_SDM_PWR_ON BIT(0) |
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#define RG_DSI_MPPLL_SDM_ISO_EN BIT(1) |
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#define RG_DSI_MPPLL_SDM_PWR_ACK BIT(8) |
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#define MIPITX_DSI_SW_CTRL 0x80 |
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#define SW_CTRL_EN BIT(0) |
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#define MIPITX_DSI_SW_CTRL_CON0 0x84 |
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#define SW_LNTC_LPTX_PRE_OE BIT(0) |
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#define SW_LNTC_LPTX_OE BIT(1) |
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#define SW_LNTC_LPTX_P BIT(2) |
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#define SW_LNTC_LPTX_N BIT(3) |
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#define SW_LNTC_HSTX_PRE_OE BIT(4) |
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#define SW_LNTC_HSTX_OE BIT(5) |
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#define SW_LNTC_HSTX_ZEROCLK BIT(6) |
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#define SW_LNT0_LPTX_PRE_OE BIT(7) |
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#define SW_LNT0_LPTX_OE BIT(8) |
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#define SW_LNT0_LPTX_P BIT(9) |
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#define SW_LNT0_LPTX_N BIT(10) |
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#define SW_LNT0_HSTX_PRE_OE BIT(11) |
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#define SW_LNT0_HSTX_OE BIT(12) |
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#define SW_LNT0_LPRX_EN BIT(13) |
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#define SW_LNT1_LPTX_PRE_OE BIT(14) |
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#define SW_LNT1_LPTX_OE BIT(15) |
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#define SW_LNT1_LPTX_P BIT(16) |
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#define SW_LNT1_LPTX_N BIT(17) |
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#define SW_LNT1_HSTX_PRE_OE BIT(18) |
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#define SW_LNT1_HSTX_OE BIT(19) |
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#define SW_LNT2_LPTX_PRE_OE BIT(20) |
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#define SW_LNT2_LPTX_OE BIT(21) |
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#define SW_LNT2_LPTX_P BIT(22) |
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#define SW_LNT2_LPTX_N BIT(23) |
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#define SW_LNT2_HSTX_PRE_OE BIT(24) |
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#define SW_LNT2_HSTX_OE BIT(25) |
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static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) |
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{ |
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struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); |
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u8 txdiv, txdiv0, txdiv1; |
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u64 pcw; |
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dev_dbg(mipi_tx->dev, "prepare: %u Hz\n", mipi_tx->data_rate); |
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if (mipi_tx->data_rate >= 500000000) { |
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txdiv = 1; |
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txdiv0 = 0; |
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txdiv1 = 0; |
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} else if (mipi_tx->data_rate >= 250000000) { |
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txdiv = 2; |
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txdiv0 = 1; |
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txdiv1 = 0; |
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} else if (mipi_tx->data_rate >= 125000000) { |
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txdiv = 4; |
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txdiv0 = 2; |
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txdiv1 = 0; |
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} else if (mipi_tx->data_rate > 62000000) { |
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txdiv = 8; |
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txdiv0 = 2; |
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txdiv1 = 1; |
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} else if (mipi_tx->data_rate >= 50000000) { |
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txdiv = 16; |
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txdiv0 = 2; |
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txdiv1 = 2; |
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} else { |
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return -EINVAL; |
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} |
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mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_BG_CON, |
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RG_DSI_VOUT_MSK | |
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RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN, |
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(4 << 20) | (4 << 17) | (4 << 14) | |
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(4 << 11) | (4 << 8) | (4 << 5) | |
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RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN); |
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usleep_range(30, 100); |
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mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON, |
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RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN, |
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(8 << 4) | RG_DSI_LNT_HS_BIAS_EN); |
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mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_CON, |
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RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN); |
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mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR, |
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RG_DSI_MPPLL_SDM_PWR_ON | |
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RG_DSI_MPPLL_SDM_ISO_EN, |
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RG_DSI_MPPLL_SDM_PWR_ON); |
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0, |
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RG_DSI_MPPLL_PLL_EN); |
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mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0, |
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RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 | |
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RG_DSI_MPPLL_PREDIV, |
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(txdiv0 << 3) | (txdiv1 << 5)); |
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/* |
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* PLL PCW config |
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* PCW bit 24~30 = integer part of pcw |
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* PCW bit 0~23 = fractional part of pcw |
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* pcw = data_Rate*4*txdiv/(Ref_clk*2); |
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* Post DIV =4, so need data_Rate*4 |
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* Ref_clk is 26MHz |
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*/ |
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pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24, |
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26000000); |
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writel(pcw, mipi_tx->regs + MIPITX_DSI_PLL_CON2); |
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mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON1, |
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RG_DSI_MPPLL_SDM_FRA_EN); |
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mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN); |
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usleep_range(20, 100); |
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON1, |
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RG_DSI_MPPLL_SDM_SSC_EN); |
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mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP, |
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RG_DSI_MPPLL_PRESERVE, |
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mipi_tx->driver_data->mppll_preserve); |
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return 0; |
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} |
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static void mtk_mipi_tx_pll_unprepare(struct clk_hw *hw) |
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{ |
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struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); |
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dev_dbg(mipi_tx->dev, "unprepare\n"); |
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0, |
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RG_DSI_MPPLL_PLL_EN); |
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mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP, |
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RG_DSI_MPPLL_PRESERVE, 0); |
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mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR, |
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RG_DSI_MPPLL_SDM_ISO_EN | |
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RG_DSI_MPPLL_SDM_PWR_ON, |
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RG_DSI_MPPLL_SDM_ISO_EN); |
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON, |
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RG_DSI_LNT_HS_BIAS_EN); |
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_CON, |
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RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN); |
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_BG_CON, |
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RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN); |
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0, |
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RG_DSI_MPPLL_DIV_MSK); |
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} |
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static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *prate) |
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{ |
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return clamp_val(rate, 50000000, 1250000000); |
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} |
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static const struct clk_ops mtk_mipi_tx_pll_ops = { |
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.prepare = mtk_mipi_tx_pll_prepare, |
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.unprepare = mtk_mipi_tx_pll_unprepare, |
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.round_rate = mtk_mipi_tx_pll_round_rate, |
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.set_rate = mtk_mipi_tx_pll_set_rate, |
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.recalc_rate = mtk_mipi_tx_pll_recalc_rate, |
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}; |
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static void mtk_mipi_tx_power_on_signal(struct phy *phy) |
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{ |
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struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); |
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u32 reg; |
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for (reg = MIPITX_DSI_CLOCK_LANE; |
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reg <= MIPITX_DSI_DATA_LANE3; reg += 4) |
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mtk_mipi_tx_set_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN); |
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON, |
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RG_DSI_PAD_TIE_LOW_EN); |
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} |
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static void mtk_mipi_tx_power_off_signal(struct phy *phy) |
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{ |
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struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); |
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u32 reg; |
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mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_TOP_CON, |
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RG_DSI_PAD_TIE_LOW_EN); |
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for (reg = MIPITX_DSI_CLOCK_LANE; |
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reg <= MIPITX_DSI_DATA_LANE3; reg += 4) |
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mtk_mipi_tx_clear_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN); |
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} |
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const struct mtk_mipitx_data mt2701_mipitx_data = { |
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.mppll_preserve = (3 << 8), |
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.mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops, |
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.mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal, |
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.mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal, |
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}; |
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const struct mtk_mipitx_data mt8173_mipitx_data = { |
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.mppll_preserve = (0 << 8), |
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.mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops, |
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.mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal, |
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.mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal, |
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};
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