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289 lines
7.7 KiB
289 lines
7.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2011 Marvell International Ltd. All rights reserved. |
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* Copyright (C) 2018,2019 Lubomir Rintel <[email protected]> |
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*/ |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/soc/mmp/cputype.h> |
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#define USB2_PLL_REG0 0x4 |
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#define USB2_PLL_REG1 0x8 |
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#define USB2_TX_REG0 0x10 |
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#define USB2_TX_REG1 0x14 |
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#define USB2_TX_REG2 0x18 |
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#define USB2_RX_REG0 0x20 |
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#define USB2_RX_REG1 0x24 |
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#define USB2_RX_REG2 0x28 |
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#define USB2_ANA_REG0 0x30 |
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#define USB2_ANA_REG1 0x34 |
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#define USB2_ANA_REG2 0x38 |
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#define USB2_DIG_REG0 0x3C |
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#define USB2_DIG_REG1 0x40 |
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#define USB2_DIG_REG2 0x44 |
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#define USB2_DIG_REG3 0x48 |
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#define USB2_TEST_REG0 0x4C |
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#define USB2_TEST_REG1 0x50 |
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#define USB2_TEST_REG2 0x54 |
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#define USB2_CHARGER_REG0 0x58 |
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#define USB2_OTG_REG0 0x5C |
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#define USB2_PHY_MON0 0x60 |
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#define USB2_RESETVE_REG0 0x64 |
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#define USB2_ICID_REG0 0x78 |
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#define USB2_ICID_REG1 0x7C |
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/* USB2_PLL_REG0 */ |
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/* This is for Ax stepping */ |
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#define USB2_PLL_FBDIV_SHIFT_MMP3 0 |
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#define USB2_PLL_FBDIV_MASK_MMP3 (0xFF << 0) |
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#define USB2_PLL_REFDIV_SHIFT_MMP3 8 |
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#define USB2_PLL_REFDIV_MASK_MMP3 (0xF << 8) |
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#define USB2_PLL_VDD12_SHIFT_MMP3 12 |
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#define USB2_PLL_VDD18_SHIFT_MMP3 14 |
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/* This is for B0 stepping */ |
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#define USB2_PLL_FBDIV_SHIFT_MMP3_B0 0 |
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#define USB2_PLL_REFDIV_SHIFT_MMP3_B0 9 |
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#define USB2_PLL_VDD18_SHIFT_MMP3_B0 14 |
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#define USB2_PLL_FBDIV_MASK_MMP3_B0 0x01FF |
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#define USB2_PLL_REFDIV_MASK_MMP3_B0 0x3E00 |
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#define USB2_PLL_CAL12_SHIFT_MMP3 0 |
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#define USB2_PLL_CALI12_MASK_MMP3 (0x3 << 0) |
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#define USB2_PLL_VCOCAL_START_SHIFT_MMP3 2 |
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#define USB2_PLL_KVCO_SHIFT_MMP3 4 |
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#define USB2_PLL_KVCO_MASK_MMP3 (0x7<<4) |
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#define USB2_PLL_ICP_SHIFT_MMP3 8 |
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#define USB2_PLL_ICP_MASK_MMP3 (0x7<<8) |
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#define USB2_PLL_LOCK_BYPASS_SHIFT_MMP3 12 |
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#define USB2_PLL_PU_PLL_SHIFT_MMP3 13 |
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#define USB2_PLL_PU_PLL_MASK (0x1 << 13) |
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#define USB2_PLL_READY_MASK_MMP3 (0x1 << 15) |
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/* USB2_TX_REG0 */ |
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#define USB2_TX_IMPCAL_VTH_SHIFT_MMP3 8 |
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#define USB2_TX_IMPCAL_VTH_MASK_MMP3 (0x7 << 8) |
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#define USB2_TX_RCAL_START_SHIFT_MMP3 13 |
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/* USB2_TX_REG1 */ |
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#define USB2_TX_CK60_PHSEL_SHIFT_MMP3 0 |
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#define USB2_TX_CK60_PHSEL_MASK_MMP3 (0xf << 0) |
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#define USB2_TX_AMP_SHIFT_MMP3 4 |
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#define USB2_TX_AMP_MASK_MMP3 (0x7 << 4) |
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#define USB2_TX_VDD12_SHIFT_MMP3 8 |
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#define USB2_TX_VDD12_MASK_MMP3 (0x3 << 8) |
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/* USB2_TX_REG2 */ |
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#define USB2_TX_DRV_SLEWRATE_SHIFT 10 |
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/* USB2_RX_REG0 */ |
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#define USB2_RX_SQ_THRESH_SHIFT_MMP3 4 |
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#define USB2_RX_SQ_THRESH_MASK_MMP3 (0xf << 4) |
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#define USB2_RX_SQ_LENGTH_SHIFT_MMP3 10 |
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#define USB2_RX_SQ_LENGTH_MASK_MMP3 (0x3 << 10) |
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/* USB2_ANA_REG1*/ |
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#define USB2_ANA_PU_ANA_SHIFT_MMP3 14 |
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/* USB2_OTG_REG0 */ |
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#define USB2_OTG_PU_OTG_SHIFT_MMP3 3 |
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struct mmp3_usb_phy { |
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struct phy *phy; |
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void __iomem *base; |
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}; |
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static unsigned int u2o_get(void __iomem *base, unsigned int offset) |
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{ |
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return readl_relaxed(base + offset); |
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} |
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static void u2o_set(void __iomem *base, unsigned int offset, |
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unsigned int value) |
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{ |
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u32 reg; |
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reg = readl_relaxed(base + offset); |
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reg |= value; |
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writel_relaxed(reg, base + offset); |
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readl_relaxed(base + offset); |
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} |
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static void u2o_clear(void __iomem *base, unsigned int offset, |
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unsigned int value) |
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{ |
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u32 reg; |
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reg = readl_relaxed(base + offset); |
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reg &= ~value; |
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writel_relaxed(reg, base + offset); |
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readl_relaxed(base + offset); |
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} |
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static int mmp3_usb_phy_init(struct phy *phy) |
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{ |
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struct mmp3_usb_phy *mmp3_usb_phy = phy_get_drvdata(phy); |
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void __iomem *base = mmp3_usb_phy->base; |
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if (cpu_is_mmp3_a0()) { |
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u2o_clear(base, USB2_PLL_REG0, (USB2_PLL_FBDIV_MASK_MMP3 |
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| USB2_PLL_REFDIV_MASK_MMP3)); |
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u2o_set(base, USB2_PLL_REG0, |
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0xd << USB2_PLL_REFDIV_SHIFT_MMP3 |
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| 0xf0 << USB2_PLL_FBDIV_SHIFT_MMP3); |
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} else if (cpu_is_mmp3_b0()) { |
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u2o_clear(base, USB2_PLL_REG0, USB2_PLL_REFDIV_MASK_MMP3_B0 |
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| USB2_PLL_FBDIV_MASK_MMP3_B0); |
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u2o_set(base, USB2_PLL_REG0, |
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0xd << USB2_PLL_REFDIV_SHIFT_MMP3_B0 |
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| 0xf0 << USB2_PLL_FBDIV_SHIFT_MMP3_B0); |
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} else { |
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dev_err(&phy->dev, "unsupported silicon revision\n"); |
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return -ENODEV; |
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} |
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u2o_clear(base, USB2_PLL_REG1, USB2_PLL_PU_PLL_MASK |
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| USB2_PLL_ICP_MASK_MMP3 |
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| USB2_PLL_KVCO_MASK_MMP3 |
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| USB2_PLL_CALI12_MASK_MMP3); |
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u2o_set(base, USB2_PLL_REG1, 1 << USB2_PLL_PU_PLL_SHIFT_MMP3 |
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| 1 << USB2_PLL_LOCK_BYPASS_SHIFT_MMP3 |
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| 3 << USB2_PLL_ICP_SHIFT_MMP3 |
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| 3 << USB2_PLL_KVCO_SHIFT_MMP3 |
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| 3 << USB2_PLL_CAL12_SHIFT_MMP3); |
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u2o_clear(base, USB2_TX_REG0, USB2_TX_IMPCAL_VTH_MASK_MMP3); |
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u2o_set(base, USB2_TX_REG0, 2 << USB2_TX_IMPCAL_VTH_SHIFT_MMP3); |
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u2o_clear(base, USB2_TX_REG1, USB2_TX_VDD12_MASK_MMP3 |
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| USB2_TX_AMP_MASK_MMP3 |
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| USB2_TX_CK60_PHSEL_MASK_MMP3); |
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u2o_set(base, USB2_TX_REG1, 3 << USB2_TX_VDD12_SHIFT_MMP3 |
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| 4 << USB2_TX_AMP_SHIFT_MMP3 |
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| 4 << USB2_TX_CK60_PHSEL_SHIFT_MMP3); |
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u2o_clear(base, USB2_TX_REG2, 3 << USB2_TX_DRV_SLEWRATE_SHIFT); |
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u2o_set(base, USB2_TX_REG2, 2 << USB2_TX_DRV_SLEWRATE_SHIFT); |
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u2o_clear(base, USB2_RX_REG0, USB2_RX_SQ_THRESH_MASK_MMP3); |
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u2o_set(base, USB2_RX_REG0, 0xa << USB2_RX_SQ_THRESH_SHIFT_MMP3); |
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u2o_set(base, USB2_ANA_REG1, 0x1 << USB2_ANA_PU_ANA_SHIFT_MMP3); |
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u2o_set(base, USB2_OTG_REG0, 0x1 << USB2_OTG_PU_OTG_SHIFT_MMP3); |
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return 0; |
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} |
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static int mmp3_usb_phy_calibrate(struct phy *phy) |
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{ |
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struct mmp3_usb_phy *mmp3_usb_phy = phy_get_drvdata(phy); |
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void __iomem *base = mmp3_usb_phy->base; |
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int loops; |
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/* |
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* PLL VCO and TX Impedance Calibration Timing: |
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* |
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* _____________________________________ |
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* PU __________| |
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* _____________________________ |
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* VCOCAL START _________| |
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* ___ |
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* REG_RCAL_START ________________| |________|_______ |
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* | 200us | 400us | 40| 400us | USB PHY READY |
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*/ |
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udelay(200); |
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u2o_set(base, USB2_PLL_REG1, 1 << USB2_PLL_VCOCAL_START_SHIFT_MMP3); |
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udelay(400); |
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u2o_set(base, USB2_TX_REG0, 1 << USB2_TX_RCAL_START_SHIFT_MMP3); |
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udelay(40); |
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u2o_clear(base, USB2_TX_REG0, 1 << USB2_TX_RCAL_START_SHIFT_MMP3); |
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udelay(400); |
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loops = 0; |
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while ((u2o_get(base, USB2_PLL_REG1) & USB2_PLL_READY_MASK_MMP3) == 0) { |
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mdelay(1); |
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loops++; |
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if (loops > 100) { |
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dev_err(&phy->dev, "PLL_READY not set after 100mS.\n"); |
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return -ETIMEDOUT; |
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} |
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} |
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return 0; |
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} |
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static const struct phy_ops mmp3_usb_phy_ops = { |
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.init = mmp3_usb_phy_init, |
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.calibrate = mmp3_usb_phy_calibrate, |
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.owner = THIS_MODULE, |
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}; |
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static const struct of_device_id mmp3_usb_phy_of_match[] = { |
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{ .compatible = "marvell,mmp3-usb-phy", }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, mmp3_usb_phy_of_match); |
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static int mmp3_usb_phy_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct mmp3_usb_phy *mmp3_usb_phy; |
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struct phy_provider *provider; |
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mmp3_usb_phy = devm_kzalloc(dev, sizeof(*mmp3_usb_phy), GFP_KERNEL); |
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if (!mmp3_usb_phy) |
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return -ENOMEM; |
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mmp3_usb_phy->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(mmp3_usb_phy->base)) { |
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dev_err(dev, "failed to remap PHY regs\n"); |
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return PTR_ERR(mmp3_usb_phy->base); |
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} |
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mmp3_usb_phy->phy = devm_phy_create(dev, NULL, &mmp3_usb_phy_ops); |
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if (IS_ERR(mmp3_usb_phy->phy)) { |
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dev_err(dev, "failed to create PHY\n"); |
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return PTR_ERR(mmp3_usb_phy->phy); |
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} |
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phy_set_drvdata(mmp3_usb_phy->phy, mmp3_usb_phy); |
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provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
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if (IS_ERR(provider)) { |
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dev_err(dev, "failed to register PHY provider\n"); |
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return PTR_ERR(provider); |
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} |
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return 0; |
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} |
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static struct platform_driver mmp3_usb_phy_driver = { |
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.probe = mmp3_usb_phy_probe, |
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.driver = { |
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.name = "mmp3-usb-phy", |
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.of_match_table = mmp3_usb_phy_of_match, |
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}, |
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}; |
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module_platform_driver(mmp3_usb_phy_driver); |
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MODULE_AUTHOR("Lubomir Rintel <[email protected]>"); |
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MODULE_DESCRIPTION("Marvell MMP3 USB PHY Driver"); |
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MODULE_LICENSE("GPL v2");
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