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270 lines
6.0 KiB
270 lines
6.0 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2018 Russell King, Deep Blue Solutions Ltd. |
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* |
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* Partly derived from CP110 comphy driver by Antoine Tenart |
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* <[email protected]> |
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*/ |
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#include <linux/delay.h> |
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#include <linux/iopoll.h> |
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#include <linux/module.h> |
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#include <linux/phy/phy.h> |
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#include <linux/phy.h> |
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#include <linux/platform_device.h> |
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#define MAX_A38X_COMPHY 6 |
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#define MAX_A38X_PORTS 3 |
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#define COMPHY_CFG1 0x00 |
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#define COMPHY_CFG1_GEN_TX(x) ((x) << 26) |
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#define COMPHY_CFG1_GEN_TX_MSK COMPHY_CFG1_GEN_TX(15) |
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#define COMPHY_CFG1_GEN_RX(x) ((x) << 22) |
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#define COMPHY_CFG1_GEN_RX_MSK COMPHY_CFG1_GEN_RX(15) |
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#define GEN_SGMII_1_25GBPS 6 |
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#define GEN_SGMII_3_125GBPS 8 |
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#define COMPHY_STAT1 0x18 |
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#define COMPHY_STAT1_PLL_RDY_TX BIT(3) |
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#define COMPHY_STAT1_PLL_RDY_RX BIT(2) |
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#define COMPHY_SELECTOR 0xfc |
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struct a38x_comphy; |
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struct a38x_comphy_lane { |
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void __iomem *base; |
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struct a38x_comphy *priv; |
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unsigned int n; |
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int port; |
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}; |
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struct a38x_comphy { |
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void __iomem *base; |
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void __iomem *conf; |
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struct device *dev; |
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struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; |
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}; |
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static const u8 gbe_mux[MAX_A38X_COMPHY][MAX_A38X_PORTS] = { |
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{ 0, 0, 0 }, |
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{ 4, 5, 0 }, |
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{ 0, 4, 0 }, |
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{ 0, 0, 4 }, |
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{ 0, 3, 0 }, |
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{ 0, 0, 3 }, |
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}; |
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static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) |
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{ |
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struct a38x_comphy *priv = lane->priv; |
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u32 conf; |
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if (priv->conf) { |
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conf = readl_relaxed(priv->conf); |
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if (enable) |
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conf |= BIT(lane->port); |
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else |
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conf &= ~BIT(lane->port); |
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writel(conf, priv->conf); |
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} |
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} |
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static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane, |
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unsigned int offset, u32 mask, u32 value) |
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{ |
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u32 val; |
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val = readl_relaxed(lane->base + offset) & ~mask; |
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writel(val | value, lane->base + offset); |
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} |
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static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane, |
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unsigned int gen_tx, unsigned int gen_rx) |
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{ |
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a38x_comphy_set_reg(lane, COMPHY_CFG1, |
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COMPHY_CFG1_GEN_TX_MSK | COMPHY_CFG1_GEN_RX_MSK, |
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COMPHY_CFG1_GEN_TX(gen_tx) | |
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COMPHY_CFG1_GEN_RX(gen_rx)); |
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} |
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static int a38x_comphy_poll(struct a38x_comphy_lane *lane, |
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unsigned int offset, u32 mask, u32 value) |
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{ |
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u32 val; |
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int ret; |
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ret = readl_relaxed_poll_timeout_atomic(lane->base + offset, val, |
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(val & mask) == value, |
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1000, 150000); |
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if (ret) |
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dev_err(lane->priv->dev, |
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"comphy%u: timed out waiting for status\n", lane->n); |
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return ret; |
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} |
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/* |
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* We only support changing the speed for comphys configured for GBE. |
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* Since that is all we do, we only poll for PLL ready status. |
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*/ |
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static int a38x_comphy_set_mode(struct phy *phy, enum phy_mode mode, int sub) |
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{ |
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struct a38x_comphy_lane *lane = phy_get_drvdata(phy); |
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unsigned int gen; |
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int ret; |
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if (mode != PHY_MODE_ETHERNET) |
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return -EINVAL; |
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switch (sub) { |
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case PHY_INTERFACE_MODE_SGMII: |
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case PHY_INTERFACE_MODE_1000BASEX: |
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gen = GEN_SGMII_1_25GBPS; |
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break; |
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case PHY_INTERFACE_MODE_2500BASEX: |
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gen = GEN_SGMII_3_125GBPS; |
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break; |
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default: |
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return -EINVAL; |
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} |
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a38x_set_conf(lane, false); |
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a38x_comphy_set_speed(lane, gen, gen); |
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ret = a38x_comphy_poll(lane, COMPHY_STAT1, |
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COMPHY_STAT1_PLL_RDY_TX | |
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COMPHY_STAT1_PLL_RDY_RX, |
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COMPHY_STAT1_PLL_RDY_TX | |
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COMPHY_STAT1_PLL_RDY_RX); |
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if (ret == 0) |
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a38x_set_conf(lane, true); |
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return ret; |
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} |
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static const struct phy_ops a38x_comphy_ops = { |
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.set_mode = a38x_comphy_set_mode, |
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.owner = THIS_MODULE, |
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}; |
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static struct phy *a38x_comphy_xlate(struct device *dev, |
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struct of_phandle_args *args) |
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{ |
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struct a38x_comphy_lane *lane; |
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struct phy *phy; |
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u32 val; |
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if (WARN_ON(args->args[0] >= MAX_A38X_PORTS)) |
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return ERR_PTR(-EINVAL); |
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phy = of_phy_simple_xlate(dev, args); |
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if (IS_ERR(phy)) |
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return phy; |
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lane = phy_get_drvdata(phy); |
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if (lane->port >= 0) |
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return ERR_PTR(-EBUSY); |
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lane->port = args->args[0]; |
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val = readl_relaxed(lane->priv->base + COMPHY_SELECTOR); |
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val = (val >> (4 * lane->n)) & 0xf; |
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if (!gbe_mux[lane->n][lane->port] || |
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val != gbe_mux[lane->n][lane->port]) { |
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dev_warn(lane->priv->dev, |
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"comphy%u: not configured for GBE\n", lane->n); |
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phy = ERR_PTR(-EINVAL); |
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} |
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return phy; |
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} |
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static int a38x_comphy_probe(struct platform_device *pdev) |
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{ |
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struct phy_provider *provider; |
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struct device_node *child; |
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struct a38x_comphy *priv; |
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struct resource *res; |
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void __iomem *base; |
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(base)) |
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return PTR_ERR(base); |
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priv->dev = &pdev->dev; |
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priv->base = base; |
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/* Optional */ |
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "conf"); |
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if (res) { |
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priv->conf = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(priv->conf)) |
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return PTR_ERR(priv->conf); |
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} |
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for_each_available_child_of_node(pdev->dev.of_node, child) { |
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struct phy *phy; |
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int ret; |
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u32 val; |
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ret = of_property_read_u32(child, "reg", &val); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "missing 'reg' property (%d)\n", |
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ret); |
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continue; |
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} |
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if (val >= MAX_A38X_COMPHY || priv->lane[val].base) { |
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dev_err(&pdev->dev, "invalid 'reg' property\n"); |
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continue; |
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} |
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phy = devm_phy_create(&pdev->dev, child, &a38x_comphy_ops); |
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if (IS_ERR(phy)) { |
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of_node_put(child); |
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return PTR_ERR(phy); |
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} |
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priv->lane[val].base = base + 0x28 * val; |
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priv->lane[val].priv = priv; |
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priv->lane[val].n = val; |
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priv->lane[val].port = -1; |
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phy_set_drvdata(phy, &priv->lane[val]); |
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} |
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dev_set_drvdata(&pdev->dev, priv); |
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provider = devm_of_phy_provider_register(&pdev->dev, a38x_comphy_xlate); |
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return PTR_ERR_OR_ZERO(provider); |
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} |
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static const struct of_device_id a38x_comphy_of_match_table[] = { |
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{ .compatible = "marvell,armada-380-comphy" }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, a38x_comphy_of_match_table); |
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static struct platform_driver a38x_comphy_driver = { |
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.probe = a38x_comphy_probe, |
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.driver = { |
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.name = "armada-38x-comphy", |
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.of_match_table = a38x_comphy_of_match_table, |
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}, |
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}; |
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module_platform_driver(a38x_comphy_driver); |
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MODULE_AUTHOR("Russell King <[email protected]>"); |
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MODULE_DESCRIPTION("Common PHY driver for Armada 38x SoCs"); |
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MODULE_LICENSE("GPL v2");
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