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495 lines
12 KiB
495 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright 2017,2018 NXP |
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* Copyright 2019 Purism SPC |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_platform.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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/* DPHY registers */ |
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#define DPHY_PD_DPHY 0x00 |
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#define DPHY_M_PRG_HS_PREPARE 0x04 |
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#define DPHY_MC_PRG_HS_PREPARE 0x08 |
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#define DPHY_M_PRG_HS_ZERO 0x0c |
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#define DPHY_MC_PRG_HS_ZERO 0x10 |
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#define DPHY_M_PRG_HS_TRAIL 0x14 |
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#define DPHY_MC_PRG_HS_TRAIL 0x18 |
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#define DPHY_PD_PLL 0x1c |
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#define DPHY_TST 0x20 |
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#define DPHY_CN 0x24 |
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#define DPHY_CM 0x28 |
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#define DPHY_CO 0x2c |
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#define DPHY_LOCK 0x30 |
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#define DPHY_LOCK_BYP 0x34 |
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#define DPHY_REG_BYPASS_PLL 0x4C |
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#define MBPS(x) ((x) * 1000000) |
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#define DATA_RATE_MAX_SPEED MBPS(1500) |
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#define DATA_RATE_MIN_SPEED MBPS(80) |
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#define PLL_LOCK_SLEEP 10 |
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#define PLL_LOCK_TIMEOUT 1000 |
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#define CN_BUF 0xcb7a89c0 |
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#define CO_BUF 0x63 |
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#define CM(x) ( \ |
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((x) < 32) ? 0xe0 | ((x) - 16) : \ |
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((x) < 64) ? 0xc0 | ((x) - 32) : \ |
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((x) < 128) ? 0x80 | ((x) - 64) : \ |
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((x) - 128)) |
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#define CN(x) (((x) == 1) ? 0x1f : (((CN_BUF) >> ((x) - 1)) & 0x1f)) |
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#define CO(x) ((CO_BUF) >> (8 - (x)) & 0x03) |
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/* PHY power on is active low */ |
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#define PWR_ON 0 |
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#define PWR_OFF 1 |
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enum mixel_dphy_devtype { |
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MIXEL_IMX8MQ, |
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}; |
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struct mixel_dphy_devdata { |
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u8 reg_tx_rcal; |
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u8 reg_auto_pd_en; |
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u8 reg_rxlprp; |
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u8 reg_rxcdrp; |
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u8 reg_rxhs_settle; |
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}; |
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static const struct mixel_dphy_devdata mixel_dphy_devdata[] = { |
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[MIXEL_IMX8MQ] = { |
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.reg_tx_rcal = 0x38, |
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.reg_auto_pd_en = 0x3c, |
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.reg_rxlprp = 0x40, |
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.reg_rxcdrp = 0x44, |
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.reg_rxhs_settle = 0x48, |
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}, |
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}; |
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struct mixel_dphy_cfg { |
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/* DPHY PLL parameters */ |
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u32 cm; |
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u32 cn; |
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u32 co; |
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/* DPHY register values */ |
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u8 mc_prg_hs_prepare; |
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u8 m_prg_hs_prepare; |
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u8 mc_prg_hs_zero; |
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u8 m_prg_hs_zero; |
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u8 mc_prg_hs_trail; |
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u8 m_prg_hs_trail; |
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u8 rxhs_settle; |
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}; |
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struct mixel_dphy_priv { |
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struct mixel_dphy_cfg cfg; |
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struct regmap *regmap; |
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struct clk *phy_ref_clk; |
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const struct mixel_dphy_devdata *devdata; |
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}; |
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static const struct regmap_config mixel_dphy_regmap_config = { |
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.reg_bits = 8, |
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.val_bits = 32, |
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.reg_stride = 4, |
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.max_register = DPHY_REG_BYPASS_PLL, |
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.name = "mipi-dphy", |
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}; |
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static int phy_write(struct phy *phy, u32 value, unsigned int reg) |
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{ |
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struct mixel_dphy_priv *priv = phy_get_drvdata(phy); |
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int ret; |
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ret = regmap_write(priv->regmap, reg, value); |
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if (ret < 0) |
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dev_err(&phy->dev, "Failed to write DPHY reg %d: %d\n", reg, |
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ret); |
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return ret; |
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} |
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/* |
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* Find a ratio close to the desired one using continued fraction |
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* approximation ending either at exact match or maximum allowed |
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* nominator, denominator. |
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*/ |
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static void get_best_ratio(u32 *pnum, u32 *pdenom, u32 max_n, u32 max_d) |
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{ |
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u32 a = *pnum; |
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u32 b = *pdenom; |
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u32 c; |
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u32 n[] = {0, 1}; |
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u32 d[] = {1, 0}; |
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u32 whole; |
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unsigned int i = 1; |
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while (b) { |
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i ^= 1; |
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whole = a / b; |
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n[i] += (n[i ^ 1] * whole); |
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d[i] += (d[i ^ 1] * whole); |
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if ((n[i] > max_n) || (d[i] > max_d)) { |
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i ^= 1; |
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break; |
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} |
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c = a - (b * whole); |
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a = b; |
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b = c; |
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} |
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*pnum = n[i]; |
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*pdenom = d[i]; |
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} |
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static int mixel_dphy_config_from_opts(struct phy *phy, |
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struct phy_configure_opts_mipi_dphy *dphy_opts, |
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struct mixel_dphy_cfg *cfg) |
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{ |
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struct mixel_dphy_priv *priv = dev_get_drvdata(phy->dev.parent); |
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unsigned long ref_clk = clk_get_rate(priv->phy_ref_clk); |
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u32 lp_t, numerator, denominator; |
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unsigned long long tmp; |
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u32 n; |
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int i; |
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if (dphy_opts->hs_clk_rate > DATA_RATE_MAX_SPEED || |
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dphy_opts->hs_clk_rate < DATA_RATE_MIN_SPEED) |
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return -EINVAL; |
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numerator = dphy_opts->hs_clk_rate; |
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denominator = ref_clk; |
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get_best_ratio(&numerator, &denominator, 255, 256); |
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if (!numerator || !denominator) { |
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dev_err(&phy->dev, "Invalid %d/%d for %ld/%ld\n", |
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numerator, denominator, |
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dphy_opts->hs_clk_rate, ref_clk); |
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return -EINVAL; |
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} |
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while ((numerator < 16) && (denominator <= 128)) { |
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numerator <<= 1; |
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denominator <<= 1; |
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} |
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/* |
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* CM ranges between 16 and 255 |
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* CN ranges between 1 and 32 |
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* CO is power of 2: 1, 2, 4, 8 |
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*/ |
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i = __ffs(denominator); |
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if (i > 3) |
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i = 3; |
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cfg->cn = denominator >> i; |
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cfg->co = 1 << i; |
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cfg->cm = numerator; |
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if (cfg->cm < 16 || cfg->cm > 255 || |
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cfg->cn < 1 || cfg->cn > 32 || |
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cfg->co < 1 || cfg->co > 8) { |
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dev_err(&phy->dev, "Invalid CM/CN/CO values: %u/%u/%u\n", |
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cfg->cm, cfg->cn, cfg->co); |
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dev_err(&phy->dev, "for hs_clk/ref_clk=%ld/%ld ~ %d/%d\n", |
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dphy_opts->hs_clk_rate, ref_clk, |
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numerator, denominator); |
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return -EINVAL; |
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} |
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dev_dbg(&phy->dev, "hs_clk/ref_clk=%ld/%ld ~ %d/%d\n", |
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dphy_opts->hs_clk_rate, ref_clk, numerator, denominator); |
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/* LP clock period */ |
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tmp = 1000000000000LL; |
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do_div(tmp, dphy_opts->lp_clk_rate); /* ps */ |
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if (tmp > ULONG_MAX) |
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return -EINVAL; |
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lp_t = tmp; |
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dev_dbg(&phy->dev, "LP clock %lu, period: %u ps\n", |
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dphy_opts->lp_clk_rate, lp_t); |
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/* hs_prepare: in lp clock periods */ |
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if (2 * dphy_opts->hs_prepare > 5 * lp_t) { |
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dev_err(&phy->dev, |
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"hs_prepare (%u) > 2.5 * lp clock period (%u)\n", |
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dphy_opts->hs_prepare, lp_t); |
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return -EINVAL; |
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} |
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/* 00: lp_t, 01: 1.5 * lp_t, 10: 2 * lp_t, 11: 2.5 * lp_t */ |
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if (dphy_opts->hs_prepare < lp_t) { |
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n = 0; |
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} else { |
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tmp = 2 * (dphy_opts->hs_prepare - lp_t); |
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do_div(tmp, lp_t); |
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n = tmp; |
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} |
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cfg->m_prg_hs_prepare = n; |
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/* clk_prepare: in lp clock periods */ |
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if (2 * dphy_opts->clk_prepare > 3 * lp_t) { |
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dev_err(&phy->dev, |
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"clk_prepare (%u) > 1.5 * lp clock period (%u)\n", |
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dphy_opts->clk_prepare, lp_t); |
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return -EINVAL; |
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} |
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/* 00: lp_t, 01: 1.5 * lp_t */ |
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cfg->mc_prg_hs_prepare = dphy_opts->clk_prepare > lp_t ? 1 : 0; |
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/* hs_zero: formula from NXP BSP */ |
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n = (144 * (dphy_opts->hs_clk_rate / 1000000) - 47500) / 10000; |
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cfg->m_prg_hs_zero = n < 1 ? 1 : n; |
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/* clk_zero: formula from NXP BSP */ |
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n = (34 * (dphy_opts->hs_clk_rate / 1000000) - 2500) / 1000; |
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cfg->mc_prg_hs_zero = n < 1 ? 1 : n; |
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/* clk_trail, hs_trail: formula from NXP BSP */ |
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n = (103 * (dphy_opts->hs_clk_rate / 1000000) + 10000) / 10000; |
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if (n > 15) |
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n = 15; |
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if (n < 1) |
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n = 1; |
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cfg->m_prg_hs_trail = n; |
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cfg->mc_prg_hs_trail = n; |
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/* rxhs_settle: formula from NXP BSP */ |
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if (dphy_opts->hs_clk_rate < MBPS(80)) |
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cfg->rxhs_settle = 0x0d; |
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else if (dphy_opts->hs_clk_rate < MBPS(90)) |
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cfg->rxhs_settle = 0x0c; |
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else if (dphy_opts->hs_clk_rate < MBPS(125)) |
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cfg->rxhs_settle = 0x0b; |
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else if (dphy_opts->hs_clk_rate < MBPS(150)) |
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cfg->rxhs_settle = 0x0a; |
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else if (dphy_opts->hs_clk_rate < MBPS(225)) |
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cfg->rxhs_settle = 0x09; |
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else if (dphy_opts->hs_clk_rate < MBPS(500)) |
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cfg->rxhs_settle = 0x08; |
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else |
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cfg->rxhs_settle = 0x07; |
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dev_dbg(&phy->dev, "phy_config: %u %u %u %u %u %u %u\n", |
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cfg->m_prg_hs_prepare, cfg->mc_prg_hs_prepare, |
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cfg->m_prg_hs_zero, cfg->mc_prg_hs_zero, |
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cfg->m_prg_hs_trail, cfg->mc_prg_hs_trail, |
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cfg->rxhs_settle); |
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return 0; |
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} |
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static void mixel_phy_set_hs_timings(struct phy *phy) |
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{ |
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struct mixel_dphy_priv *priv = phy_get_drvdata(phy); |
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phy_write(phy, priv->cfg.m_prg_hs_prepare, DPHY_M_PRG_HS_PREPARE); |
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phy_write(phy, priv->cfg.mc_prg_hs_prepare, DPHY_MC_PRG_HS_PREPARE); |
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phy_write(phy, priv->cfg.m_prg_hs_zero, DPHY_M_PRG_HS_ZERO); |
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phy_write(phy, priv->cfg.mc_prg_hs_zero, DPHY_MC_PRG_HS_ZERO); |
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phy_write(phy, priv->cfg.m_prg_hs_trail, DPHY_M_PRG_HS_TRAIL); |
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phy_write(phy, priv->cfg.mc_prg_hs_trail, DPHY_MC_PRG_HS_TRAIL); |
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phy_write(phy, priv->cfg.rxhs_settle, priv->devdata->reg_rxhs_settle); |
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} |
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static int mixel_dphy_set_pll_params(struct phy *phy) |
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{ |
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struct mixel_dphy_priv *priv = dev_get_drvdata(phy->dev.parent); |
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if (priv->cfg.cm < 16 || priv->cfg.cm > 255 || |
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priv->cfg.cn < 1 || priv->cfg.cn > 32 || |
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priv->cfg.co < 1 || priv->cfg.co > 8) { |
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dev_err(&phy->dev, "Invalid CM/CN/CO values! (%u/%u/%u)\n", |
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priv->cfg.cm, priv->cfg.cn, priv->cfg.co); |
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return -EINVAL; |
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} |
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dev_dbg(&phy->dev, "Using CM:%u CN:%u CO:%u\n", |
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priv->cfg.cm, priv->cfg.cn, priv->cfg.co); |
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phy_write(phy, CM(priv->cfg.cm), DPHY_CM); |
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phy_write(phy, CN(priv->cfg.cn), DPHY_CN); |
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phy_write(phy, CO(priv->cfg.co), DPHY_CO); |
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return 0; |
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} |
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static int mixel_dphy_configure(struct phy *phy, union phy_configure_opts *opts) |
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{ |
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struct mixel_dphy_priv *priv = phy_get_drvdata(phy); |
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struct mixel_dphy_cfg cfg = { 0 }; |
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int ret; |
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ret = mixel_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg); |
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if (ret) |
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return ret; |
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/* Update the configuration */ |
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memcpy(&priv->cfg, &cfg, sizeof(struct mixel_dphy_cfg)); |
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phy_write(phy, 0x00, DPHY_LOCK_BYP); |
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phy_write(phy, 0x01, priv->devdata->reg_tx_rcal); |
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phy_write(phy, 0x00, priv->devdata->reg_auto_pd_en); |
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phy_write(phy, 0x02, priv->devdata->reg_rxlprp); |
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phy_write(phy, 0x02, priv->devdata->reg_rxcdrp); |
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phy_write(phy, 0x25, DPHY_TST); |
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mixel_phy_set_hs_timings(phy); |
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ret = mixel_dphy_set_pll_params(phy); |
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if (ret < 0) |
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return ret; |
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return 0; |
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} |
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static int mixel_dphy_validate(struct phy *phy, enum phy_mode mode, int submode, |
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union phy_configure_opts *opts) |
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{ |
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struct mixel_dphy_cfg cfg = { 0 }; |
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if (mode != PHY_MODE_MIPI_DPHY) |
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return -EINVAL; |
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return mixel_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg); |
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} |
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static int mixel_dphy_init(struct phy *phy) |
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{ |
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phy_write(phy, PWR_OFF, DPHY_PD_PLL); |
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phy_write(phy, PWR_OFF, DPHY_PD_DPHY); |
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return 0; |
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} |
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static int mixel_dphy_exit(struct phy *phy) |
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{ |
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phy_write(phy, 0, DPHY_CM); |
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phy_write(phy, 0, DPHY_CN); |
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phy_write(phy, 0, DPHY_CO); |
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return 0; |
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} |
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static int mixel_dphy_power_on(struct phy *phy) |
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{ |
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struct mixel_dphy_priv *priv = phy_get_drvdata(phy); |
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u32 locked; |
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int ret; |
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ret = clk_prepare_enable(priv->phy_ref_clk); |
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if (ret < 0) |
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return ret; |
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phy_write(phy, PWR_ON, DPHY_PD_PLL); |
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ret = regmap_read_poll_timeout(priv->regmap, DPHY_LOCK, locked, |
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locked, PLL_LOCK_SLEEP, |
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PLL_LOCK_TIMEOUT); |
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if (ret < 0) { |
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dev_err(&phy->dev, "Could not get DPHY lock (%d)!\n", ret); |
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goto clock_disable; |
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} |
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phy_write(phy, PWR_ON, DPHY_PD_DPHY); |
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return 0; |
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clock_disable: |
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clk_disable_unprepare(priv->phy_ref_clk); |
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return ret; |
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} |
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static int mixel_dphy_power_off(struct phy *phy) |
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{ |
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struct mixel_dphy_priv *priv = phy_get_drvdata(phy); |
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phy_write(phy, PWR_OFF, DPHY_PD_PLL); |
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phy_write(phy, PWR_OFF, DPHY_PD_DPHY); |
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clk_disable_unprepare(priv->phy_ref_clk); |
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return 0; |
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} |
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static const struct phy_ops mixel_dphy_phy_ops = { |
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.init = mixel_dphy_init, |
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.exit = mixel_dphy_exit, |
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.power_on = mixel_dphy_power_on, |
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.power_off = mixel_dphy_power_off, |
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.configure = mixel_dphy_configure, |
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.validate = mixel_dphy_validate, |
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.owner = THIS_MODULE, |
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}; |
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static const struct of_device_id mixel_dphy_of_match[] = { |
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{ .compatible = "fsl,imx8mq-mipi-dphy", |
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.data = &mixel_dphy_devdata[MIXEL_IMX8MQ] }, |
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{ /* sentinel */ }, |
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}; |
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MODULE_DEVICE_TABLE(of, mixel_dphy_of_match); |
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static int mixel_dphy_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct device_node *np = dev->of_node; |
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struct phy_provider *phy_provider; |
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struct mixel_dphy_priv *priv; |
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struct phy *phy; |
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void __iomem *base; |
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if (!np) |
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return -ENODEV; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->devdata = of_device_get_match_data(&pdev->dev); |
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if (!priv->devdata) |
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return -EINVAL; |
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base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(base)) |
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return PTR_ERR(base); |
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priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, |
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&mixel_dphy_regmap_config); |
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if (IS_ERR(priv->regmap)) { |
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dev_err(dev, "Couldn't create the DPHY regmap\n"); |
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return PTR_ERR(priv->regmap); |
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} |
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priv->phy_ref_clk = devm_clk_get(&pdev->dev, "phy_ref"); |
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if (IS_ERR(priv->phy_ref_clk)) { |
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dev_err(dev, "No phy_ref clock found\n"); |
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return PTR_ERR(priv->phy_ref_clk); |
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} |
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dev_dbg(dev, "phy_ref clock rate: %lu\n", |
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clk_get_rate(priv->phy_ref_clk)); |
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dev_set_drvdata(dev, priv); |
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phy = devm_phy_create(dev, np, &mixel_dphy_phy_ops); |
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if (IS_ERR(phy)) { |
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dev_err(dev, "Failed to create phy %ld\n", PTR_ERR(phy)); |
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return PTR_ERR(phy); |
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} |
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phy_set_drvdata(phy, priv); |
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
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return PTR_ERR_OR_ZERO(phy_provider); |
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} |
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static struct platform_driver mixel_dphy_driver = { |
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.probe = mixel_dphy_probe, |
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.driver = { |
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.name = "mixel-mipi-dphy", |
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.of_match_table = mixel_dphy_of_match, |
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} |
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}; |
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module_platform_driver(mixel_dphy_driver); |
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MODULE_AUTHOR("NXP Semiconductor"); |
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MODULE_DESCRIPTION("Mixel MIPI-DSI PHY driver"); |
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MODULE_LICENSE("GPL");
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