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554 lines
12 KiB
554 lines
12 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* Copyright(c) 2007 - 2018 Intel Corporation. */ |
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#ifndef _E1000_IGB_HW_H_ |
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#define _E1000_IGB_HW_H_ |
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#include <linux/types.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/netdevice.h> |
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#include "e1000_regs.h" |
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#include "e1000_defines.h" |
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struct e1000_hw; |
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#define E1000_DEV_ID_82576 0x10C9 |
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#define E1000_DEV_ID_82576_FIBER 0x10E6 |
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#define E1000_DEV_ID_82576_SERDES 0x10E7 |
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#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 |
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#define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 |
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#define E1000_DEV_ID_82576_NS 0x150A |
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#define E1000_DEV_ID_82576_NS_SERDES 0x1518 |
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#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D |
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#define E1000_DEV_ID_82575EB_COPPER 0x10A7 |
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#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 |
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#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 |
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#define E1000_DEV_ID_82580_COPPER 0x150E |
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#define E1000_DEV_ID_82580_FIBER 0x150F |
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#define E1000_DEV_ID_82580_SERDES 0x1510 |
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#define E1000_DEV_ID_82580_SGMII 0x1511 |
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#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 |
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#define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 |
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#define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 |
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#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A |
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#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C |
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#define E1000_DEV_ID_DH89XXCC_SFP 0x0440 |
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#define E1000_DEV_ID_I350_COPPER 0x1521 |
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#define E1000_DEV_ID_I350_FIBER 0x1522 |
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#define E1000_DEV_ID_I350_SERDES 0x1523 |
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#define E1000_DEV_ID_I350_SGMII 0x1524 |
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#define E1000_DEV_ID_I210_COPPER 0x1533 |
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#define E1000_DEV_ID_I210_FIBER 0x1536 |
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#define E1000_DEV_ID_I210_SERDES 0x1537 |
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#define E1000_DEV_ID_I210_SGMII 0x1538 |
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#define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B |
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#define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C |
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#define E1000_DEV_ID_I211_COPPER 0x1539 |
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#define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 |
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#define E1000_DEV_ID_I354_SGMII 0x1F41 |
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#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 |
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#define E1000_REVISION_2 2 |
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#define E1000_REVISION_4 4 |
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#define E1000_FUNC_0 0 |
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#define E1000_FUNC_1 1 |
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#define E1000_FUNC_2 2 |
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#define E1000_FUNC_3 3 |
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#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 |
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#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 |
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#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 |
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#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 |
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enum e1000_mac_type { |
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e1000_undefined = 0, |
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e1000_82575, |
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e1000_82576, |
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e1000_82580, |
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e1000_i350, |
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e1000_i354, |
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e1000_i210, |
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e1000_i211, |
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e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ |
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}; |
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enum e1000_media_type { |
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e1000_media_type_unknown = 0, |
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e1000_media_type_copper = 1, |
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e1000_media_type_fiber = 2, |
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e1000_media_type_internal_serdes = 3, |
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e1000_num_media_types |
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}; |
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enum e1000_nvm_type { |
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e1000_nvm_unknown = 0, |
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e1000_nvm_none, |
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e1000_nvm_eeprom_spi, |
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e1000_nvm_flash_hw, |
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e1000_nvm_invm, |
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e1000_nvm_flash_sw |
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}; |
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enum e1000_nvm_override { |
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e1000_nvm_override_none = 0, |
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e1000_nvm_override_spi_small, |
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e1000_nvm_override_spi_large, |
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}; |
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enum e1000_phy_type { |
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e1000_phy_unknown = 0, |
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e1000_phy_none, |
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e1000_phy_m88, |
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e1000_phy_igp, |
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e1000_phy_igp_2, |
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e1000_phy_gg82563, |
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e1000_phy_igp_3, |
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e1000_phy_ife, |
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e1000_phy_82580, |
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e1000_phy_i210, |
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e1000_phy_bcm54616, |
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}; |
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enum e1000_bus_type { |
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e1000_bus_type_unknown = 0, |
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e1000_bus_type_pci, |
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e1000_bus_type_pcix, |
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e1000_bus_type_pci_express, |
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e1000_bus_type_reserved |
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}; |
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enum e1000_bus_speed { |
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e1000_bus_speed_unknown = 0, |
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e1000_bus_speed_33, |
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e1000_bus_speed_66, |
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e1000_bus_speed_100, |
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e1000_bus_speed_120, |
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e1000_bus_speed_133, |
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e1000_bus_speed_2500, |
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e1000_bus_speed_5000, |
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e1000_bus_speed_reserved |
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}; |
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enum e1000_bus_width { |
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e1000_bus_width_unknown = 0, |
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e1000_bus_width_pcie_x1, |
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e1000_bus_width_pcie_x2, |
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e1000_bus_width_pcie_x4 = 4, |
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e1000_bus_width_pcie_x8 = 8, |
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e1000_bus_width_32, |
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e1000_bus_width_64, |
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e1000_bus_width_reserved |
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}; |
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enum e1000_1000t_rx_status { |
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e1000_1000t_rx_status_not_ok = 0, |
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e1000_1000t_rx_status_ok, |
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e1000_1000t_rx_status_undefined = 0xFF |
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}; |
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enum e1000_rev_polarity { |
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e1000_rev_polarity_normal = 0, |
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e1000_rev_polarity_reversed, |
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e1000_rev_polarity_undefined = 0xFF |
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}; |
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enum e1000_fc_mode { |
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e1000_fc_none = 0, |
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e1000_fc_rx_pause, |
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e1000_fc_tx_pause, |
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e1000_fc_full, |
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e1000_fc_default = 0xFF |
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}; |
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/* Statistics counters collected by the MAC */ |
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struct e1000_hw_stats { |
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u64 crcerrs; |
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u64 algnerrc; |
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u64 symerrs; |
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u64 rxerrc; |
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u64 mpc; |
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u64 scc; |
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u64 ecol; |
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u64 mcc; |
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u64 latecol; |
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u64 colc; |
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u64 dc; |
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u64 tncrs; |
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u64 sec; |
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u64 cexterr; |
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u64 rlec; |
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u64 xonrxc; |
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u64 xontxc; |
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u64 xoffrxc; |
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u64 xofftxc; |
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u64 fcruc; |
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u64 prc64; |
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u64 prc127; |
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u64 prc255; |
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u64 prc511; |
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u64 prc1023; |
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u64 prc1522; |
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u64 gprc; |
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u64 bprc; |
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u64 mprc; |
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u64 gptc; |
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u64 gorc; |
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u64 gotc; |
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u64 rnbc; |
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u64 ruc; |
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u64 rfc; |
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u64 roc; |
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u64 rjc; |
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u64 mgprc; |
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u64 mgpdc; |
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u64 mgptc; |
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u64 tor; |
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u64 tot; |
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u64 tpr; |
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u64 tpt; |
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u64 ptc64; |
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u64 ptc127; |
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u64 ptc255; |
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u64 ptc511; |
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u64 ptc1023; |
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u64 ptc1522; |
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u64 mptc; |
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u64 bptc; |
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u64 tsctc; |
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u64 tsctfc; |
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u64 iac; |
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u64 icrxptc; |
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u64 icrxatc; |
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u64 ictxptc; |
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u64 ictxatc; |
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u64 ictxqec; |
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u64 ictxqmtc; |
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u64 icrxdmtc; |
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u64 icrxoc; |
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u64 cbtmpc; |
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u64 htdpmc; |
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u64 cbrdpc; |
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u64 cbrmpc; |
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u64 rpthc; |
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u64 hgptc; |
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u64 htcbdpc; |
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u64 hgorc; |
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u64 hgotc; |
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u64 lenerrs; |
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u64 scvpc; |
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u64 hrmpc; |
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u64 doosync; |
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u64 o2bgptc; |
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u64 o2bspc; |
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u64 b2ospc; |
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u64 b2ogprc; |
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}; |
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struct e1000_host_mng_dhcp_cookie { |
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u32 signature; |
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u8 status; |
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u8 reserved0; |
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u16 vlan_id; |
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u32 reserved1; |
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u16 reserved2; |
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u8 reserved3; |
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u8 checksum; |
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}; |
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/* Host Interface "Rev 1" */ |
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struct e1000_host_command_header { |
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u8 command_id; |
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u8 command_length; |
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u8 command_options; |
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u8 checksum; |
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}; |
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#define E1000_HI_MAX_DATA_LENGTH 252 |
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struct e1000_host_command_info { |
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struct e1000_host_command_header command_header; |
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u8 command_data[E1000_HI_MAX_DATA_LENGTH]; |
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}; |
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/* Host Interface "Rev 2" */ |
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struct e1000_host_mng_command_header { |
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u8 command_id; |
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u8 checksum; |
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u16 reserved1; |
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u16 reserved2; |
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u16 command_length; |
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}; |
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#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 |
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struct e1000_host_mng_command_info { |
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struct e1000_host_mng_command_header command_header; |
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u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; |
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}; |
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#include "e1000_mac.h" |
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#include "e1000_phy.h" |
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#include "e1000_nvm.h" |
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#include "e1000_mbx.h" |
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struct e1000_mac_operations { |
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s32 (*check_for_link)(struct e1000_hw *); |
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s32 (*reset_hw)(struct e1000_hw *); |
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s32 (*init_hw)(struct e1000_hw *); |
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bool (*check_mng_mode)(struct e1000_hw *); |
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s32 (*setup_physical_interface)(struct e1000_hw *); |
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void (*rar_set)(struct e1000_hw *, u8 *, u32); |
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s32 (*read_mac_addr)(struct e1000_hw *); |
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s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *); |
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s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); |
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void (*release_swfw_sync)(struct e1000_hw *, u16); |
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#ifdef CONFIG_IGB_HWMON |
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s32 (*get_thermal_sensor_data)(struct e1000_hw *); |
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s32 (*init_thermal_sensor_thresh)(struct e1000_hw *); |
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#endif |
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void (*write_vfta)(struct e1000_hw *, u32, u32); |
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}; |
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struct e1000_phy_operations { |
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s32 (*acquire)(struct e1000_hw *); |
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s32 (*check_polarity)(struct e1000_hw *); |
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s32 (*check_reset_block)(struct e1000_hw *); |
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s32 (*force_speed_duplex)(struct e1000_hw *); |
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s32 (*get_cfg_done)(struct e1000_hw *hw); |
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s32 (*get_cable_length)(struct e1000_hw *); |
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s32 (*get_phy_info)(struct e1000_hw *); |
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s32 (*read_reg)(struct e1000_hw *, u32, u16 *); |
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void (*release)(struct e1000_hw *); |
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s32 (*reset)(struct e1000_hw *); |
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s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); |
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s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); |
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s32 (*write_reg)(struct e1000_hw *, u32, u16); |
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s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); |
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s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); |
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}; |
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struct e1000_nvm_operations { |
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s32 (*acquire)(struct e1000_hw *); |
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s32 (*read)(struct e1000_hw *, u16, u16, u16 *); |
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void (*release)(struct e1000_hw *); |
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s32 (*write)(struct e1000_hw *, u16, u16, u16 *); |
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s32 (*update)(struct e1000_hw *); |
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s32 (*validate)(struct e1000_hw *); |
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s32 (*valid_led_default)(struct e1000_hw *, u16 *); |
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}; |
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#define E1000_MAX_SENSORS 3 |
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struct e1000_thermal_diode_data { |
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u8 location; |
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u8 temp; |
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u8 caution_thresh; |
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u8 max_op_thresh; |
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}; |
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struct e1000_thermal_sensor_data { |
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struct e1000_thermal_diode_data sensor[E1000_MAX_SENSORS]; |
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}; |
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struct e1000_info { |
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s32 (*get_invariants)(struct e1000_hw *); |
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struct e1000_mac_operations *mac_ops; |
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const struct e1000_phy_operations *phy_ops; |
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struct e1000_nvm_operations *nvm_ops; |
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}; |
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extern const struct e1000_info e1000_82575_info; |
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struct e1000_mac_info { |
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struct e1000_mac_operations ops; |
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u8 addr[6]; |
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u8 perm_addr[6]; |
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enum e1000_mac_type type; |
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u32 ledctl_default; |
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u32 ledctl_mode1; |
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u32 ledctl_mode2; |
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u32 mc_filter_type; |
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u32 txcw; |
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u16 mta_reg_count; |
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u16 uta_reg_count; |
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/* Maximum size of the MTA register table in all supported adapters */ |
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#define MAX_MTA_REG 128 |
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u32 mta_shadow[MAX_MTA_REG]; |
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u16 rar_entry_count; |
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u8 forced_speed_duplex; |
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bool adaptive_ifs; |
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bool arc_subsystem_valid; |
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bool asf_firmware_present; |
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bool autoneg; |
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bool autoneg_failed; |
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bool disable_hw_init_bits; |
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bool get_link_status; |
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bool ifs_params_forced; |
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bool in_ifs_mode; |
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bool report_tx_early; |
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bool serdes_has_link; |
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bool tx_pkt_filtering; |
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struct e1000_thermal_sensor_data thermal_sensor_data; |
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}; |
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struct e1000_phy_info { |
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struct e1000_phy_operations ops; |
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enum e1000_phy_type type; |
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enum e1000_1000t_rx_status local_rx; |
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enum e1000_1000t_rx_status remote_rx; |
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enum e1000_ms_type ms_type; |
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enum e1000_ms_type original_ms_type; |
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enum e1000_rev_polarity cable_polarity; |
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enum e1000_smart_speed smart_speed; |
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u32 addr; |
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u32 id; |
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u32 reset_delay_us; /* in usec */ |
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u32 revision; |
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enum e1000_media_type media_type; |
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u16 autoneg_advertised; |
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u16 autoneg_mask; |
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u16 cable_length; |
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u16 max_cable_length; |
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u16 min_cable_length; |
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u16 pair_length[4]; |
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u8 mdix; |
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bool disable_polarity_correction; |
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bool is_mdix; |
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bool polarity_correction; |
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bool reset_disable; |
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bool speed_downgraded; |
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bool autoneg_wait_to_complete; |
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}; |
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struct e1000_nvm_info { |
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struct e1000_nvm_operations ops; |
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enum e1000_nvm_type type; |
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enum e1000_nvm_override override; |
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u32 flash_bank_size; |
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u32 flash_base_addr; |
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u16 word_size; |
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u16 delay_usec; |
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u16 address_bits; |
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u16 opcode_bits; |
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u16 page_size; |
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}; |
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struct e1000_bus_info { |
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enum e1000_bus_type type; |
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enum e1000_bus_speed speed; |
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enum e1000_bus_width width; |
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u32 snoop; |
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u16 func; |
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u16 pci_cmd_word; |
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}; |
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struct e1000_fc_info { |
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u32 high_water; /* Flow control high-water mark */ |
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u32 low_water; /* Flow control low-water mark */ |
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u16 pause_time; /* Flow control pause timer */ |
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bool send_xon; /* Flow control send XON */ |
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bool strict_ieee; /* Strict IEEE mode */ |
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enum e1000_fc_mode current_mode; /* Type of flow control */ |
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enum e1000_fc_mode requested_mode; |
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}; |
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struct e1000_mbx_operations { |
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s32 (*init_params)(struct e1000_hw *hw); |
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s32 (*read)(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id, |
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bool unlock); |
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s32 (*write)(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id); |
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s32 (*read_posted)(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id); |
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s32 (*write_posted)(struct e1000_hw *hw, u32 *msg, u16 size, |
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u16 mbx_id); |
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s32 (*check_for_msg)(struct e1000_hw *hw, u16 mbx_id); |
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s32 (*check_for_ack)(struct e1000_hw *hw, u16 mbx_id); |
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s32 (*check_for_rst)(struct e1000_hw *hw, u16 mbx_id); |
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s32 (*unlock)(struct e1000_hw *hw, u16 mbx_id); |
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}; |
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struct e1000_mbx_stats { |
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u32 msgs_tx; |
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u32 msgs_rx; |
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u32 acks; |
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u32 reqs; |
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u32 rsts; |
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}; |
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struct e1000_mbx_info { |
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struct e1000_mbx_operations ops; |
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struct e1000_mbx_stats stats; |
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u32 timeout; |
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u32 usec_delay; |
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u16 size; |
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}; |
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struct e1000_dev_spec_82575 { |
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bool sgmii_active; |
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bool global_device_reset; |
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bool eee_disable; |
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bool clear_semaphore_once; |
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struct e1000_sfp_flags eth_flags; |
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bool module_plugged; |
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u8 media_port; |
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bool media_changed; |
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bool mas_capable; |
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}; |
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struct e1000_hw { |
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void *back; |
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u8 __iomem *hw_addr; |
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u8 __iomem *flash_address; |
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unsigned long io_base; |
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struct e1000_mac_info mac; |
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struct e1000_fc_info fc; |
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struct e1000_phy_info phy; |
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struct e1000_nvm_info nvm; |
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struct e1000_bus_info bus; |
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struct e1000_mbx_info mbx; |
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struct e1000_host_mng_dhcp_cookie mng_cookie; |
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union { |
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struct e1000_dev_spec_82575 _82575; |
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} dev_spec; |
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u16 device_id; |
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u16 subsystem_vendor_id; |
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u16 subsystem_device_id; |
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u16 vendor_id; |
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u8 revision_id; |
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}; |
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struct net_device *igb_get_hw_dev(struct e1000_hw *hw); |
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#define hw_dbg(format, arg...) \ |
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netdev_dbg(igb_get_hw_dev(hw), format, ##arg) |
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/* These functions must be implemented by drivers */ |
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s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); |
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s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); |
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void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); |
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void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); |
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#endif /* _E1000_IGB_HW_H_ */
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