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808 lines
20 KiB
808 lines
20 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/delay.h> |
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#include <linux/mutex.h> |
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#include <linux/of_device.h> |
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#include <linux/slab.h> |
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#include <linux/string.h> |
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#include <dt-bindings/memory/tegra20-mc.h> |
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#include "mc.h" |
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#define MC_STAT_CONTROL 0x90 |
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#define MC_STAT_EMC_CLOCK_LIMIT 0xa0 |
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#define MC_STAT_EMC_CLOCKS 0xa4 |
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#define MC_STAT_EMC_CONTROL_0 0xa8 |
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#define MC_STAT_EMC_CONTROL_1 0xac |
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#define MC_STAT_EMC_COUNT_0 0xb8 |
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#define MC_STAT_EMC_COUNT_1 0xbc |
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#define MC_STAT_CONTROL_CLIENT_ID GENMASK(13, 8) |
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#define MC_STAT_CONTROL_EVENT GENMASK(23, 16) |
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#define MC_STAT_CONTROL_PRI_EVENT GENMASK(25, 24) |
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#define MC_STAT_CONTROL_FILTER_CLIENT_ENABLE GENMASK(26, 26) |
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#define MC_STAT_CONTROL_FILTER_PRI GENMASK(29, 28) |
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#define MC_STAT_CONTROL_PRI_EVENT_HP 0 |
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#define MC_STAT_CONTROL_PRI_EVENT_TM 1 |
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#define MC_STAT_CONTROL_PRI_EVENT_BW 2 |
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#define MC_STAT_CONTROL_FILTER_PRI_DISABLE 0 |
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#define MC_STAT_CONTROL_FILTER_PRI_NO 1 |
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#define MC_STAT_CONTROL_FILTER_PRI_YES 2 |
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#define MC_STAT_CONTROL_EVENT_QUALIFIED 0 |
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#define MC_STAT_CONTROL_EVENT_ANY_READ 1 |
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#define MC_STAT_CONTROL_EVENT_ANY_WRITE 2 |
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#define MC_STAT_CONTROL_EVENT_RD_WR_CHANGE 3 |
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#define MC_STAT_CONTROL_EVENT_SUCCESSIVE 4 |
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#define MC_STAT_CONTROL_EVENT_ARB_BANK_AA 5 |
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#define MC_STAT_CONTROL_EVENT_ARB_BANK_BB 6 |
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#define MC_STAT_CONTROL_EVENT_PAGE_MISS 7 |
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#define MC_STAT_CONTROL_EVENT_AUTO_PRECHARGE 8 |
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#define EMC_GATHER_RST (0 << 8) |
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#define EMC_GATHER_CLEAR (1 << 8) |
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#define EMC_GATHER_DISABLE (2 << 8) |
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#define EMC_GATHER_ENABLE (3 << 8) |
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#define MC_STAT_SAMPLE_TIME_USEC 16000 |
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/* we store collected statistics as a fixed point values */ |
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#define MC_FX_FRAC_SCALE 100 |
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static DEFINE_MUTEX(tegra20_mc_stat_lock); |
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struct tegra20_mc_stat_gather { |
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unsigned int pri_filter; |
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unsigned int pri_event; |
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unsigned int result; |
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unsigned int client; |
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unsigned int event; |
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bool client_enb; |
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}; |
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struct tegra20_mc_stat { |
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struct tegra20_mc_stat_gather gather0; |
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struct tegra20_mc_stat_gather gather1; |
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unsigned int sample_time_usec; |
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const struct tegra_mc *mc; |
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}; |
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struct tegra20_mc_client_stat { |
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unsigned int events; |
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unsigned int arb_high_prio; |
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unsigned int arb_timeout; |
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unsigned int arb_bandwidth; |
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unsigned int rd_wr_change; |
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unsigned int successive; |
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unsigned int page_miss; |
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unsigned int auto_precharge; |
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unsigned int arb_bank_aa; |
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unsigned int arb_bank_bb; |
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}; |
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static const struct tegra_mc_client tegra20_mc_clients[] = { |
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{ |
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.id = 0x00, |
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.name = "display0a", |
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}, { |
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.id = 0x01, |
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.name = "display0ab", |
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}, { |
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.id = 0x02, |
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.name = "display0b", |
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}, { |
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.id = 0x03, |
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.name = "display0bb", |
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}, { |
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.id = 0x04, |
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.name = "display0c", |
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}, { |
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.id = 0x05, |
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.name = "display0cb", |
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}, { |
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.id = 0x06, |
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.name = "display1b", |
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}, { |
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.id = 0x07, |
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.name = "display1bb", |
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}, { |
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.id = 0x08, |
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.name = "eppup", |
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}, { |
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.id = 0x09, |
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.name = "g2pr", |
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}, { |
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.id = 0x0a, |
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.name = "g2sr", |
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}, { |
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.id = 0x0b, |
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.name = "mpeunifbr", |
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}, { |
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.id = 0x0c, |
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.name = "viruv", |
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}, { |
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.id = 0x0d, |
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.name = "avpcarm7r", |
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}, { |
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.id = 0x0e, |
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.name = "displayhc", |
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}, { |
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.id = 0x0f, |
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.name = "displayhcb", |
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}, { |
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.id = 0x10, |
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.name = "fdcdrd", |
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}, { |
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.id = 0x11, |
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.name = "g2dr", |
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}, { |
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.id = 0x12, |
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.name = "host1xdmar", |
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}, { |
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.id = 0x13, |
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.name = "host1xr", |
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}, { |
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.id = 0x14, |
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.name = "idxsrd", |
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}, { |
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.id = 0x15, |
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.name = "mpcorer", |
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}, { |
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.id = 0x16, |
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.name = "mpe_ipred", |
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}, { |
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.id = 0x17, |
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.name = "mpeamemrd", |
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}, { |
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.id = 0x18, |
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.name = "mpecsrd", |
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}, { |
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.id = 0x19, |
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.name = "ppcsahbdmar", |
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}, { |
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.id = 0x1a, |
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.name = "ppcsahbslvr", |
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}, { |
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.id = 0x1b, |
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.name = "texsrd", |
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}, { |
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.id = 0x1c, |
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.name = "vdebsevr", |
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}, { |
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.id = 0x1d, |
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.name = "vdember", |
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}, { |
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.id = 0x1e, |
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.name = "vdemcer", |
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}, { |
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.id = 0x1f, |
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.name = "vdetper", |
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}, { |
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.id = 0x20, |
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.name = "eppu", |
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}, { |
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.id = 0x21, |
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.name = "eppv", |
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}, { |
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.id = 0x22, |
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.name = "eppy", |
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}, { |
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.id = 0x23, |
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.name = "mpeunifbw", |
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}, { |
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.id = 0x24, |
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.name = "viwsb", |
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}, { |
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.id = 0x25, |
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.name = "viwu", |
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}, { |
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.id = 0x26, |
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.name = "viwv", |
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}, { |
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.id = 0x27, |
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.name = "viwy", |
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}, { |
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.id = 0x28, |
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.name = "g2dw", |
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}, { |
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.id = 0x29, |
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.name = "avpcarm7w", |
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}, { |
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.id = 0x2a, |
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.name = "fdcdwr", |
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}, { |
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.id = 0x2b, |
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.name = "host1xw", |
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}, { |
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.id = 0x2c, |
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.name = "ispw", |
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}, { |
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.id = 0x2d, |
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.name = "mpcorew", |
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}, { |
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.id = 0x2e, |
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.name = "mpecswr", |
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}, { |
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.id = 0x2f, |
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.name = "ppcsahbdmaw", |
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}, { |
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.id = 0x30, |
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.name = "ppcsahbslvw", |
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}, { |
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.id = 0x31, |
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.name = "vdebsevw", |
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}, { |
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.id = 0x32, |
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.name = "vdembew", |
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}, { |
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.id = 0x33, |
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.name = "vdetpmw", |
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}, |
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}; |
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#define TEGRA20_MC_RESET(_name, _control, _status, _reset, _bit) \ |
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{ \ |
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.name = #_name, \ |
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.id = TEGRA20_MC_RESET_##_name, \ |
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.control = _control, \ |
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.status = _status, \ |
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.reset = _reset, \ |
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.bit = _bit, \ |
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} |
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static const struct tegra_mc_reset tegra20_mc_resets[] = { |
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TEGRA20_MC_RESET(AVPC, 0x100, 0x140, 0x104, 0), |
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TEGRA20_MC_RESET(DC, 0x100, 0x144, 0x104, 1), |
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TEGRA20_MC_RESET(DCB, 0x100, 0x148, 0x104, 2), |
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TEGRA20_MC_RESET(EPP, 0x100, 0x14c, 0x104, 3), |
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TEGRA20_MC_RESET(2D, 0x100, 0x150, 0x104, 4), |
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TEGRA20_MC_RESET(HC, 0x100, 0x154, 0x104, 5), |
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TEGRA20_MC_RESET(ISP, 0x100, 0x158, 0x104, 6), |
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TEGRA20_MC_RESET(MPCORE, 0x100, 0x15c, 0x104, 7), |
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TEGRA20_MC_RESET(MPEA, 0x100, 0x160, 0x104, 8), |
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TEGRA20_MC_RESET(MPEB, 0x100, 0x164, 0x104, 9), |
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TEGRA20_MC_RESET(MPEC, 0x100, 0x168, 0x104, 10), |
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TEGRA20_MC_RESET(3D, 0x100, 0x16c, 0x104, 11), |
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TEGRA20_MC_RESET(PPCS, 0x100, 0x170, 0x104, 12), |
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TEGRA20_MC_RESET(VDE, 0x100, 0x174, 0x104, 13), |
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TEGRA20_MC_RESET(VI, 0x100, 0x178, 0x104, 14), |
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}; |
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static int tegra20_mc_hotreset_assert(struct tegra_mc *mc, |
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const struct tegra_mc_reset *rst) |
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{ |
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unsigned long flags; |
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u32 value; |
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spin_lock_irqsave(&mc->lock, flags); |
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value = mc_readl(mc, rst->reset); |
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mc_writel(mc, value & ~BIT(rst->bit), rst->reset); |
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spin_unlock_irqrestore(&mc->lock, flags); |
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return 0; |
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} |
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static int tegra20_mc_hotreset_deassert(struct tegra_mc *mc, |
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const struct tegra_mc_reset *rst) |
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{ |
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unsigned long flags; |
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u32 value; |
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spin_lock_irqsave(&mc->lock, flags); |
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value = mc_readl(mc, rst->reset); |
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mc_writel(mc, value | BIT(rst->bit), rst->reset); |
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spin_unlock_irqrestore(&mc->lock, flags); |
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return 0; |
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} |
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static int tegra20_mc_block_dma(struct tegra_mc *mc, |
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const struct tegra_mc_reset *rst) |
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{ |
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unsigned long flags; |
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u32 value; |
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spin_lock_irqsave(&mc->lock, flags); |
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value = mc_readl(mc, rst->control) & ~BIT(rst->bit); |
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mc_writel(mc, value, rst->control); |
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spin_unlock_irqrestore(&mc->lock, flags); |
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return 0; |
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} |
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static bool tegra20_mc_dma_idling(struct tegra_mc *mc, |
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const struct tegra_mc_reset *rst) |
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{ |
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return mc_readl(mc, rst->status) == 0; |
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} |
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static int tegra20_mc_reset_status(struct tegra_mc *mc, |
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const struct tegra_mc_reset *rst) |
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{ |
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return (mc_readl(mc, rst->reset) & BIT(rst->bit)) == 0; |
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} |
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static int tegra20_mc_unblock_dma(struct tegra_mc *mc, |
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const struct tegra_mc_reset *rst) |
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{ |
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unsigned long flags; |
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u32 value; |
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spin_lock_irqsave(&mc->lock, flags); |
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value = mc_readl(mc, rst->control) | BIT(rst->bit); |
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mc_writel(mc, value, rst->control); |
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spin_unlock_irqrestore(&mc->lock, flags); |
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return 0; |
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} |
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static const struct tegra_mc_reset_ops tegra20_mc_reset_ops = { |
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.hotreset_assert = tegra20_mc_hotreset_assert, |
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.hotreset_deassert = tegra20_mc_hotreset_deassert, |
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.block_dma = tegra20_mc_block_dma, |
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.dma_idling = tegra20_mc_dma_idling, |
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.unblock_dma = tegra20_mc_unblock_dma, |
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.reset_status = tegra20_mc_reset_status, |
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}; |
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static int tegra20_mc_icc_set(struct icc_node *src, struct icc_node *dst) |
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{ |
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/* |
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* It should be possible to tune arbitration knobs here, but the |
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* default values are known to work well on all devices. Hence |
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* nothing to do here so far. |
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*/ |
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return 0; |
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} |
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static int tegra20_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw, |
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u32 peak_bw, u32 *agg_avg, u32 *agg_peak) |
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{ |
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/* |
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* ISO clients need to reserve extra bandwidth up-front because |
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* there could be high bandwidth pressure during initial filling |
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* of the client's FIFO buffers. Secondly, we need to take into |
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* account impurities of the memory subsystem. |
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*/ |
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if (tag & TEGRA_MC_ICC_TAG_ISO) |
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peak_bw = tegra_mc_scale_percents(peak_bw, 300); |
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*agg_avg += avg_bw; |
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*agg_peak = max(*agg_peak, peak_bw); |
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return 0; |
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} |
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static struct icc_node_data * |
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tegra20_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data) |
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{ |
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struct tegra_mc *mc = icc_provider_to_tegra_mc(data); |
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unsigned int i, idx = spec->args[0]; |
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struct icc_node_data *ndata; |
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struct icc_node *node; |
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list_for_each_entry(node, &mc->provider.nodes, node_list) { |
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if (node->id != idx) |
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continue; |
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ndata = kzalloc(sizeof(*ndata), GFP_KERNEL); |
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if (!ndata) |
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return ERR_PTR(-ENOMEM); |
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ndata->node = node; |
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/* these clients are isochronous by default */ |
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if (strstarts(node->name, "display") || |
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strstarts(node->name, "vi")) |
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ndata->tag = TEGRA_MC_ICC_TAG_ISO; |
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else |
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ndata->tag = TEGRA_MC_ICC_TAG_DEFAULT; |
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return ndata; |
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} |
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for (i = 0; i < mc->soc->num_clients; i++) { |
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if (mc->soc->clients[i].id == idx) |
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return ERR_PTR(-EPROBE_DEFER); |
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} |
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dev_err(mc->dev, "invalid ICC client ID %u\n", idx); |
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return ERR_PTR(-EINVAL); |
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} |
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static const struct tegra_mc_icc_ops tegra20_mc_icc_ops = { |
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.xlate_extended = tegra20_mc_of_icc_xlate_extended, |
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.aggregate = tegra20_mc_icc_aggreate, |
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.set = tegra20_mc_icc_set, |
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}; |
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static u32 tegra20_mc_stat_gather_control(const struct tegra20_mc_stat_gather *g) |
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{ |
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u32 control; |
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control = FIELD_PREP(MC_STAT_CONTROL_EVENT, g->event); |
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control |= FIELD_PREP(MC_STAT_CONTROL_CLIENT_ID, g->client); |
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control |= FIELD_PREP(MC_STAT_CONTROL_PRI_EVENT, g->pri_event); |
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control |= FIELD_PREP(MC_STAT_CONTROL_FILTER_PRI, g->pri_filter); |
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control |= FIELD_PREP(MC_STAT_CONTROL_FILTER_CLIENT_ENABLE, g->client_enb); |
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return control; |
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} |
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static void tegra20_mc_stat_gather(struct tegra20_mc_stat *stat) |
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{ |
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u32 clocks, count0, count1, control_0, control_1; |
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const struct tegra_mc *mc = stat->mc; |
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control_0 = tegra20_mc_stat_gather_control(&stat->gather0); |
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control_1 = tegra20_mc_stat_gather_control(&stat->gather1); |
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/* |
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* Reset statistic gathers state, select statistics collection mode |
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* and set clocks counter saturation limit to maximum. |
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*/ |
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mc_writel(mc, 0x00000000, MC_STAT_CONTROL); |
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mc_writel(mc, control_0, MC_STAT_EMC_CONTROL_0); |
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mc_writel(mc, control_1, MC_STAT_EMC_CONTROL_1); |
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mc_writel(mc, 0xffffffff, MC_STAT_EMC_CLOCK_LIMIT); |
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mc_writel(mc, EMC_GATHER_ENABLE, MC_STAT_CONTROL); |
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fsleep(stat->sample_time_usec); |
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mc_writel(mc, EMC_GATHER_DISABLE, MC_STAT_CONTROL); |
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count0 = mc_readl(mc, MC_STAT_EMC_COUNT_0); |
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count1 = mc_readl(mc, MC_STAT_EMC_COUNT_1); |
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clocks = mc_readl(mc, MC_STAT_EMC_CLOCKS); |
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clocks = max(clocks / 100 / MC_FX_FRAC_SCALE, 1u); |
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stat->gather0.result = DIV_ROUND_UP(count0, clocks); |
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stat->gather1.result = DIV_ROUND_UP(count1, clocks); |
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} |
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static void tegra20_mc_stat_events(const struct tegra_mc *mc, |
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const struct tegra_mc_client *client0, |
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const struct tegra_mc_client *client1, |
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unsigned int pri_filter, |
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unsigned int pri_event, |
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unsigned int event, |
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unsigned int *result0, |
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unsigned int *result1) |
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{ |
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struct tegra20_mc_stat stat = {}; |
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stat.gather0.client = client0 ? client0->id : 0; |
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stat.gather0.pri_filter = pri_filter; |
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stat.gather0.client_enb = !!client0; |
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stat.gather0.pri_event = pri_event; |
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stat.gather0.event = event; |
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stat.gather1.client = client1 ? client1->id : 0; |
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stat.gather1.pri_filter = pri_filter; |
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stat.gather1.client_enb = !!client1; |
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stat.gather1.pri_event = pri_event; |
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stat.gather1.event = event; |
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stat.sample_time_usec = MC_STAT_SAMPLE_TIME_USEC; |
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stat.mc = mc; |
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tegra20_mc_stat_gather(&stat); |
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*result0 = stat.gather0.result; |
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*result1 = stat.gather1.result; |
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} |
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static void tegra20_mc_collect_stats(const struct tegra_mc *mc, |
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struct tegra20_mc_client_stat *stats) |
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{ |
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const struct tegra_mc_client *client0, *client1; |
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unsigned int i; |
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/* collect memory controller utilization percent for each client */ |
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for (i = 0; i < mc->soc->num_clients; i += 2) { |
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client0 = &mc->soc->clients[i]; |
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client1 = &mc->soc->clients[i + 1]; |
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if (i + 1 == mc->soc->num_clients) |
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client1 = NULL; |
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tegra20_mc_stat_events(mc, client0, client1, |
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MC_STAT_CONTROL_FILTER_PRI_DISABLE, |
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MC_STAT_CONTROL_PRI_EVENT_HP, |
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MC_STAT_CONTROL_EVENT_QUALIFIED, |
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&stats[i + 0].events, |
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&stats[i + 1].events); |
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} |
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/* collect more info from active clients */ |
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for (i = 0; i < mc->soc->num_clients; i++) { |
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unsigned int clienta, clientb = mc->soc->num_clients; |
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for (client0 = NULL; i < mc->soc->num_clients; i++) { |
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if (stats[i].events) { |
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client0 = &mc->soc->clients[i]; |
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clienta = i++; |
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break; |
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} |
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} |
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for (client1 = NULL; i < mc->soc->num_clients; i++) { |
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if (stats[i].events) { |
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client1 = &mc->soc->clients[i]; |
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clientb = i; |
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break; |
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} |
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} |
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if (!client0 && !client1) |
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break; |
|
|
|
tegra20_mc_stat_events(mc, client0, client1, |
|
MC_STAT_CONTROL_FILTER_PRI_YES, |
|
MC_STAT_CONTROL_PRI_EVENT_HP, |
|
MC_STAT_CONTROL_EVENT_QUALIFIED, |
|
&stats[clienta].arb_high_prio, |
|
&stats[clientb].arb_high_prio); |
|
|
|
tegra20_mc_stat_events(mc, client0, client1, |
|
MC_STAT_CONTROL_FILTER_PRI_YES, |
|
MC_STAT_CONTROL_PRI_EVENT_TM, |
|
MC_STAT_CONTROL_EVENT_QUALIFIED, |
|
&stats[clienta].arb_timeout, |
|
&stats[clientb].arb_timeout); |
|
|
|
tegra20_mc_stat_events(mc, client0, client1, |
|
MC_STAT_CONTROL_FILTER_PRI_YES, |
|
MC_STAT_CONTROL_PRI_EVENT_BW, |
|
MC_STAT_CONTROL_EVENT_QUALIFIED, |
|
&stats[clienta].arb_bandwidth, |
|
&stats[clientb].arb_bandwidth); |
|
|
|
tegra20_mc_stat_events(mc, client0, client1, |
|
MC_STAT_CONTROL_FILTER_PRI_DISABLE, |
|
MC_STAT_CONTROL_PRI_EVENT_HP, |
|
MC_STAT_CONTROL_EVENT_RD_WR_CHANGE, |
|
&stats[clienta].rd_wr_change, |
|
&stats[clientb].rd_wr_change); |
|
|
|
tegra20_mc_stat_events(mc, client0, client1, |
|
MC_STAT_CONTROL_FILTER_PRI_DISABLE, |
|
MC_STAT_CONTROL_PRI_EVENT_HP, |
|
MC_STAT_CONTROL_EVENT_SUCCESSIVE, |
|
&stats[clienta].successive, |
|
&stats[clientb].successive); |
|
|
|
tegra20_mc_stat_events(mc, client0, client1, |
|
MC_STAT_CONTROL_FILTER_PRI_DISABLE, |
|
MC_STAT_CONTROL_PRI_EVENT_HP, |
|
MC_STAT_CONTROL_EVENT_PAGE_MISS, |
|
&stats[clienta].page_miss, |
|
&stats[clientb].page_miss); |
|
} |
|
} |
|
|
|
static void tegra20_mc_printf_percents(struct seq_file *s, |
|
const char *fmt, |
|
unsigned int percents_fx) |
|
{ |
|
char percents_str[8]; |
|
|
|
snprintf(percents_str, ARRAY_SIZE(percents_str), "%3u.%02u%%", |
|
percents_fx / MC_FX_FRAC_SCALE, percents_fx % MC_FX_FRAC_SCALE); |
|
|
|
seq_printf(s, fmt, percents_str); |
|
} |
|
|
|
static int tegra20_mc_stats_show(struct seq_file *s, void *unused) |
|
{ |
|
const struct tegra_mc *mc = dev_get_drvdata(s->private); |
|
struct tegra20_mc_client_stat *stats; |
|
unsigned int i; |
|
|
|
stats = kcalloc(mc->soc->num_clients + 1, sizeof(*stats), GFP_KERNEL); |
|
if (!stats) |
|
return -ENOMEM; |
|
|
|
mutex_lock(&tegra20_mc_stat_lock); |
|
|
|
tegra20_mc_collect_stats(mc, stats); |
|
|
|
mutex_unlock(&tegra20_mc_stat_lock); |
|
|
|
seq_puts(s, "Memory client Events Timeout High priority Bandwidth ARB RW change Successive Page miss\n"); |
|
seq_puts(s, "-----------------------------------------------------------------------------------------------------\n"); |
|
|
|
for (i = 0; i < mc->soc->num_clients; i++) { |
|
seq_printf(s, "%-14s ", mc->soc->clients[i].name); |
|
|
|
/* An event is generated when client performs R/W request. */ |
|
tegra20_mc_printf_percents(s, "%-9s", stats[i].events); |
|
|
|
/* |
|
* An event is generated based on the timeout (TM) signal |
|
* accompanying a request for arbitration. |
|
*/ |
|
tegra20_mc_printf_percents(s, "%-10s", stats[i].arb_timeout); |
|
|
|
/* |
|
* An event is generated based on the high-priority (HP) signal |
|
* accompanying a request for arbitration. |
|
*/ |
|
tegra20_mc_printf_percents(s, "%-16s", stats[i].arb_high_prio); |
|
|
|
/* |
|
* An event is generated based on the bandwidth (BW) signal |
|
* accompanying a request for arbitration. |
|
*/ |
|
tegra20_mc_printf_percents(s, "%-16s", stats[i].arb_bandwidth); |
|
|
|
/* |
|
* An event is generated when the memory controller switches |
|
* between making a read request to making a write request. |
|
*/ |
|
tegra20_mc_printf_percents(s, "%-12s", stats[i].rd_wr_change); |
|
|
|
/* |
|
* An even generated when the chosen client has wins arbitration |
|
* when it was also the winner at the previous request. If a |
|
* client makes N requests in a row that are honored, SUCCESSIVE |
|
* will be counted (N-1) times. Large values for this event |
|
* imply that if we were patient enough, all of those requests |
|
* could have been coalesced. |
|
*/ |
|
tegra20_mc_printf_percents(s, "%-13s", stats[i].successive); |
|
|
|
/* |
|
* An event is generated when the memory controller detects a |
|
* page miss for the current request. |
|
*/ |
|
tegra20_mc_printf_percents(s, "%-12s\n", stats[i].page_miss); |
|
} |
|
|
|
kfree(stats); |
|
|
|
return 0; |
|
} |
|
|
|
static int tegra20_mc_probe(struct tegra_mc *mc) |
|
{ |
|
debugfs_create_devm_seqfile(mc->dev, "stats", mc->debugfs.root, |
|
tegra20_mc_stats_show); |
|
|
|
return 0; |
|
} |
|
|
|
static int tegra20_mc_suspend(struct tegra_mc *mc) |
|
{ |
|
int err; |
|
|
|
if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) { |
|
err = tegra_gart_suspend(mc->gart); |
|
if (err < 0) |
|
return err; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int tegra20_mc_resume(struct tegra_mc *mc) |
|
{ |
|
int err; |
|
|
|
if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) { |
|
err = tegra_gart_resume(mc->gart); |
|
if (err < 0) |
|
return err; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static irqreturn_t tegra20_mc_handle_irq(int irq, void *data) |
|
{ |
|
struct tegra_mc *mc = data; |
|
unsigned long status; |
|
unsigned int bit; |
|
|
|
/* mask all interrupts to avoid flooding */ |
|
status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; |
|
if (!status) |
|
return IRQ_NONE; |
|
|
|
for_each_set_bit(bit, &status, 32) { |
|
const char *error = tegra_mc_status_names[bit]; |
|
const char *direction = "read", *secure = ""; |
|
const char *client, *desc; |
|
phys_addr_t addr; |
|
u32 value, reg; |
|
u8 id, type; |
|
|
|
switch (BIT(bit)) { |
|
case MC_INT_DECERR_EMEM: |
|
reg = MC_DECERR_EMEM_OTHERS_STATUS; |
|
value = mc_readl(mc, reg); |
|
|
|
id = value & mc->soc->client_id_mask; |
|
desc = tegra_mc_error_names[2]; |
|
|
|
if (value & BIT(31)) |
|
direction = "write"; |
|
break; |
|
|
|
case MC_INT_INVALID_GART_PAGE: |
|
reg = MC_GART_ERROR_REQ; |
|
value = mc_readl(mc, reg); |
|
|
|
id = (value >> 1) & mc->soc->client_id_mask; |
|
desc = tegra_mc_error_names[2]; |
|
|
|
if (value & BIT(0)) |
|
direction = "write"; |
|
break; |
|
|
|
case MC_INT_SECURITY_VIOLATION: |
|
reg = MC_SECURITY_VIOLATION_STATUS; |
|
value = mc_readl(mc, reg); |
|
|
|
id = value & mc->soc->client_id_mask; |
|
type = (value & BIT(30)) ? 4 : 3; |
|
desc = tegra_mc_error_names[type]; |
|
secure = "secure "; |
|
|
|
if (value & BIT(31)) |
|
direction = "write"; |
|
break; |
|
|
|
default: |
|
continue; |
|
} |
|
|
|
client = mc->soc->clients[id].name; |
|
addr = mc_readl(mc, reg + sizeof(u32)); |
|
|
|
dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n", |
|
client, secure, direction, &addr, error, |
|
desc); |
|
} |
|
|
|
/* clear interrupts */ |
|
mc_writel(mc, status, MC_INTSTATUS); |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
static const struct tegra_mc_ops tegra20_mc_ops = { |
|
.probe = tegra20_mc_probe, |
|
.suspend = tegra20_mc_suspend, |
|
.resume = tegra20_mc_resume, |
|
.handle_irq = tegra20_mc_handle_irq, |
|
}; |
|
|
|
const struct tegra_mc_soc tegra20_mc_soc = { |
|
.clients = tegra20_mc_clients, |
|
.num_clients = ARRAY_SIZE(tegra20_mc_clients), |
|
.num_address_bits = 32, |
|
.client_id_mask = 0x3f, |
|
.intmask = MC_INT_SECURITY_VIOLATION | MC_INT_INVALID_GART_PAGE | |
|
MC_INT_DECERR_EMEM, |
|
.reset_ops = &tegra20_mc_reset_ops, |
|
.resets = tegra20_mc_resets, |
|
.num_resets = ARRAY_SIZE(tegra20_mc_resets), |
|
.icc_ops = &tegra20_mc_icc_ops, |
|
.ops = &tegra20_mc_ops, |
|
};
|
|
|