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878 lines
16 KiB
878 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved. |
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*/ |
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#include <linux/io.h> |
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#include <linux/iommu.h> |
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#include <linux/module.h> |
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#include <linux/mod_devicetable.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <soc/tegra/mc.h> |
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#if defined(CONFIG_ARCH_TEGRA_186_SOC) |
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#include <dt-bindings/memory/tegra186-mc.h> |
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#endif |
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#define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0) |
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#define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16) |
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#define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8) |
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static void tegra186_mc_program_sid(struct tegra_mc *mc) |
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{ |
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unsigned int i; |
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for (i = 0; i < mc->soc->num_clients; i++) { |
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const struct tegra_mc_client *client = &mc->soc->clients[i]; |
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u32 override, security; |
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override = readl(mc->regs + client->regs.sid.override); |
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security = readl(mc->regs + client->regs.sid.security); |
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dev_dbg(mc->dev, "client %s: override: %x security: %x\n", |
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client->name, override, security); |
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dev_dbg(mc->dev, "setting SID %u for %s\n", client->sid, |
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client->name); |
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writel(client->sid, mc->regs + client->regs.sid.override); |
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override = readl(mc->regs + client->regs.sid.override); |
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security = readl(mc->regs + client->regs.sid.security); |
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dev_dbg(mc->dev, "client %s: override: %x security: %x\n", |
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client->name, override, security); |
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} |
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} |
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static int tegra186_mc_probe(struct tegra_mc *mc) |
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{ |
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int err; |
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err = of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev); |
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if (err < 0) |
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return err; |
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tegra186_mc_program_sid(mc); |
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return 0; |
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} |
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static void tegra186_mc_remove(struct tegra_mc *mc) |
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{ |
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of_platform_depopulate(mc->dev); |
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} |
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static int tegra186_mc_resume(struct tegra_mc *mc) |
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{ |
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tegra186_mc_program_sid(mc); |
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return 0; |
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} |
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static void tegra186_mc_client_sid_override(struct tegra_mc *mc, |
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const struct tegra_mc_client *client, |
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unsigned int sid) |
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{ |
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u32 value, old; |
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value = readl(mc->regs + client->regs.sid.security); |
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if ((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) { |
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/* |
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* If the secure firmware has locked this down the override |
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* for this memory client, there's nothing we can do here. |
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*/ |
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if (value & MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED) |
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return; |
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/* |
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* Otherwise, try to set the override itself. Typically the |
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* secure firmware will never have set this configuration. |
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* Instead, it will either have disabled write access to |
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* this field, or it will already have set an explicit |
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* override itself. |
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*/ |
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WARN_ON((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0); |
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value |= MC_SID_STREAMID_SECURITY_OVERRIDE; |
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writel(value, mc->regs + client->regs.sid.security); |
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} |
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value = readl(mc->regs + client->regs.sid.override); |
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old = value & MC_SID_STREAMID_OVERRIDE_MASK; |
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if (old != sid) { |
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dev_dbg(mc->dev, "overriding SID %x for %s with %x\n", old, |
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client->name, sid); |
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writel(sid, mc->regs + client->regs.sid.override); |
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} |
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} |
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static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev) |
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{ |
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#if IS_ENABLED(CONFIG_IOMMU_API) |
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struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
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struct of_phandle_args args; |
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unsigned int i, index = 0; |
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while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells", |
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index, &args)) { |
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if (args.np == mc->dev->of_node && args.args_count != 0) { |
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for (i = 0; i < mc->soc->num_clients; i++) { |
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const struct tegra_mc_client *client = &mc->soc->clients[i]; |
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if (client->id == args.args[0]) { |
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u32 sid = fwspec->ids[0] & MC_SID_STREAMID_OVERRIDE_MASK; |
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tegra186_mc_client_sid_override(mc, client, sid); |
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} |
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} |
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} |
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index++; |
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} |
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#endif |
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return 0; |
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} |
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const struct tegra_mc_ops tegra186_mc_ops = { |
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.probe = tegra186_mc_probe, |
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.remove = tegra186_mc_remove, |
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.resume = tegra186_mc_resume, |
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.probe_device = tegra186_mc_probe_device, |
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}; |
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#if defined(CONFIG_ARCH_TEGRA_186_SOC) |
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static const struct tegra_mc_client tegra186_mc_clients[] = { |
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{ |
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.id = TEGRA186_MEMORY_CLIENT_PTCR, |
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.name = "ptcr", |
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.sid = TEGRA186_SID_PASSTHROUGH, |
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.regs = { |
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.sid = { |
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.override = 0x000, |
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.security = 0x004, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_AFIR, |
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.name = "afir", |
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.sid = TEGRA186_SID_AFI, |
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.regs = { |
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.sid = { |
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.override = 0x070, |
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.security = 0x074, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_HDAR, |
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.name = "hdar", |
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.sid = TEGRA186_SID_HDA, |
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.regs = { |
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.sid = { |
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.override = 0x0a8, |
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.security = 0x0ac, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_HOST1XDMAR, |
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.name = "host1xdmar", |
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.sid = TEGRA186_SID_HOST1X, |
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.regs = { |
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.sid = { |
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.override = 0x0b0, |
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.security = 0x0b4, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_NVENCSRD, |
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.name = "nvencsrd", |
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.sid = TEGRA186_SID_NVENC, |
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.regs = { |
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.sid = { |
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.override = 0x0e0, |
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.security = 0x0e4, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_SATAR, |
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.name = "satar", |
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.sid = TEGRA186_SID_SATA, |
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.regs = { |
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.sid = { |
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.override = 0x0f8, |
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.security = 0x0fc, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_MPCORER, |
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.name = "mpcorer", |
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.sid = TEGRA186_SID_PASSTHROUGH, |
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.regs = { |
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.sid = { |
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.override = 0x138, |
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.security = 0x13c, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_NVENCSWR, |
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.name = "nvencswr", |
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.sid = TEGRA186_SID_NVENC, |
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.regs = { |
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.sid = { |
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.override = 0x158, |
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.security = 0x15c, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_AFIW, |
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.name = "afiw", |
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.sid = TEGRA186_SID_AFI, |
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.regs = { |
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.sid = { |
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.override = 0x188, |
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.security = 0x18c, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_HDAW, |
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.name = "hdaw", |
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.sid = TEGRA186_SID_HDA, |
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.regs = { |
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.sid = { |
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.override = 0x1a8, |
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.security = 0x1ac, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_MPCOREW, |
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.name = "mpcorew", |
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.sid = TEGRA186_SID_PASSTHROUGH, |
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.regs = { |
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.sid = { |
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.override = 0x1c8, |
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.security = 0x1cc, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_SATAW, |
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.name = "sataw", |
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.sid = TEGRA186_SID_SATA, |
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.regs = { |
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.sid = { |
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.override = 0x1e8, |
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.security = 0x1ec, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_ISPRA, |
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.name = "ispra", |
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.sid = TEGRA186_SID_ISP, |
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.regs = { |
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.sid = { |
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.override = 0x220, |
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.security = 0x224, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_ISPWA, |
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.name = "ispwa", |
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.sid = TEGRA186_SID_ISP, |
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.regs = { |
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.sid = { |
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.override = 0x230, |
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.security = 0x234, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_ISPWB, |
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.name = "ispwb", |
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.sid = TEGRA186_SID_ISP, |
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.regs = { |
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.sid = { |
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.override = 0x238, |
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.security = 0x23c, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTR, |
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.name = "xusb_hostr", |
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.sid = TEGRA186_SID_XUSB_HOST, |
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.regs = { |
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.sid = { |
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.override = 0x250, |
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.security = 0x254, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTW, |
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.name = "xusb_hostw", |
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.sid = TEGRA186_SID_XUSB_HOST, |
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.regs = { |
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.sid = { |
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.override = 0x258, |
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.security = 0x25c, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_XUSB_DEVR, |
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.name = "xusb_devr", |
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.sid = TEGRA186_SID_XUSB_DEV, |
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.regs = { |
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.sid = { |
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.override = 0x260, |
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.security = 0x264, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_XUSB_DEVW, |
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.name = "xusb_devw", |
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.sid = TEGRA186_SID_XUSB_DEV, |
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.regs = { |
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.sid = { |
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.override = 0x268, |
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.security = 0x26c, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_TSECSRD, |
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.name = "tsecsrd", |
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.sid = TEGRA186_SID_TSEC, |
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.regs = { |
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.sid = { |
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.override = 0x2a0, |
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.security = 0x2a4, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_TSECSWR, |
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.name = "tsecswr", |
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.sid = TEGRA186_SID_TSEC, |
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.regs = { |
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.sid = { |
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.override = 0x2a8, |
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.security = 0x2ac, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_GPUSRD, |
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.name = "gpusrd", |
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.sid = TEGRA186_SID_GPU, |
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.regs = { |
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.sid = { |
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.override = 0x2c0, |
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.security = 0x2c4, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_GPUSWR, |
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.name = "gpuswr", |
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.sid = TEGRA186_SID_GPU, |
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.regs = { |
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.sid = { |
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.override = 0x2c8, |
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.security = 0x2cc, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_SDMMCRA, |
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.name = "sdmmcra", |
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.sid = TEGRA186_SID_SDMMC1, |
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.regs = { |
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.sid = { |
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.override = 0x300, |
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.security = 0x304, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_SDMMCRAA, |
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.name = "sdmmcraa", |
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.sid = TEGRA186_SID_SDMMC2, |
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.regs = { |
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.sid = { |
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.override = 0x308, |
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.security = 0x30c, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_SDMMCR, |
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.name = "sdmmcr", |
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.sid = TEGRA186_SID_SDMMC3, |
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.regs = { |
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.sid = { |
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.override = 0x310, |
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.security = 0x314, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_SDMMCRAB, |
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.name = "sdmmcrab", |
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.sid = TEGRA186_SID_SDMMC4, |
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.regs = { |
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.sid = { |
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.override = 0x318, |
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.security = 0x31c, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_SDMMCWA, |
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.name = "sdmmcwa", |
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.sid = TEGRA186_SID_SDMMC1, |
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.regs = { |
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.sid = { |
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.override = 0x320, |
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.security = 0x324, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_SDMMCWAA, |
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.name = "sdmmcwaa", |
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.sid = TEGRA186_SID_SDMMC2, |
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.regs = { |
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.sid = { |
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.override = 0x328, |
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.security = 0x32c, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_SDMMCW, |
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.name = "sdmmcw", |
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.sid = TEGRA186_SID_SDMMC3, |
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.regs = { |
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.sid = { |
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.override = 0x330, |
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.security = 0x334, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_SDMMCWAB, |
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.name = "sdmmcwab", |
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.sid = TEGRA186_SID_SDMMC4, |
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.regs = { |
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.sid = { |
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.override = 0x338, |
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.security = 0x33c, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_VICSRD, |
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.name = "vicsrd", |
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.sid = TEGRA186_SID_VIC, |
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.regs = { |
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.sid = { |
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.override = 0x360, |
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.security = 0x364, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_VICSWR, |
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.name = "vicswr", |
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.sid = TEGRA186_SID_VIC, |
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.regs = { |
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.sid = { |
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.override = 0x368, |
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.security = 0x36c, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_VIW, |
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.name = "viw", |
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.sid = TEGRA186_SID_VI, |
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.regs = { |
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.sid = { |
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.override = 0x390, |
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.security = 0x394, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_NVDECSRD, |
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.name = "nvdecsrd", |
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.sid = TEGRA186_SID_NVDEC, |
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.regs = { |
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.sid = { |
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.override = 0x3c0, |
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.security = 0x3c4, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_NVDECSWR, |
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.name = "nvdecswr", |
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.sid = TEGRA186_SID_NVDEC, |
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.regs = { |
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.sid = { |
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.override = 0x3c8, |
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.security = 0x3cc, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_APER, |
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.name = "aper", |
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.sid = TEGRA186_SID_APE, |
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.regs = { |
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.sid = { |
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.override = 0x3d0, |
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.security = 0x3d4, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_APEW, |
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.name = "apew", |
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.sid = TEGRA186_SID_APE, |
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.regs = { |
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.sid = { |
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.override = 0x3d8, |
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.security = 0x3dc, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_NVJPGSRD, |
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.name = "nvjpgsrd", |
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.sid = TEGRA186_SID_NVJPG, |
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.regs = { |
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.sid = { |
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.override = 0x3f0, |
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.security = 0x3f4, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_NVJPGSWR, |
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.name = "nvjpgswr", |
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.sid = TEGRA186_SID_NVJPG, |
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.regs = { |
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.sid = { |
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.override = 0x3f8, |
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.security = 0x3fc, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_SESRD, |
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.name = "sesrd", |
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.sid = TEGRA186_SID_SE, |
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.regs = { |
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.sid = { |
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.override = 0x400, |
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.security = 0x404, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_SESWR, |
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.name = "seswr", |
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.sid = TEGRA186_SID_SE, |
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.regs = { |
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.sid = { |
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.override = 0x408, |
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.security = 0x40c, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_ETRR, |
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.name = "etrr", |
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.sid = TEGRA186_SID_ETR, |
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.regs = { |
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.sid = { |
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.override = 0x420, |
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.security = 0x424, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_ETRW, |
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.name = "etrw", |
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.sid = TEGRA186_SID_ETR, |
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.regs = { |
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.sid = { |
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.override = 0x428, |
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.security = 0x42c, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_TSECSRDB, |
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.name = "tsecsrdb", |
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.sid = TEGRA186_SID_TSECB, |
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.regs = { |
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.sid = { |
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.override = 0x430, |
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.security = 0x434, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_TSECSWRB, |
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.name = "tsecswrb", |
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.sid = TEGRA186_SID_TSECB, |
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.regs = { |
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.sid = { |
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.override = 0x438, |
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.security = 0x43c, |
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}, |
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}, |
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}, { |
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.id = TEGRA186_MEMORY_CLIENT_GPUSRD2, |
|
.name = "gpusrd2", |
|
.sid = TEGRA186_SID_GPU, |
|
.regs = { |
|
.sid = { |
|
.override = 0x440, |
|
.security = 0x444, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_GPUSWR2, |
|
.name = "gpuswr2", |
|
.sid = TEGRA186_SID_GPU, |
|
.regs = { |
|
.sid = { |
|
.override = 0x448, |
|
.security = 0x44c, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_AXISR, |
|
.name = "axisr", |
|
.sid = TEGRA186_SID_GPCDMA_0, |
|
.regs = { |
|
.sid = { |
|
.override = 0x460, |
|
.security = 0x464, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_AXISW, |
|
.name = "axisw", |
|
.sid = TEGRA186_SID_GPCDMA_0, |
|
.regs = { |
|
.sid = { |
|
.override = 0x468, |
|
.security = 0x46c, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_EQOSR, |
|
.name = "eqosr", |
|
.sid = TEGRA186_SID_EQOS, |
|
.regs = { |
|
.sid = { |
|
.override = 0x470, |
|
.security = 0x474, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_EQOSW, |
|
.name = "eqosw", |
|
.sid = TEGRA186_SID_EQOS, |
|
.regs = { |
|
.sid = { |
|
.override = 0x478, |
|
.security = 0x47c, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_UFSHCR, |
|
.name = "ufshcr", |
|
.sid = TEGRA186_SID_UFSHC, |
|
.regs = { |
|
.sid = { |
|
.override = 0x480, |
|
.security = 0x484, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_UFSHCW, |
|
.name = "ufshcw", |
|
.sid = TEGRA186_SID_UFSHC, |
|
.regs = { |
|
.sid = { |
|
.override = 0x488, |
|
.security = 0x48c, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR, |
|
.name = "nvdisplayr", |
|
.sid = TEGRA186_SID_NVDISPLAY, |
|
.regs = { |
|
.sid = { |
|
.override = 0x490, |
|
.security = 0x494, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_BPMPR, |
|
.name = "bpmpr", |
|
.sid = TEGRA186_SID_BPMP, |
|
.regs = { |
|
.sid = { |
|
.override = 0x498, |
|
.security = 0x49c, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_BPMPW, |
|
.name = "bpmpw", |
|
.sid = TEGRA186_SID_BPMP, |
|
.regs = { |
|
.sid = { |
|
.override = 0x4a0, |
|
.security = 0x4a4, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_BPMPDMAR, |
|
.name = "bpmpdmar", |
|
.sid = TEGRA186_SID_BPMP, |
|
.regs = { |
|
.sid = { |
|
.override = 0x4a8, |
|
.security = 0x4ac, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_BPMPDMAW, |
|
.name = "bpmpdmaw", |
|
.sid = TEGRA186_SID_BPMP, |
|
.regs = { |
|
.sid = { |
|
.override = 0x4b0, |
|
.security = 0x4b4, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_AONR, |
|
.name = "aonr", |
|
.sid = TEGRA186_SID_AON, |
|
.regs = { |
|
.sid = { |
|
.override = 0x4b8, |
|
.security = 0x4bc, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_AONW, |
|
.name = "aonw", |
|
.sid = TEGRA186_SID_AON, |
|
.regs = { |
|
.sid = { |
|
.override = 0x4c0, |
|
.security = 0x4c4, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_AONDMAR, |
|
.name = "aondmar", |
|
.sid = TEGRA186_SID_AON, |
|
.regs = { |
|
.sid = { |
|
.override = 0x4c8, |
|
.security = 0x4cc, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_AONDMAW, |
|
.name = "aondmaw", |
|
.sid = TEGRA186_SID_AON, |
|
.regs = { |
|
.sid = { |
|
.override = 0x4d0, |
|
.security = 0x4d4, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_SCER, |
|
.name = "scer", |
|
.sid = TEGRA186_SID_SCE, |
|
.regs = { |
|
.sid = { |
|
.override = 0x4d8, |
|
.security = 0x4dc, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_SCEW, |
|
.name = "scew", |
|
.sid = TEGRA186_SID_SCE, |
|
.regs = { |
|
.sid = { |
|
.override = 0x4e0, |
|
.security = 0x4e4, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_SCEDMAR, |
|
.name = "scedmar", |
|
.sid = TEGRA186_SID_SCE, |
|
.regs = { |
|
.sid = { |
|
.override = 0x4e8, |
|
.security = 0x4ec, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_SCEDMAW, |
|
.name = "scedmaw", |
|
.sid = TEGRA186_SID_SCE, |
|
.regs = { |
|
.sid = { |
|
.override = 0x4f0, |
|
.security = 0x4f4, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_APEDMAR, |
|
.name = "apedmar", |
|
.sid = TEGRA186_SID_APE, |
|
.regs = { |
|
.sid = { |
|
.override = 0x4f8, |
|
.security = 0x4fc, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_APEDMAW, |
|
.name = "apedmaw", |
|
.sid = TEGRA186_SID_APE, |
|
.regs = { |
|
.sid = { |
|
.override = 0x500, |
|
.security = 0x504, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR1, |
|
.name = "nvdisplayr1", |
|
.sid = TEGRA186_SID_NVDISPLAY, |
|
.regs = { |
|
.sid = { |
|
.override = 0x508, |
|
.security = 0x50c, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_VICSRD1, |
|
.name = "vicsrd1", |
|
.sid = TEGRA186_SID_VIC, |
|
.regs = { |
|
.sid = { |
|
.override = 0x510, |
|
.security = 0x514, |
|
}, |
|
}, |
|
}, { |
|
.id = TEGRA186_MEMORY_CLIENT_NVDECSRD1, |
|
.name = "nvdecsrd1", |
|
.sid = TEGRA186_SID_NVDEC, |
|
.regs = { |
|
.sid = { |
|
.override = 0x518, |
|
.security = 0x51c, |
|
}, |
|
}, |
|
}, |
|
}; |
|
|
|
const struct tegra_mc_soc tegra186_mc_soc = { |
|
.num_clients = ARRAY_SIZE(tegra186_mc_clients), |
|
.clients = tegra186_mc_clients, |
|
.num_address_bits = 40, |
|
.ops = &tegra186_mc_ops, |
|
}; |
|
#endif
|
|
|