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288 lines
7.0 KiB
288 lines
7.0 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2019 NVIDIA CORPORATION. All rights reserved. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/debugfs.h> |
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#include <linux/module.h> |
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#include <linux/mod_devicetable.h> |
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#include <linux/platform_device.h> |
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#include <soc/tegra/bpmp.h> |
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struct tegra186_emc_dvfs { |
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unsigned long latency; |
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unsigned long rate; |
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}; |
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struct tegra186_emc { |
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struct tegra_bpmp *bpmp; |
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struct device *dev; |
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struct clk *clk; |
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struct tegra186_emc_dvfs *dvfs; |
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unsigned int num_dvfs; |
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struct { |
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struct dentry *root; |
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unsigned long min_rate; |
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unsigned long max_rate; |
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} debugfs; |
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}; |
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/* |
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* debugfs interface |
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* |
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* The memory controller driver exposes some files in debugfs that can be used |
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* to control the EMC frequency. The top-level directory can be found here: |
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* |
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* /sys/kernel/debug/emc |
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* |
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* It contains the following files: |
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* |
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* - available_rates: This file contains a list of valid, space-separated |
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* EMC frequencies. |
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* |
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* - min_rate: Writing a value to this file sets the given frequency as the |
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* floor of the permitted range. If this is higher than the currently |
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* configured EMC frequency, this will cause the frequency to be |
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* increased so that it stays within the valid range. |
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* |
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* - max_rate: Similarily to the min_rate file, writing a value to this file |
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* sets the given frequency as the ceiling of the permitted range. If |
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* the value is lower than the currently configured EMC frequency, this |
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* will cause the frequency to be decreased so that it stays within the |
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* valid range. |
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*/ |
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static bool tegra186_emc_validate_rate(struct tegra186_emc *emc, |
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unsigned long rate) |
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{ |
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unsigned int i; |
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for (i = 0; i < emc->num_dvfs; i++) |
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if (rate == emc->dvfs[i].rate) |
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return true; |
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return false; |
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} |
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static int tegra186_emc_debug_available_rates_show(struct seq_file *s, |
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void *data) |
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{ |
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struct tegra186_emc *emc = s->private; |
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const char *prefix = ""; |
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unsigned int i; |
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for (i = 0; i < emc->num_dvfs; i++) { |
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seq_printf(s, "%s%lu", prefix, emc->dvfs[i].rate); |
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prefix = " "; |
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} |
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seq_puts(s, "\n"); |
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return 0; |
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} |
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static int tegra186_emc_debug_available_rates_open(struct inode *inode, |
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struct file *file) |
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{ |
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return single_open(file, tegra186_emc_debug_available_rates_show, |
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inode->i_private); |
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} |
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static const struct file_operations tegra186_emc_debug_available_rates_fops = { |
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.open = tegra186_emc_debug_available_rates_open, |
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.read = seq_read, |
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.llseek = seq_lseek, |
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.release = single_release, |
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}; |
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static int tegra186_emc_debug_min_rate_get(void *data, u64 *rate) |
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{ |
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struct tegra186_emc *emc = data; |
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*rate = emc->debugfs.min_rate; |
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return 0; |
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} |
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static int tegra186_emc_debug_min_rate_set(void *data, u64 rate) |
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{ |
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struct tegra186_emc *emc = data; |
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int err; |
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if (!tegra186_emc_validate_rate(emc, rate)) |
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return -EINVAL; |
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err = clk_set_min_rate(emc->clk, rate); |
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if (err < 0) |
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return err; |
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emc->debugfs.min_rate = rate; |
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return 0; |
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} |
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DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_min_rate_fops, |
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tegra186_emc_debug_min_rate_get, |
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tegra186_emc_debug_min_rate_set, "%llu\n"); |
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static int tegra186_emc_debug_max_rate_get(void *data, u64 *rate) |
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{ |
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struct tegra186_emc *emc = data; |
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*rate = emc->debugfs.max_rate; |
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return 0; |
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} |
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static int tegra186_emc_debug_max_rate_set(void *data, u64 rate) |
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{ |
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struct tegra186_emc *emc = data; |
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int err; |
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if (!tegra186_emc_validate_rate(emc, rate)) |
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return -EINVAL; |
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err = clk_set_max_rate(emc->clk, rate); |
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if (err < 0) |
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return err; |
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emc->debugfs.max_rate = rate; |
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return 0; |
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} |
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DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_max_rate_fops, |
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tegra186_emc_debug_max_rate_get, |
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tegra186_emc_debug_max_rate_set, "%llu\n"); |
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static int tegra186_emc_probe(struct platform_device *pdev) |
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{ |
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struct mrq_emc_dvfs_latency_response response; |
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struct tegra_bpmp_message msg; |
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struct tegra186_emc *emc; |
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unsigned int i; |
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int err; |
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emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); |
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if (!emc) |
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return -ENOMEM; |
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emc->bpmp = tegra_bpmp_get(&pdev->dev); |
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if (IS_ERR(emc->bpmp)) |
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return dev_err_probe(&pdev->dev, PTR_ERR(emc->bpmp), "failed to get BPMP\n"); |
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emc->clk = devm_clk_get(&pdev->dev, "emc"); |
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if (IS_ERR(emc->clk)) { |
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err = PTR_ERR(emc->clk); |
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dev_err(&pdev->dev, "failed to get EMC clock: %d\n", err); |
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goto put_bpmp; |
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} |
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platform_set_drvdata(pdev, emc); |
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emc->dev = &pdev->dev; |
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memset(&msg, 0, sizeof(msg)); |
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msg.mrq = MRQ_EMC_DVFS_LATENCY; |
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msg.tx.data = NULL; |
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msg.tx.size = 0; |
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msg.rx.data = &response; |
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msg.rx.size = sizeof(response); |
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err = tegra_bpmp_transfer(emc->bpmp, &msg); |
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if (err < 0) { |
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dev_err(&pdev->dev, "failed to EMC DVFS pairs: %d\n", err); |
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goto put_bpmp; |
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} |
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emc->debugfs.min_rate = ULONG_MAX; |
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emc->debugfs.max_rate = 0; |
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emc->num_dvfs = response.num_pairs; |
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emc->dvfs = devm_kmalloc_array(&pdev->dev, emc->num_dvfs, |
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sizeof(*emc->dvfs), GFP_KERNEL); |
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if (!emc->dvfs) { |
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err = -ENOMEM; |
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goto put_bpmp; |
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} |
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dev_dbg(&pdev->dev, "%u DVFS pairs:\n", emc->num_dvfs); |
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for (i = 0; i < emc->num_dvfs; i++) { |
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emc->dvfs[i].rate = response.pairs[i].freq * 1000; |
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emc->dvfs[i].latency = response.pairs[i].latency; |
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if (emc->dvfs[i].rate < emc->debugfs.min_rate) |
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emc->debugfs.min_rate = emc->dvfs[i].rate; |
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if (emc->dvfs[i].rate > emc->debugfs.max_rate) |
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emc->debugfs.max_rate = emc->dvfs[i].rate; |
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dev_dbg(&pdev->dev, " %2u: %lu Hz -> %lu us\n", i, |
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emc->dvfs[i].rate, emc->dvfs[i].latency); |
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} |
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err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, |
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emc->debugfs.max_rate); |
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if (err < 0) { |
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dev_err(&pdev->dev, |
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"failed to set rate range [%lu-%lu] for %pC\n", |
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emc->debugfs.min_rate, emc->debugfs.max_rate, |
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emc->clk); |
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goto put_bpmp; |
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} |
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emc->debugfs.root = debugfs_create_dir("emc", NULL); |
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debugfs_create_file("available_rates", S_IRUGO, emc->debugfs.root, |
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emc, &tegra186_emc_debug_available_rates_fops); |
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debugfs_create_file("min_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, |
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emc, &tegra186_emc_debug_min_rate_fops); |
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debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, |
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emc, &tegra186_emc_debug_max_rate_fops); |
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return 0; |
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put_bpmp: |
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tegra_bpmp_put(emc->bpmp); |
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return err; |
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} |
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static int tegra186_emc_remove(struct platform_device *pdev) |
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{ |
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struct tegra186_emc *emc = platform_get_drvdata(pdev); |
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debugfs_remove_recursive(emc->debugfs.root); |
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tegra_bpmp_put(emc->bpmp); |
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return 0; |
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} |
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static const struct of_device_id tegra186_emc_of_match[] = { |
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#if defined(CONFIG_ARCH_TEGRA_186_SOC) |
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{ .compatible = "nvidia,tegra186-emc" }, |
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#endif |
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#if defined(CONFIG_ARCH_TEGRA_194_SOC) |
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{ .compatible = "nvidia,tegra194-emc" }, |
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#endif |
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{ /* sentinel */ } |
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}; |
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MODULE_DEVICE_TABLE(of, tegra186_emc_of_match); |
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static struct platform_driver tegra186_emc_driver = { |
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.driver = { |
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.name = "tegra186-emc", |
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.of_match_table = tegra186_emc_of_match, |
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.suppress_bind_attrs = true, |
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}, |
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.probe = tegra186_emc_probe, |
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.remove = tegra186_emc_remove, |
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}; |
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module_platform_driver(tegra186_emc_driver); |
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MODULE_AUTHOR("Thierry Reding <[email protected]>"); |
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MODULE_DESCRIPTION("NVIDIA Tegra186 External Memory Controller driver"); |
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MODULE_LICENSE("GPL v2");
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