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591 lines
16 KiB
591 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Renesas RPC-IF core driver |
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* |
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* Copyright (C) 2018-2019 Renesas Solutions Corp. |
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* Copyright (C) 2019 Macronix International Co., Ltd. |
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* Copyright (C) 2019-2020 Cogent Embedded, Inc. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/of.h> |
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#include <linux/regmap.h> |
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#include <linux/reset.h> |
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#include <memory/renesas-rpc-if.h> |
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#define RPCIF_CMNCR 0x0000 /* R/W */ |
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#define RPCIF_CMNCR_MD BIT(31) |
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#define RPCIF_CMNCR_SFDE BIT(24) /* undocumented but must be set */ |
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#define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22) |
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#define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20) |
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#define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18) |
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#define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16) |
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#define RPCIF_CMNCR_MOIIO_HIZ (RPCIF_CMNCR_MOIIO0(3) | \ |
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RPCIF_CMNCR_MOIIO1(3) | \ |
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RPCIF_CMNCR_MOIIO2(3) | RPCIF_CMNCR_MOIIO3(3)) |
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#define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* undocumented */ |
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#define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* undocumented */ |
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#define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8) |
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#define RPCIF_CMNCR_IOFV_HIZ (RPCIF_CMNCR_IO0FV(3) | RPCIF_CMNCR_IO2FV(3) | \ |
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RPCIF_CMNCR_IO3FV(3)) |
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#define RPCIF_CMNCR_BSZ(val) (((val) & 0x3) << 0) |
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#define RPCIF_SSLDR 0x0004 /* R/W */ |
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#define RPCIF_SSLDR_SPNDL(d) (((d) & 0x7) << 16) |
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#define RPCIF_SSLDR_SLNDL(d) (((d) & 0x7) << 8) |
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#define RPCIF_SSLDR_SCKDL(d) (((d) & 0x7) << 0) |
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#define RPCIF_DRCR 0x000C /* R/W */ |
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#define RPCIF_DRCR_SSLN BIT(24) |
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#define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16) |
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#define RPCIF_DRCR_RCF BIT(9) |
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#define RPCIF_DRCR_RBE BIT(8) |
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#define RPCIF_DRCR_SSLE BIT(0) |
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#define RPCIF_DRCMR 0x0010 /* R/W */ |
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#define RPCIF_DRCMR_CMD(c) (((c) & 0xFF) << 16) |
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#define RPCIF_DRCMR_OCMD(c) (((c) & 0xFF) << 0) |
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#define RPCIF_DREAR 0x0014 /* R/W */ |
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#define RPCIF_DREAR_EAV(c) (((c) & 0xF) << 16) |
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#define RPCIF_DREAR_EAC(c) (((c) & 0x7) << 0) |
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#define RPCIF_DROPR 0x0018 /* R/W */ |
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#define RPCIF_DRENR 0x001C /* R/W */ |
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#define RPCIF_DRENR_CDB(o) (u32)((((o) & 0x3) << 30)) |
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#define RPCIF_DRENR_OCDB(o) (((o) & 0x3) << 28) |
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#define RPCIF_DRENR_ADB(o) (((o) & 0x3) << 24) |
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#define RPCIF_DRENR_OPDB(o) (((o) & 0x3) << 20) |
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#define RPCIF_DRENR_DRDB(o) (((o) & 0x3) << 16) |
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#define RPCIF_DRENR_DME BIT(15) |
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#define RPCIF_DRENR_CDE BIT(14) |
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#define RPCIF_DRENR_OCDE BIT(12) |
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#define RPCIF_DRENR_ADE(v) (((v) & 0xF) << 8) |
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#define RPCIF_DRENR_OPDE(v) (((v) & 0xF) << 4) |
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#define RPCIF_SMCR 0x0020 /* R/W */ |
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#define RPCIF_SMCR_SSLKP BIT(8) |
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#define RPCIF_SMCR_SPIRE BIT(2) |
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#define RPCIF_SMCR_SPIWE BIT(1) |
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#define RPCIF_SMCR_SPIE BIT(0) |
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#define RPCIF_SMCMR 0x0024 /* R/W */ |
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#define RPCIF_SMCMR_CMD(c) (((c) & 0xFF) << 16) |
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#define RPCIF_SMCMR_OCMD(c) (((c) & 0xFF) << 0) |
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#define RPCIF_SMADR 0x0028 /* R/W */ |
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#define RPCIF_SMOPR 0x002C /* R/W */ |
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#define RPCIF_SMOPR_OPD3(o) (((o) & 0xFF) << 24) |
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#define RPCIF_SMOPR_OPD2(o) (((o) & 0xFF) << 16) |
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#define RPCIF_SMOPR_OPD1(o) (((o) & 0xFF) << 8) |
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#define RPCIF_SMOPR_OPD0(o) (((o) & 0xFF) << 0) |
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#define RPCIF_SMENR 0x0030 /* R/W */ |
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#define RPCIF_SMENR_CDB(o) (((o) & 0x3) << 30) |
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#define RPCIF_SMENR_OCDB(o) (((o) & 0x3) << 28) |
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#define RPCIF_SMENR_ADB(o) (((o) & 0x3) << 24) |
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#define RPCIF_SMENR_OPDB(o) (((o) & 0x3) << 20) |
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#define RPCIF_SMENR_SPIDB(o) (((o) & 0x3) << 16) |
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#define RPCIF_SMENR_DME BIT(15) |
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#define RPCIF_SMENR_CDE BIT(14) |
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#define RPCIF_SMENR_OCDE BIT(12) |
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#define RPCIF_SMENR_ADE(v) (((v) & 0xF) << 8) |
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#define RPCIF_SMENR_OPDE(v) (((v) & 0xF) << 4) |
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#define RPCIF_SMENR_SPIDE(v) (((v) & 0xF) << 0) |
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#define RPCIF_SMRDR0 0x0038 /* R */ |
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#define RPCIF_SMRDR1 0x003C /* R */ |
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#define RPCIF_SMWDR0 0x0040 /* W */ |
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#define RPCIF_SMWDR1 0x0044 /* W */ |
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#define RPCIF_CMNSR 0x0048 /* R */ |
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#define RPCIF_CMNSR_SSLF BIT(1) |
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#define RPCIF_CMNSR_TEND BIT(0) |
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#define RPCIF_DRDMCR 0x0058 /* R/W */ |
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#define RPCIF_DMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0) |
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#define RPCIF_DRDRENR 0x005C /* R/W */ |
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#define RPCIF_DRDRENR_HYPE(v) (((v) & 0x7) << 12) |
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#define RPCIF_DRDRENR_ADDRE BIT(8) |
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#define RPCIF_DRDRENR_OPDRE BIT(4) |
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#define RPCIF_DRDRENR_DRDRE BIT(0) |
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#define RPCIF_SMDMCR 0x0060 /* R/W */ |
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#define RPCIF_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0) |
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#define RPCIF_SMDRENR 0x0064 /* R/W */ |
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#define RPCIF_SMDRENR_HYPE(v) (((v) & 0x7) << 12) |
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#define RPCIF_SMDRENR_ADDRE BIT(8) |
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#define RPCIF_SMDRENR_OPDRE BIT(4) |
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#define RPCIF_SMDRENR_SPIDRE BIT(0) |
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#define RPCIF_PHYCNT 0x007C /* R/W */ |
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#define RPCIF_PHYCNT_CAL BIT(31) |
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#define RPCIF_PHYCNT_OCTA(v) (((v) & 0x3) << 22) |
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#define RPCIF_PHYCNT_EXDS BIT(21) |
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#define RPCIF_PHYCNT_OCT BIT(20) |
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#define RPCIF_PHYCNT_DDRCAL BIT(19) |
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#define RPCIF_PHYCNT_HS BIT(18) |
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#define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15) |
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#define RPCIF_PHYCNT_WBUF2 BIT(4) |
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#define RPCIF_PHYCNT_WBUF BIT(2) |
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#define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0) |
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#define RPCIF_PHYOFFSET1 0x0080 /* R/W */ |
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#define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28) |
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#define RPCIF_PHYOFFSET2 0x0084 /* R/W */ |
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#define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8) |
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#define RPCIF_PHYINT 0x0088 /* R/W */ |
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#define RPCIF_PHYINT_WPVAL BIT(1) |
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#define RPCIF_DIRMAP_SIZE 0x4000000 |
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static const struct regmap_range rpcif_volatile_ranges[] = { |
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regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1), |
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regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1), |
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regmap_reg_range(RPCIF_CMNSR, RPCIF_CMNSR), |
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}; |
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static const struct regmap_access_table rpcif_volatile_table = { |
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.yes_ranges = rpcif_volatile_ranges, |
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.n_yes_ranges = ARRAY_SIZE(rpcif_volatile_ranges), |
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}; |
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static const struct regmap_config rpcif_regmap_config = { |
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.reg_bits = 32, |
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.val_bits = 32, |
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.reg_stride = 4, |
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.fast_io = true, |
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.max_register = RPCIF_PHYINT, |
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.volatile_table = &rpcif_volatile_table, |
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}; |
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int rpcif_sw_init(struct rpcif *rpc, struct device *dev) |
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{ |
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struct platform_device *pdev = to_platform_device(dev); |
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struct resource *res; |
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void __iomem *base; |
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rpc->dev = dev; |
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); |
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base = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(base)) |
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return PTR_ERR(base); |
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rpc->regmap = devm_regmap_init_mmio(&pdev->dev, base, |
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&rpcif_regmap_config); |
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if (IS_ERR(rpc->regmap)) { |
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dev_err(&pdev->dev, |
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"failed to init regmap for rpcif, error %ld\n", |
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PTR_ERR(rpc->regmap)); |
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return PTR_ERR(rpc->regmap); |
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} |
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap"); |
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rpc->dirmap = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(rpc->dirmap)) |
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rpc->dirmap = NULL; |
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rpc->size = resource_size(res); |
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rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); |
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return PTR_ERR_OR_ZERO(rpc->rstc); |
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} |
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EXPORT_SYMBOL(rpcif_sw_init); |
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void rpcif_hw_init(struct rpcif *rpc, bool hyperflash) |
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{ |
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u32 dummy; |
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pm_runtime_get_sync(rpc->dev); |
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/* |
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* NOTE: The 0x260 are undocumented bits, but they must be set. |
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* RPCIF_PHYCNT_STRTIM is strobe timing adjustment bits, |
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* 0x0 : the delay is biggest, |
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* 0x1 : the delay is 2nd biggest, |
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* On H3 ES1.x, the value should be 0, while on others, |
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* the value should be 7. |
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*/ |
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regmap_write(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7) | |
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RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260); |
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/* |
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* NOTE: The 0x1511144 are undocumented bits, but they must be set |
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* for RPCIF_PHYOFFSET1. |
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* The 0x31 are undocumented bits, but they must be set |
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* for RPCIF_PHYOFFSET2. |
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*/ |
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regmap_write(rpc->regmap, RPCIF_PHYOFFSET1, 0x1511144 | |
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RPCIF_PHYOFFSET1_DDRTMG(3)); |
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regmap_write(rpc->regmap, RPCIF_PHYOFFSET2, 0x31 | |
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RPCIF_PHYOFFSET2_OCTTMG(4)); |
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if (hyperflash) |
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regmap_update_bits(rpc->regmap, RPCIF_PHYINT, |
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RPCIF_PHYINT_WPVAL, 0); |
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regmap_write(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_SFDE | |
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RPCIF_CMNCR_MOIIO_HIZ | RPCIF_CMNCR_IOFV_HIZ | |
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RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); |
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/* Set RCF after BSZ update */ |
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regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF); |
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/* Dummy read according to spec */ |
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regmap_read(rpc->regmap, RPCIF_DRCR, &dummy); |
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regmap_write(rpc->regmap, RPCIF_SSLDR, RPCIF_SSLDR_SPNDL(7) | |
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RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7)); |
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pm_runtime_put(rpc->dev); |
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rpc->bus_size = hyperflash ? 2 : 1; |
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} |
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EXPORT_SYMBOL(rpcif_hw_init); |
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static int wait_msg_xfer_end(struct rpcif *rpc) |
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{ |
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u32 sts; |
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return regmap_read_poll_timeout(rpc->regmap, RPCIF_CMNSR, sts, |
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sts & RPCIF_CMNSR_TEND, 0, |
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USEC_PER_SEC); |
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} |
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static u8 rpcif_bits_set(struct rpcif *rpc, u32 nbytes) |
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{ |
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if (rpc->bus_size == 2) |
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nbytes /= 2; |
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nbytes = clamp(nbytes, 1U, 4U); |
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return GENMASK(3, 4 - nbytes); |
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} |
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static u8 rpcif_bit_size(u8 buswidth) |
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{ |
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return buswidth > 4 ? 2 : ilog2(buswidth); |
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} |
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void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs, |
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size_t *len) |
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{ |
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rpc->smcr = 0; |
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rpc->smadr = 0; |
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rpc->enable = 0; |
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rpc->command = 0; |
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rpc->option = 0; |
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rpc->dummy = 0; |
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rpc->ddr = 0; |
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rpc->xferlen = 0; |
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if (op->cmd.buswidth) { |
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rpc->enable = RPCIF_SMENR_CDE | |
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RPCIF_SMENR_CDB(rpcif_bit_size(op->cmd.buswidth)); |
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rpc->command = RPCIF_SMCMR_CMD(op->cmd.opcode); |
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if (op->cmd.ddr) |
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rpc->ddr = RPCIF_SMDRENR_HYPE(0x5); |
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} |
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if (op->ocmd.buswidth) { |
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rpc->enable |= RPCIF_SMENR_OCDE | |
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RPCIF_SMENR_OCDB(rpcif_bit_size(op->ocmd.buswidth)); |
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rpc->command |= RPCIF_SMCMR_OCMD(op->ocmd.opcode); |
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} |
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if (op->addr.buswidth) { |
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rpc->enable |= |
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RPCIF_SMENR_ADB(rpcif_bit_size(op->addr.buswidth)); |
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if (op->addr.nbytes == 4) |
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rpc->enable |= RPCIF_SMENR_ADE(0xF); |
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else |
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rpc->enable |= RPCIF_SMENR_ADE(GENMASK( |
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2, 3 - op->addr.nbytes)); |
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if (op->addr.ddr) |
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rpc->ddr |= RPCIF_SMDRENR_ADDRE; |
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if (offs && len) |
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rpc->smadr = *offs; |
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else |
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rpc->smadr = op->addr.val; |
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} |
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if (op->dummy.buswidth) { |
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rpc->enable |= RPCIF_SMENR_DME; |
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rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles / |
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op->dummy.buswidth); |
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} |
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if (op->option.buswidth) { |
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rpc->enable |= RPCIF_SMENR_OPDE( |
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rpcif_bits_set(rpc, op->option.nbytes)) | |
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RPCIF_SMENR_OPDB(rpcif_bit_size(op->option.buswidth)); |
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if (op->option.ddr) |
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rpc->ddr |= RPCIF_SMDRENR_OPDRE; |
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rpc->option = op->option.val; |
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} |
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rpc->dir = op->data.dir; |
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if (op->data.buswidth) { |
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u32 nbytes; |
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rpc->buffer = op->data.buf.in; |
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switch (op->data.dir) { |
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case RPCIF_DATA_IN: |
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rpc->smcr = RPCIF_SMCR_SPIRE; |
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break; |
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case RPCIF_DATA_OUT: |
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rpc->smcr = RPCIF_SMCR_SPIWE; |
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break; |
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default: |
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break; |
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} |
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if (op->data.ddr) |
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rpc->ddr |= RPCIF_SMDRENR_SPIDRE; |
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if (offs && len) |
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nbytes = *len; |
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else |
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nbytes = op->data.nbytes; |
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rpc->xferlen = nbytes; |
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rpc->enable |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes)) | |
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RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth)); |
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} |
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} |
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EXPORT_SYMBOL(rpcif_prepare); |
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int rpcif_manual_xfer(struct rpcif *rpc) |
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{ |
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u32 smenr, smcr, pos = 0, max = 4; |
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int ret = 0; |
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if (rpc->bus_size == 2) |
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max = 8; |
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pm_runtime_get_sync(rpc->dev); |
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regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, |
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RPCIF_PHYCNT_CAL, RPCIF_PHYCNT_CAL); |
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regmap_update_bits(rpc->regmap, RPCIF_CMNCR, |
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RPCIF_CMNCR_MD, RPCIF_CMNCR_MD); |
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regmap_write(rpc->regmap, RPCIF_SMCMR, rpc->command); |
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regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option); |
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regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy); |
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regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr); |
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smenr = rpc->enable; |
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switch (rpc->dir) { |
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case RPCIF_DATA_OUT: |
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while (pos < rpc->xferlen) { |
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u32 nbytes = rpc->xferlen - pos; |
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u32 data[2]; |
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smcr = rpc->smcr | RPCIF_SMCR_SPIE; |
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if (nbytes > max) { |
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nbytes = max; |
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smcr |= RPCIF_SMCR_SSLKP; |
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} |
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memcpy(data, rpc->buffer + pos, nbytes); |
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if (nbytes > 4) { |
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regmap_write(rpc->regmap, RPCIF_SMWDR1, |
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data[0]); |
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regmap_write(rpc->regmap, RPCIF_SMWDR0, |
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data[1]); |
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} else if (nbytes > 2) { |
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regmap_write(rpc->regmap, RPCIF_SMWDR0, |
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data[0]); |
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} else { |
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regmap_write(rpc->regmap, RPCIF_SMWDR0, |
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data[0] << 16); |
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} |
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regmap_write(rpc->regmap, RPCIF_SMADR, |
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rpc->smadr + pos); |
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regmap_write(rpc->regmap, RPCIF_SMENR, smenr); |
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regmap_write(rpc->regmap, RPCIF_SMCR, smcr); |
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ret = wait_msg_xfer_end(rpc); |
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if (ret) |
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goto err_out; |
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pos += nbytes; |
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smenr = rpc->enable & |
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~RPCIF_SMENR_CDE & ~RPCIF_SMENR_ADE(0xF); |
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} |
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break; |
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case RPCIF_DATA_IN: |
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/* |
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* RPC-IF spoils the data for the commands without an address |
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* phase (like RDID) in the manual mode, so we'll have to work |
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* around this issue by using the external address space read |
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* mode instead. |
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*/ |
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if (!(smenr & RPCIF_SMENR_ADE(0xF)) && rpc->dirmap) { |
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u32 dummy; |
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regmap_update_bits(rpc->regmap, RPCIF_CMNCR, |
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RPCIF_CMNCR_MD, 0); |
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regmap_write(rpc->regmap, RPCIF_DRCR, |
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RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE); |
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regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command); |
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regmap_write(rpc->regmap, RPCIF_DREAR, |
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RPCIF_DREAR_EAC(1)); |
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regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option); |
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regmap_write(rpc->regmap, RPCIF_DRENR, |
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smenr & ~RPCIF_SMENR_SPIDE(0xF)); |
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regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy); |
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regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr); |
|
memcpy_fromio(rpc->buffer, rpc->dirmap, rpc->xferlen); |
|
regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF); |
|
/* Dummy read according to spec */ |
|
regmap_read(rpc->regmap, RPCIF_DRCR, &dummy); |
|
break; |
|
} |
|
while (pos < rpc->xferlen) { |
|
u32 nbytes = rpc->xferlen - pos; |
|
u32 data[2]; |
|
|
|
if (nbytes > max) |
|
nbytes = max; |
|
|
|
regmap_write(rpc->regmap, RPCIF_SMADR, |
|
rpc->smadr + pos); |
|
regmap_write(rpc->regmap, RPCIF_SMENR, smenr); |
|
regmap_write(rpc->regmap, RPCIF_SMCR, |
|
rpc->smcr | RPCIF_SMCR_SPIE); |
|
ret = wait_msg_xfer_end(rpc); |
|
if (ret) |
|
goto err_out; |
|
|
|
if (nbytes > 4) { |
|
regmap_read(rpc->regmap, RPCIF_SMRDR1, |
|
&data[0]); |
|
regmap_read(rpc->regmap, RPCIF_SMRDR0, |
|
&data[1]); |
|
} else if (nbytes > 2) { |
|
regmap_read(rpc->regmap, RPCIF_SMRDR0, |
|
&data[0]); |
|
} else { |
|
regmap_read(rpc->regmap, RPCIF_SMRDR0, |
|
&data[0]); |
|
data[0] >>= 16; |
|
} |
|
memcpy(rpc->buffer + pos, data, nbytes); |
|
|
|
pos += nbytes; |
|
} |
|
break; |
|
default: |
|
regmap_write(rpc->regmap, RPCIF_SMENR, rpc->enable); |
|
regmap_write(rpc->regmap, RPCIF_SMCR, |
|
rpc->smcr | RPCIF_SMCR_SPIE); |
|
ret = wait_msg_xfer_end(rpc); |
|
if (ret) |
|
goto err_out; |
|
} |
|
|
|
exit: |
|
pm_runtime_put(rpc->dev); |
|
return ret; |
|
|
|
err_out: |
|
if (reset_control_reset(rpc->rstc)) |
|
dev_err(rpc->dev, "Failed to reset HW\n"); |
|
rpcif_hw_init(rpc, rpc->bus_size == 2); |
|
goto exit; |
|
} |
|
EXPORT_SYMBOL(rpcif_manual_xfer); |
|
|
|
ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf) |
|
{ |
|
loff_t from = offs & (RPCIF_DIRMAP_SIZE - 1); |
|
size_t size = RPCIF_DIRMAP_SIZE - from; |
|
|
|
if (len > size) |
|
len = size; |
|
|
|
pm_runtime_get_sync(rpc->dev); |
|
|
|
regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0); |
|
regmap_write(rpc->regmap, RPCIF_DRCR, 0); |
|
regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command); |
|
regmap_write(rpc->regmap, RPCIF_DREAR, |
|
RPCIF_DREAR_EAV(offs >> 25) | RPCIF_DREAR_EAC(1)); |
|
regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option); |
|
regmap_write(rpc->regmap, RPCIF_DRENR, |
|
rpc->enable & ~RPCIF_SMENR_SPIDE(0xF)); |
|
regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy); |
|
regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr); |
|
|
|
memcpy_fromio(buf, rpc->dirmap + from, len); |
|
|
|
pm_runtime_put(rpc->dev); |
|
|
|
return len; |
|
} |
|
EXPORT_SYMBOL(rpcif_dirmap_read); |
|
|
|
static int rpcif_probe(struct platform_device *pdev) |
|
{ |
|
struct platform_device *vdev; |
|
struct device_node *flash; |
|
const char *name; |
|
|
|
flash = of_get_next_child(pdev->dev.of_node, NULL); |
|
if (!flash) { |
|
dev_warn(&pdev->dev, "no flash node found\n"); |
|
return -ENODEV; |
|
} |
|
|
|
if (of_device_is_compatible(flash, "jedec,spi-nor")) { |
|
name = "rpc-if-spi"; |
|
} else if (of_device_is_compatible(flash, "cfi-flash")) { |
|
name = "rpc-if-hyperflash"; |
|
} else { |
|
of_node_put(flash); |
|
dev_warn(&pdev->dev, "unknown flash type\n"); |
|
return -ENODEV; |
|
} |
|
of_node_put(flash); |
|
|
|
vdev = platform_device_alloc(name, pdev->id); |
|
if (!vdev) |
|
return -ENOMEM; |
|
vdev->dev.parent = &pdev->dev; |
|
platform_set_drvdata(pdev, vdev); |
|
return platform_device_add(vdev); |
|
} |
|
|
|
static int rpcif_remove(struct platform_device *pdev) |
|
{ |
|
struct platform_device *vdev = platform_get_drvdata(pdev); |
|
|
|
platform_device_unregister(vdev); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id rpcif_of_match[] = { |
|
{ .compatible = "renesas,rcar-gen3-rpc-if", }, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, rpcif_of_match); |
|
|
|
static struct platform_driver rpcif_driver = { |
|
.probe = rpcif_probe, |
|
.remove = rpcif_remove, |
|
.driver = { |
|
.name = "rpc-if", |
|
.of_match_table = rpcif_of_match, |
|
}, |
|
}; |
|
module_platform_driver(rpcif_driver); |
|
|
|
MODULE_DESCRIPTION("Renesas RPC-IF core driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|