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423 lines
10 KiB
423 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* JZ4780 NAND/external memory controller (NEMC) |
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* |
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* Copyright (c) 2015 Imagination Technologies |
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* Author: Alex Smith <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/math64.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/of_platform.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/spinlock.h> |
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#include <linux/jz4780-nemc.h> |
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#define NEMC_SMCRn(n) (0x14 + (((n) - 1) * 4)) |
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#define NEMC_NFCSR 0x50 |
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#define NEMC_REG_LEN 0x54 |
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#define NEMC_SMCR_SMT BIT(0) |
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#define NEMC_SMCR_BW_SHIFT 6 |
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#define NEMC_SMCR_BW_MASK (0x3 << NEMC_SMCR_BW_SHIFT) |
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#define NEMC_SMCR_BW_8 (0 << 6) |
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#define NEMC_SMCR_TAS_SHIFT 8 |
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#define NEMC_SMCR_TAS_MASK (0xf << NEMC_SMCR_TAS_SHIFT) |
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#define NEMC_SMCR_TAH_SHIFT 12 |
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#define NEMC_SMCR_TAH_MASK (0xf << NEMC_SMCR_TAH_SHIFT) |
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#define NEMC_SMCR_TBP_SHIFT 16 |
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#define NEMC_SMCR_TBP_MASK (0xf << NEMC_SMCR_TBP_SHIFT) |
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#define NEMC_SMCR_TAW_SHIFT 20 |
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#define NEMC_SMCR_TAW_MASK (0xf << NEMC_SMCR_TAW_SHIFT) |
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#define NEMC_SMCR_TSTRV_SHIFT 24 |
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#define NEMC_SMCR_TSTRV_MASK (0x3f << NEMC_SMCR_TSTRV_SHIFT) |
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#define NEMC_NFCSR_NFEn(n) BIT(((n) - 1) << 1) |
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#define NEMC_NFCSR_NFCEn(n) BIT((((n) - 1) << 1) + 1) |
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#define NEMC_NFCSR_TNFEn(n) BIT(16 + (n) - 1) |
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struct jz_soc_info { |
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u8 tas_tah_cycles_max; |
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}; |
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struct jz4780_nemc { |
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spinlock_t lock; |
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struct device *dev; |
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const struct jz_soc_info *soc_info; |
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void __iomem *base; |
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struct clk *clk; |
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uint32_t clk_period; |
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unsigned long banks_present; |
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}; |
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/** |
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* jz4780_nemc_num_banks() - count the number of banks referenced by a device |
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* @dev: device to count banks for, must be a child of the NEMC. |
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* |
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* Return: The number of unique NEMC banks referred to by the specified NEMC |
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* child device. Unique here means that a device that references the same bank |
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* multiple times in its "reg" property will only count once. |
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*/ |
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unsigned int jz4780_nemc_num_banks(struct device *dev) |
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{ |
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const __be32 *prop; |
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unsigned int bank, count = 0; |
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unsigned long referenced = 0; |
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int i = 0; |
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while ((prop = of_get_address(dev->of_node, i++, NULL, NULL))) { |
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bank = of_read_number(prop, 1); |
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if (!(referenced & BIT(bank))) { |
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referenced |= BIT(bank); |
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count++; |
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} |
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} |
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return count; |
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} |
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EXPORT_SYMBOL(jz4780_nemc_num_banks); |
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/** |
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* jz4780_nemc_set_type() - set the type of device connected to a bank |
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* @dev: child device of the NEMC. |
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* @bank: bank number to configure. |
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* @type: type of device connected to the bank. |
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*/ |
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void jz4780_nemc_set_type(struct device *dev, unsigned int bank, |
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enum jz4780_nemc_bank_type type) |
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{ |
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struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent); |
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uint32_t nfcsr; |
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nfcsr = readl(nemc->base + NEMC_NFCSR); |
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/* TODO: Support toggle NAND devices. */ |
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switch (type) { |
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case JZ4780_NEMC_BANK_SRAM: |
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nfcsr &= ~(NEMC_NFCSR_TNFEn(bank) | NEMC_NFCSR_NFEn(bank)); |
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break; |
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case JZ4780_NEMC_BANK_NAND: |
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nfcsr &= ~NEMC_NFCSR_TNFEn(bank); |
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nfcsr |= NEMC_NFCSR_NFEn(bank); |
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break; |
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} |
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writel(nfcsr, nemc->base + NEMC_NFCSR); |
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} |
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EXPORT_SYMBOL(jz4780_nemc_set_type); |
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/** |
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* jz4780_nemc_assert() - (de-)assert a NAND device's chip enable pin |
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* @dev: child device of the NEMC. |
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* @bank: bank number of device. |
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* @assert: whether the chip enable pin should be asserted. |
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* |
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* (De-)asserts the chip enable pin for the NAND device connected to the |
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* specified bank. |
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*/ |
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void jz4780_nemc_assert(struct device *dev, unsigned int bank, bool assert) |
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{ |
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struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent); |
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uint32_t nfcsr; |
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nfcsr = readl(nemc->base + NEMC_NFCSR); |
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if (assert) |
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nfcsr |= NEMC_NFCSR_NFCEn(bank); |
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else |
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nfcsr &= ~NEMC_NFCSR_NFCEn(bank); |
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writel(nfcsr, nemc->base + NEMC_NFCSR); |
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} |
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EXPORT_SYMBOL(jz4780_nemc_assert); |
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static uint32_t jz4780_nemc_clk_period(struct jz4780_nemc *nemc) |
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{ |
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unsigned long rate; |
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rate = clk_get_rate(nemc->clk); |
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if (!rate) |
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return 0; |
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/* Return in picoseconds. */ |
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return div64_ul(1000000000000ull, rate); |
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} |
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static uint32_t jz4780_nemc_ns_to_cycles(struct jz4780_nemc *nemc, uint32_t ns) |
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{ |
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return ((ns * 1000) + nemc->clk_period - 1) / nemc->clk_period; |
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} |
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static bool jz4780_nemc_configure_bank(struct jz4780_nemc *nemc, |
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unsigned int bank, |
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struct device_node *node) |
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{ |
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uint32_t smcr, val, cycles; |
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/* |
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* Conversion of tBP and tAW cycle counts to values supported by the |
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* hardware (round up to the next supported value). |
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*/ |
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static const u8 convert_tBP_tAW[] = { |
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, |
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/* 11 - 12 -> 12 cycles */ |
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11, 11, |
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/* 13 - 15 -> 15 cycles */ |
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12, 12, 12, |
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/* 16 - 20 -> 20 cycles */ |
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13, 13, 13, 13, 13, |
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/* 21 - 25 -> 25 cycles */ |
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14, 14, 14, 14, 14, |
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/* 26 - 31 -> 31 cycles */ |
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15, 15, 15, 15, 15, 15 |
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}; |
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smcr = readl(nemc->base + NEMC_SMCRn(bank)); |
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smcr &= ~NEMC_SMCR_SMT; |
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if (!of_property_read_u32(node, "ingenic,nemc-bus-width", &val)) { |
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smcr &= ~NEMC_SMCR_BW_MASK; |
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switch (val) { |
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case 8: |
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smcr |= NEMC_SMCR_BW_8; |
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break; |
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default: |
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/* |
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* Earlier SoCs support a 16 bit bus width (the 4780 |
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* does not), until those are properly supported, error. |
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*/ |
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dev_err(nemc->dev, "unsupported bus width: %u\n", val); |
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return false; |
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} |
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} |
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if (of_property_read_u32(node, "ingenic,nemc-tAS", &val) == 0) { |
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smcr &= ~NEMC_SMCR_TAS_MASK; |
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cycles = jz4780_nemc_ns_to_cycles(nemc, val); |
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if (cycles > nemc->soc_info->tas_tah_cycles_max) { |
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dev_err(nemc->dev, "tAS %u is too high (%u cycles)\n", |
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val, cycles); |
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return false; |
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} |
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smcr |= cycles << NEMC_SMCR_TAS_SHIFT; |
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} |
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if (of_property_read_u32(node, "ingenic,nemc-tAH", &val) == 0) { |
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smcr &= ~NEMC_SMCR_TAH_MASK; |
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cycles = jz4780_nemc_ns_to_cycles(nemc, val); |
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if (cycles > nemc->soc_info->tas_tah_cycles_max) { |
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dev_err(nemc->dev, "tAH %u is too high (%u cycles)\n", |
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val, cycles); |
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return false; |
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} |
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smcr |= cycles << NEMC_SMCR_TAH_SHIFT; |
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} |
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if (of_property_read_u32(node, "ingenic,nemc-tBP", &val) == 0) { |
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smcr &= ~NEMC_SMCR_TBP_MASK; |
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cycles = jz4780_nemc_ns_to_cycles(nemc, val); |
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if (cycles > 31) { |
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dev_err(nemc->dev, "tBP %u is too high (%u cycles)\n", |
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val, cycles); |
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return false; |
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} |
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smcr |= convert_tBP_tAW[cycles] << NEMC_SMCR_TBP_SHIFT; |
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} |
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if (of_property_read_u32(node, "ingenic,nemc-tAW", &val) == 0) { |
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smcr &= ~NEMC_SMCR_TAW_MASK; |
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cycles = jz4780_nemc_ns_to_cycles(nemc, val); |
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if (cycles > 31) { |
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dev_err(nemc->dev, "tAW %u is too high (%u cycles)\n", |
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val, cycles); |
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return false; |
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} |
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smcr |= convert_tBP_tAW[cycles] << NEMC_SMCR_TAW_SHIFT; |
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} |
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if (of_property_read_u32(node, "ingenic,nemc-tSTRV", &val) == 0) { |
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smcr &= ~NEMC_SMCR_TSTRV_MASK; |
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cycles = jz4780_nemc_ns_to_cycles(nemc, val); |
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if (cycles > 63) { |
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dev_err(nemc->dev, "tSTRV %u is too high (%u cycles)\n", |
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val, cycles); |
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return false; |
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} |
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smcr |= cycles << NEMC_SMCR_TSTRV_SHIFT; |
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} |
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writel(smcr, nemc->base + NEMC_SMCRn(bank)); |
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return true; |
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} |
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static int jz4780_nemc_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct jz4780_nemc *nemc; |
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struct resource *res; |
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struct device_node *child; |
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const __be32 *prop; |
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unsigned int bank; |
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unsigned long referenced; |
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int i, ret; |
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nemc = devm_kzalloc(dev, sizeof(*nemc), GFP_KERNEL); |
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if (!nemc) |
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return -ENOMEM; |
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nemc->soc_info = device_get_match_data(dev); |
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if (!nemc->soc_info) |
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return -EINVAL; |
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spin_lock_init(&nemc->lock); |
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nemc->dev = dev; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (!res) |
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return -EINVAL; |
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/* |
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* The driver currently only uses the registers up to offset |
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* NEMC_REG_LEN. Since the EFUSE registers are in the middle of the |
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* NEMC registers, we only request the registers we will use for now; |
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* that way the EFUSE driver can probe too. |
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*/ |
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if (!devm_request_mem_region(dev, res->start, NEMC_REG_LEN, dev_name(dev))) { |
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dev_err(dev, "unable to request I/O memory region\n"); |
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return -EBUSY; |
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} |
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nemc->base = devm_ioremap(dev, res->start, NEMC_REG_LEN); |
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if (!nemc->base) { |
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dev_err(dev, "failed to get I/O memory\n"); |
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return -ENOMEM; |
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} |
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writel(0, nemc->base + NEMC_NFCSR); |
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nemc->clk = devm_clk_get(dev, NULL); |
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if (IS_ERR(nemc->clk)) { |
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dev_err(dev, "failed to get clock\n"); |
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return PTR_ERR(nemc->clk); |
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} |
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ret = clk_prepare_enable(nemc->clk); |
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if (ret) { |
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dev_err(dev, "failed to enable clock: %d\n", ret); |
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return ret; |
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} |
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nemc->clk_period = jz4780_nemc_clk_period(nemc); |
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if (!nemc->clk_period) { |
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dev_err(dev, "failed to calculate clock period\n"); |
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clk_disable_unprepare(nemc->clk); |
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return -EINVAL; |
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} |
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/* |
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* Iterate over child devices, check that they do not conflict with |
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* each other, and register child devices for them. If a child device |
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* has invalid properties, it is ignored and no platform device is |
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* registered for it. |
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*/ |
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for_each_child_of_node(nemc->dev->of_node, child) { |
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referenced = 0; |
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i = 0; |
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while ((prop = of_get_address(child, i++, NULL, NULL))) { |
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bank = of_read_number(prop, 1); |
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if (bank < 1 || bank >= JZ4780_NEMC_NUM_BANKS) { |
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dev_err(nemc->dev, |
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"%pOF requests invalid bank %u\n", |
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child, bank); |
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/* Will continue the outer loop below. */ |
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referenced = 0; |
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break; |
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} |
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referenced |= BIT(bank); |
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} |
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if (!referenced) { |
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dev_err(nemc->dev, "%pOF has no addresses\n", |
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child); |
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continue; |
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} else if (nemc->banks_present & referenced) { |
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dev_err(nemc->dev, "%pOF conflicts with another node\n", |
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child); |
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continue; |
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} |
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/* Configure bank parameters. */ |
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for_each_set_bit(bank, &referenced, JZ4780_NEMC_NUM_BANKS) { |
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if (!jz4780_nemc_configure_bank(nemc, bank, child)) { |
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referenced = 0; |
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break; |
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} |
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} |
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if (referenced) { |
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if (of_platform_device_create(child, NULL, nemc->dev)) |
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nemc->banks_present |= referenced; |
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} |
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} |
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platform_set_drvdata(pdev, nemc); |
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dev_info(dev, "JZ4780 NEMC initialised\n"); |
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return 0; |
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} |
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static int jz4780_nemc_remove(struct platform_device *pdev) |
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{ |
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struct jz4780_nemc *nemc = platform_get_drvdata(pdev); |
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clk_disable_unprepare(nemc->clk); |
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return 0; |
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} |
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static const struct jz_soc_info jz4740_soc_info = { |
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.tas_tah_cycles_max = 7, |
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}; |
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static const struct jz_soc_info jz4780_soc_info = { |
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.tas_tah_cycles_max = 15, |
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}; |
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static const struct of_device_id jz4780_nemc_dt_match[] = { |
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{ .compatible = "ingenic,jz4740-nemc", .data = &jz4740_soc_info, }, |
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{ .compatible = "ingenic,jz4780-nemc", .data = &jz4780_soc_info, }, |
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{}, |
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}; |
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static struct platform_driver jz4780_nemc_driver = { |
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.probe = jz4780_nemc_probe, |
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.remove = jz4780_nemc_remove, |
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.driver = { |
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.name = "jz4780-nemc", |
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.of_match_table = of_match_ptr(jz4780_nemc_dt_match), |
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}, |
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}; |
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static int __init jz4780_nemc_init(void) |
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{ |
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return platform_driver_register(&jz4780_nemc_driver); |
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} |
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subsys_initcall(jz4780_nemc_init);
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