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290 lines
7.9 KiB
290 lines
7.9 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Generic Broadcom Set Top Box Level 2 Interrupt controller driver |
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* |
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* Copyright (C) 2014-2017 Broadcom |
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*/ |
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <linux/init.h> |
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#include <linux/slab.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/spinlock.h> |
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#include <linux/of.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_address.h> |
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#include <linux/of_platform.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/io.h> |
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#include <linux/irqdomain.h> |
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#include <linux/irqchip.h> |
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#include <linux/irqchip/chained_irq.h> |
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struct brcmstb_intc_init_params { |
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irq_flow_handler_t handler; |
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int cpu_status; |
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int cpu_clear; |
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int cpu_mask_status; |
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int cpu_mask_set; |
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int cpu_mask_clear; |
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}; |
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/* Register offsets in the L2 latched interrupt controller */ |
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static const struct brcmstb_intc_init_params l2_edge_intc_init = { |
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.handler = handle_edge_irq, |
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.cpu_status = 0x00, |
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.cpu_clear = 0x08, |
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.cpu_mask_status = 0x0c, |
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.cpu_mask_set = 0x10, |
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.cpu_mask_clear = 0x14 |
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}; |
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/* Register offsets in the L2 level interrupt controller */ |
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static const struct brcmstb_intc_init_params l2_lvl_intc_init = { |
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.handler = handle_level_irq, |
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.cpu_status = 0x00, |
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.cpu_clear = -1, /* Register not present */ |
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.cpu_mask_status = 0x04, |
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.cpu_mask_set = 0x08, |
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.cpu_mask_clear = 0x0C |
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}; |
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/* L2 intc private data structure */ |
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struct brcmstb_l2_intc_data { |
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struct irq_domain *domain; |
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struct irq_chip_generic *gc; |
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int status_offset; |
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int mask_offset; |
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bool can_wake; |
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u32 saved_mask; /* for suspend/resume */ |
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}; |
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/** |
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* brcmstb_l2_mask_and_ack - Mask and ack pending interrupt |
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* @d: irq_data |
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* |
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* Chip has separate enable/disable registers instead of a single mask |
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* register and pending interrupt is acknowledged by setting a bit. |
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* |
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* Note: This function is generic and could easily be added to the |
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* generic irqchip implementation if there ever becomes a will to do so. |
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* Perhaps with a name like irq_gc_mask_disable_and_ack_set(). |
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* |
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* e.g.: https://patchwork.kernel.org/patch/9831047/ |
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*/ |
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static void brcmstb_l2_mask_and_ack(struct irq_data *d) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct irq_chip_type *ct = irq_data_get_chip_type(d); |
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u32 mask = d->mask; |
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irq_gc_lock(gc); |
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irq_reg_writel(gc, mask, ct->regs.disable); |
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*ct->mask_cache &= ~mask; |
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irq_reg_writel(gc, mask, ct->regs.ack); |
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irq_gc_unlock(gc); |
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} |
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static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc) |
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{ |
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struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc); |
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struct irq_chip *chip = irq_desc_get_chip(desc); |
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unsigned int irq; |
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u32 status; |
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chained_irq_enter(chip, desc); |
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status = irq_reg_readl(b->gc, b->status_offset) & |
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~(irq_reg_readl(b->gc, b->mask_offset)); |
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if (status == 0) { |
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raw_spin_lock(&desc->lock); |
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handle_bad_irq(desc); |
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raw_spin_unlock(&desc->lock); |
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goto out; |
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} |
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do { |
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irq = ffs(status) - 1; |
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status &= ~(1 << irq); |
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generic_handle_domain_irq(b->domain, irq); |
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} while (status); |
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out: |
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chained_irq_exit(chip, desc); |
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} |
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static void brcmstb_l2_intc_suspend(struct irq_data *d) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct irq_chip_type *ct = irq_data_get_chip_type(d); |
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struct brcmstb_l2_intc_data *b = gc->private; |
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unsigned long flags; |
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irq_gc_lock_irqsave(gc, flags); |
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/* Save the current mask */ |
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b->saved_mask = irq_reg_readl(gc, ct->regs.mask); |
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if (b->can_wake) { |
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/* Program the wakeup mask */ |
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irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable); |
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irq_reg_writel(gc, gc->wake_active, ct->regs.enable); |
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} |
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irq_gc_unlock_irqrestore(gc, flags); |
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} |
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static void brcmstb_l2_intc_resume(struct irq_data *d) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct irq_chip_type *ct = irq_data_get_chip_type(d); |
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struct brcmstb_l2_intc_data *b = gc->private; |
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unsigned long flags; |
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irq_gc_lock_irqsave(gc, flags); |
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if (ct->chip.irq_ack) { |
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/* Clear unmasked non-wakeup interrupts */ |
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irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active, |
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ct->regs.ack); |
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} |
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/* Restore the saved mask */ |
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irq_reg_writel(gc, b->saved_mask, ct->regs.disable); |
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irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable); |
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irq_gc_unlock_irqrestore(gc, flags); |
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} |
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static int __init brcmstb_l2_intc_of_init(struct device_node *np, |
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struct device_node *parent, |
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const struct brcmstb_intc_init_params |
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*init_params) |
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{ |
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; |
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struct brcmstb_l2_intc_data *data; |
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struct irq_chip_type *ct; |
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int ret; |
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unsigned int flags; |
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int parent_irq; |
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void __iomem *base; |
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data = kzalloc(sizeof(*data), GFP_KERNEL); |
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if (!data) |
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return -ENOMEM; |
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base = of_iomap(np, 0); |
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if (!base) { |
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pr_err("failed to remap intc L2 registers\n"); |
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ret = -ENOMEM; |
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goto out_free; |
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} |
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/* Disable all interrupts by default */ |
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writel(0xffffffff, base + init_params->cpu_mask_set); |
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/* Wakeup interrupts may be retained from S5 (cold boot) */ |
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data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake"); |
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if (!data->can_wake && (init_params->cpu_clear >= 0)) |
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writel(0xffffffff, base + init_params->cpu_clear); |
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parent_irq = irq_of_parse_and_map(np, 0); |
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if (!parent_irq) { |
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pr_err("failed to find parent interrupt\n"); |
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ret = -EINVAL; |
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goto out_unmap; |
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} |
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data->domain = irq_domain_add_linear(np, 32, |
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&irq_generic_chip_ops, NULL); |
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if (!data->domain) { |
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ret = -ENOMEM; |
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goto out_unmap; |
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} |
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/* MIPS chips strapped for BE will automagically configure the |
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* peripheral registers for CPU-native byte order. |
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*/ |
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flags = 0; |
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) |
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flags |= IRQ_GC_BE_IO; |
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/* Allocate a single Generic IRQ chip for this node */ |
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ret = irq_alloc_domain_generic_chips(data->domain, 32, 1, |
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np->full_name, init_params->handler, clr, 0, flags); |
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if (ret) { |
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pr_err("failed to allocate generic irq chip\n"); |
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goto out_free_domain; |
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} |
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/* Set the IRQ chaining logic */ |
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irq_set_chained_handler_and_data(parent_irq, |
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brcmstb_l2_intc_irq_handle, data); |
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data->gc = irq_get_domain_generic_chip(data->domain, 0); |
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data->gc->reg_base = base; |
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data->gc->private = data; |
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data->status_offset = init_params->cpu_status; |
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data->mask_offset = init_params->cpu_mask_status; |
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ct = data->gc->chip_types; |
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if (init_params->cpu_clear >= 0) { |
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ct->regs.ack = init_params->cpu_clear; |
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ct->chip.irq_ack = irq_gc_ack_set_bit; |
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ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack; |
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} else { |
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/* No Ack - but still slightly more efficient to define this */ |
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ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; |
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} |
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ct->chip.irq_mask = irq_gc_mask_disable_reg; |
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ct->regs.disable = init_params->cpu_mask_set; |
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ct->regs.mask = init_params->cpu_mask_status; |
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ct->chip.irq_unmask = irq_gc_unmask_enable_reg; |
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ct->regs.enable = init_params->cpu_mask_clear; |
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ct->chip.irq_suspend = brcmstb_l2_intc_suspend; |
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ct->chip.irq_resume = brcmstb_l2_intc_resume; |
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ct->chip.irq_pm_shutdown = brcmstb_l2_intc_suspend; |
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if (data->can_wake) { |
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/* This IRQ chip can wake the system, set all child interrupts |
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* in wake_enabled mask |
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*/ |
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data->gc->wake_enabled = 0xffffffff; |
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ct->chip.irq_set_wake = irq_gc_set_wake; |
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enable_irq_wake(parent_irq); |
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} |
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pr_info("registered L2 intc (%pOF, parent irq: %d)\n", np, parent_irq); |
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return 0; |
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out_free_domain: |
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irq_domain_remove(data->domain); |
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out_unmap: |
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iounmap(base); |
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out_free: |
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kfree(data); |
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return ret; |
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} |
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static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np, |
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struct device_node *parent) |
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{ |
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return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init); |
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} |
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IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init); |
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IRQCHIP_DECLARE(brcmstb_hif_spi_l2_intc, "brcm,hif-spi-l2-intc", |
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brcmstb_l2_edge_intc_of_init); |
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IRQCHIP_DECLARE(brcmstb_upg_aux_aon_l2_intc, "brcm,upg-aux-aon-l2-intc", |
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brcmstb_l2_edge_intc_of_init); |
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static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np, |
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struct device_node *parent) |
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{ |
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return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init); |
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} |
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IRQCHIP_DECLARE(bcm7271_l2_intc, "brcm,bcm7271-l2-intc", |
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brcmstb_l2_lvl_intc_of_init);
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