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226 lines
7.0 KiB
226 lines
7.0 KiB
/* |
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* Broadcom NetXtreme-E RoCE driver. |
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* |
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* Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term |
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* Broadcom refers to Broadcom Limited and/or its subsidiaries. |
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* |
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* This software is available to you under a choice of one of two |
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* licenses. You may choose to be licensed under the terms of the GNU |
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* General Public License (GPL) Version 2, available from the file |
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* COPYING in the main directory of this source tree, or the |
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* BSD license below: |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' |
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS |
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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* Description: RDMA Controller HW interface (header) |
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*/ |
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#ifndef __BNXT_QPLIB_RCFW_H__ |
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#define __BNXT_QPLIB_RCFW_H__ |
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#define RCFW_CMDQ_TRIG_VAL 1 |
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#define RCFW_COMM_PCI_BAR_REGION 0 |
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#define RCFW_COMM_CONS_PCI_BAR_REGION 2 |
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#define RCFW_COMM_BASE_OFFSET 0x600 |
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#define RCFW_PF_COMM_PROD_OFFSET 0xc |
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#define RCFW_VF_COMM_PROD_OFFSET 0xc |
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#define RCFW_COMM_TRIG_OFFSET 0x100 |
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#define RCFW_COMM_SIZE 0x104 |
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#define RCFW_DBR_PCI_BAR_REGION 2 |
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#define RCFW_DBR_BASE_PAGE_SHIFT 12 |
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#define RCFW_CMD_PREP(req, CMD, cmd_flags) \ |
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do { \ |
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memset(&(req), 0, sizeof((req))); \ |
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(req).opcode = CMDQ_BASE_OPCODE_##CMD; \ |
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(req).cmd_size = sizeof((req)); \ |
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(req).flags = cpu_to_le16(cmd_flags); \ |
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} while (0) |
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#define RCFW_CMD_WAIT_TIME_MS 20000 /* 20 Seconds timeout */ |
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/* Cmdq contains a fix number of a 16-Byte slots */ |
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struct bnxt_qplib_cmdqe { |
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u8 data[16]; |
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}; |
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/* CMDQ elements */ |
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#define BNXT_QPLIB_CMDQE_MAX_CNT_256 256 |
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#define BNXT_QPLIB_CMDQE_MAX_CNT_8192 8192 |
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#define BNXT_QPLIB_CMDQE_UNITS sizeof(struct bnxt_qplib_cmdqe) |
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#define BNXT_QPLIB_CMDQE_BYTES(depth) ((depth) * BNXT_QPLIB_CMDQE_UNITS) |
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static inline u32 bnxt_qplib_cmdqe_npages(u32 depth) |
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{ |
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u32 npages; |
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npages = BNXT_QPLIB_CMDQE_BYTES(depth) / PAGE_SIZE; |
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if (BNXT_QPLIB_CMDQE_BYTES(depth) % PAGE_SIZE) |
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npages++; |
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return npages; |
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} |
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static inline u32 bnxt_qplib_cmdqe_page_size(u32 depth) |
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{ |
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return (bnxt_qplib_cmdqe_npages(depth) * PAGE_SIZE); |
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} |
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/* Set the cmd_size to a factor of CMDQE unit */ |
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static inline void bnxt_qplib_set_cmd_slots(struct cmdq_base *req) |
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{ |
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req->cmd_size = (req->cmd_size + BNXT_QPLIB_CMDQE_UNITS - 1) / |
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BNXT_QPLIB_CMDQE_UNITS; |
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} |
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#define RCFW_MAX_COOKIE_VALUE 0x7FFF |
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#define RCFW_CMD_IS_BLOCKING 0x8000 |
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#define RCFW_BLOCKED_CMD_WAIT_COUNT 0x4E20 |
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#define HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK 0x1000900020011ULL |
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/* Crsq buf is 1024-Byte */ |
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struct bnxt_qplib_crsbe { |
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u8 data[1024]; |
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}; |
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/* CREQ */ |
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/* Allocate 1 per QP for async error notification for now */ |
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#define BNXT_QPLIB_CREQE_MAX_CNT (64 * 1024) |
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#define BNXT_QPLIB_CREQE_UNITS 16 /* 16-Bytes per prod unit */ |
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#define CREQ_CMP_VALID(hdr, raw_cons, cp_bit) \ |
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(!!((hdr)->v & CREQ_BASE_V) == \ |
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!((raw_cons) & (cp_bit))) |
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#define CREQ_ENTRY_POLL_BUDGET 0x100 |
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/* HWQ */ |
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typedef int (*aeq_handler_t)(struct bnxt_qplib_rcfw *, void *, void *); |
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struct bnxt_qplib_crsqe { |
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struct creq_qp_event *resp; |
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u32 req_size; |
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}; |
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struct bnxt_qplib_rcfw_sbuf { |
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void *sb; |
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dma_addr_t dma_addr; |
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u32 size; |
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}; |
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struct bnxt_qplib_qp_node { |
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u32 qp_id; /* QP id */ |
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void *qp_handle; /* ptr to qplib_qp */ |
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}; |
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#define BNXT_QPLIB_OOS_COUNT_MASK 0xFFFFFFFF |
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#define FIRMWARE_INITIALIZED_FLAG (0) |
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#define FIRMWARE_FIRST_FLAG (31) |
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#define FIRMWARE_TIMED_OUT (3) |
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#define ERR_DEVICE_DETACHED (4) |
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struct bnxt_qplib_cmdq_mbox { |
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struct bnxt_qplib_reg_desc reg; |
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void __iomem *prod; |
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void __iomem *db; |
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}; |
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struct bnxt_qplib_cmdq_ctx { |
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struct bnxt_qplib_hwq hwq; |
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struct bnxt_qplib_cmdq_mbox cmdq_mbox; |
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wait_queue_head_t waitq; |
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unsigned long flags; |
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unsigned long *cmdq_bitmap; |
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u32 bmap_size; |
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u32 seq_num; |
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}; |
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struct bnxt_qplib_creq_db { |
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struct bnxt_qplib_reg_desc reg; |
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struct bnxt_qplib_db_info dbinfo; |
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}; |
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struct bnxt_qplib_creq_stat { |
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u64 creq_qp_event_processed; |
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u64 creq_func_event_processed; |
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}; |
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struct bnxt_qplib_creq_ctx { |
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struct bnxt_qplib_hwq hwq; |
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struct bnxt_qplib_creq_db creq_db; |
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struct bnxt_qplib_creq_stat stats; |
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struct tasklet_struct creq_tasklet; |
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aeq_handler_t aeq_handler; |
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u16 ring_id; |
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int msix_vec; |
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bool requested; /*irq handler installed */ |
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}; |
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/* RCFW Communication Channels */ |
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struct bnxt_qplib_rcfw { |
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struct pci_dev *pdev; |
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struct bnxt_qplib_res *res; |
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struct bnxt_qplib_cmdq_ctx cmdq; |
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struct bnxt_qplib_creq_ctx creq; |
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struct bnxt_qplib_crsqe *crsqe_tbl; |
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int qp_tbl_size; |
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struct bnxt_qplib_qp_node *qp_tbl; |
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u64 oos_prev; |
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u32 init_oos_stats; |
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u32 cmdq_depth; |
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}; |
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void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw); |
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int bnxt_qplib_alloc_rcfw_channel(struct bnxt_qplib_res *res, |
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struct bnxt_qplib_rcfw *rcfw, |
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struct bnxt_qplib_ctx *ctx, |
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int qp_tbl_sz); |
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void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill); |
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void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw); |
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int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector, |
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bool need_init); |
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int bnxt_qplib_enable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw, |
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int msix_vector, |
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int cp_bar_reg_off, int virt_fn, |
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aeq_handler_t aeq_handler); |
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struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf( |
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struct bnxt_qplib_rcfw *rcfw, |
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u32 size); |
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void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw, |
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struct bnxt_qplib_rcfw_sbuf *sbuf); |
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int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw, |
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struct cmdq_base *req, struct creq_base *resp, |
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void *sbuf, u8 is_block); |
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int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw); |
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int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw, |
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struct bnxt_qplib_ctx *ctx, int is_virtfn); |
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void bnxt_qplib_mark_qp_error(void *qp_handle); |
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static inline u32 map_qp_id_to_tbl_indx(u32 qid, struct bnxt_qplib_rcfw *rcfw) |
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{ |
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/* Last index of the qp_tbl is for QP1 ie. qp_tbl_size - 1*/ |
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return (qid == 1) ? rcfw->qp_tbl_size - 1 : qid % rcfw->qp_tbl_size - 2; |
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} |
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#endif /* __BNXT_QPLIB_RCFW_H__ */
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