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378 lines
9.0 KiB
378 lines
9.0 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* TI ADS124S0X chip family driver |
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* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ |
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*/ |
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#include <linux/err.h> |
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#include <linux/delay.h> |
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#include <linux/device.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_gpio.h> |
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#include <linux/slab.h> |
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#include <linux/sysfs.h> |
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#include <linux/gpio/consumer.h> |
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#include <linux/spi/spi.h> |
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#include <linux/iio/iio.h> |
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#include <linux/iio/buffer.h> |
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#include <linux/iio/trigger_consumer.h> |
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#include <linux/iio/triggered_buffer.h> |
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#include <linux/iio/sysfs.h> |
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#include <asm/unaligned.h> |
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/* Commands */ |
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#define ADS124S08_CMD_NOP 0x00 |
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#define ADS124S08_CMD_WAKEUP 0x02 |
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#define ADS124S08_CMD_PWRDWN 0x04 |
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#define ADS124S08_CMD_RESET 0x06 |
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#define ADS124S08_CMD_START 0x08 |
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#define ADS124S08_CMD_STOP 0x0a |
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#define ADS124S08_CMD_SYOCAL 0x16 |
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#define ADS124S08_CMD_SYGCAL 0x17 |
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#define ADS124S08_CMD_SFOCAL 0x19 |
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#define ADS124S08_CMD_RDATA 0x12 |
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#define ADS124S08_CMD_RREG 0x20 |
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#define ADS124S08_CMD_WREG 0x40 |
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/* Registers */ |
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#define ADS124S08_ID_REG 0x00 |
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#define ADS124S08_STATUS 0x01 |
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#define ADS124S08_INPUT_MUX 0x02 |
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#define ADS124S08_PGA 0x03 |
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#define ADS124S08_DATA_RATE 0x04 |
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#define ADS124S08_REF 0x05 |
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#define ADS124S08_IDACMAG 0x06 |
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#define ADS124S08_IDACMUX 0x07 |
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#define ADS124S08_VBIAS 0x08 |
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#define ADS124S08_SYS 0x09 |
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#define ADS124S08_OFCAL0 0x0a |
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#define ADS124S08_OFCAL1 0x0b |
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#define ADS124S08_OFCAL2 0x0c |
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#define ADS124S08_FSCAL0 0x0d |
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#define ADS124S08_FSCAL1 0x0e |
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#define ADS124S08_FSCAL2 0x0f |
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#define ADS124S08_GPIODAT 0x10 |
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#define ADS124S08_GPIOCON 0x11 |
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/* ADS124S0x common channels */ |
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#define ADS124S08_AIN0 0x00 |
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#define ADS124S08_AIN1 0x01 |
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#define ADS124S08_AIN2 0x02 |
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#define ADS124S08_AIN3 0x03 |
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#define ADS124S08_AIN4 0x04 |
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#define ADS124S08_AIN5 0x05 |
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#define ADS124S08_AINCOM 0x0c |
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/* ADS124S08 only channels */ |
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#define ADS124S08_AIN6 0x06 |
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#define ADS124S08_AIN7 0x07 |
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#define ADS124S08_AIN8 0x08 |
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#define ADS124S08_AIN9 0x09 |
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#define ADS124S08_AIN10 0x0a |
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#define ADS124S08_AIN11 0x0b |
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#define ADS124S08_MAX_CHANNELS 12 |
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#define ADS124S08_POS_MUX_SHIFT 0x04 |
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#define ADS124S08_INT_REF 0x09 |
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#define ADS124S08_START_REG_MASK 0x1f |
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#define ADS124S08_NUM_BYTES_MASK 0x1f |
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#define ADS124S08_START_CONV 0x01 |
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#define ADS124S08_STOP_CONV 0x00 |
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enum ads124s_id { |
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ADS124S08_ID, |
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ADS124S06_ID, |
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}; |
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struct ads124s_chip_info { |
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const struct iio_chan_spec *channels; |
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unsigned int num_channels; |
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}; |
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struct ads124s_private { |
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const struct ads124s_chip_info *chip_info; |
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struct gpio_desc *reset_gpio; |
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struct spi_device *spi; |
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struct mutex lock; |
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/* |
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* Used to correctly align data. |
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* Ensure timestamp is naturally aligned. |
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* Note that the full buffer length may not be needed if not |
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* all channels are enabled, as long as the alignment of the |
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* timestamp is maintained. |
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*/ |
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u32 buffer[ADS124S08_MAX_CHANNELS + sizeof(s64)/sizeof(u32)] __aligned(8); |
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u8 data[5] ____cacheline_aligned; |
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}; |
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#define ADS124S08_CHAN(index) \ |
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{ \ |
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.type = IIO_VOLTAGE, \ |
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.indexed = 1, \ |
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.channel = index, \ |
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ |
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.scan_index = index, \ |
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.scan_type = { \ |
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.sign = 'u', \ |
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.realbits = 32, \ |
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.storagebits = 32, \ |
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}, \ |
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} |
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static const struct iio_chan_spec ads124s06_channels[] = { |
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ADS124S08_CHAN(0), |
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ADS124S08_CHAN(1), |
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ADS124S08_CHAN(2), |
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ADS124S08_CHAN(3), |
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ADS124S08_CHAN(4), |
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ADS124S08_CHAN(5), |
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}; |
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static const struct iio_chan_spec ads124s08_channels[] = { |
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ADS124S08_CHAN(0), |
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ADS124S08_CHAN(1), |
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ADS124S08_CHAN(2), |
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ADS124S08_CHAN(3), |
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ADS124S08_CHAN(4), |
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ADS124S08_CHAN(5), |
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ADS124S08_CHAN(6), |
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ADS124S08_CHAN(7), |
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ADS124S08_CHAN(8), |
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ADS124S08_CHAN(9), |
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ADS124S08_CHAN(10), |
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ADS124S08_CHAN(11), |
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}; |
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static const struct ads124s_chip_info ads124s_chip_info_tbl[] = { |
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[ADS124S08_ID] = { |
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.channels = ads124s08_channels, |
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.num_channels = ARRAY_SIZE(ads124s08_channels), |
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}, |
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[ADS124S06_ID] = { |
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.channels = ads124s06_channels, |
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.num_channels = ARRAY_SIZE(ads124s06_channels), |
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}, |
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}; |
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static int ads124s_write_cmd(struct iio_dev *indio_dev, u8 command) |
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{ |
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struct ads124s_private *priv = iio_priv(indio_dev); |
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priv->data[0] = command; |
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return spi_write(priv->spi, &priv->data[0], 1); |
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} |
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static int ads124s_write_reg(struct iio_dev *indio_dev, u8 reg, u8 data) |
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{ |
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struct ads124s_private *priv = iio_priv(indio_dev); |
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priv->data[0] = ADS124S08_CMD_WREG | reg; |
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priv->data[1] = 0x0; |
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priv->data[2] = data; |
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return spi_write(priv->spi, &priv->data[0], 3); |
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} |
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static int ads124s_reset(struct iio_dev *indio_dev) |
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{ |
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struct ads124s_private *priv = iio_priv(indio_dev); |
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if (priv->reset_gpio) { |
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gpiod_set_value(priv->reset_gpio, 0); |
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udelay(200); |
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gpiod_set_value(priv->reset_gpio, 1); |
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} else { |
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return ads124s_write_cmd(indio_dev, ADS124S08_CMD_RESET); |
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} |
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return 0; |
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}; |
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static int ads124s_read(struct iio_dev *indio_dev, unsigned int chan) |
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{ |
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struct ads124s_private *priv = iio_priv(indio_dev); |
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int ret; |
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struct spi_transfer t[] = { |
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{ |
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.tx_buf = &priv->data[0], |
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.len = 4, |
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.cs_change = 1, |
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}, { |
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.tx_buf = &priv->data[1], |
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.rx_buf = &priv->data[1], |
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.len = 4, |
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}, |
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}; |
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priv->data[0] = ADS124S08_CMD_RDATA; |
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memset(&priv->data[1], ADS124S08_CMD_NOP, sizeof(priv->data) - 1); |
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ret = spi_sync_transfer(priv->spi, t, ARRAY_SIZE(t)); |
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if (ret < 0) |
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return ret; |
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return get_unaligned_be24(&priv->data[2]); |
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} |
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static int ads124s_read_raw(struct iio_dev *indio_dev, |
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struct iio_chan_spec const *chan, |
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int *val, int *val2, long m) |
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{ |
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struct ads124s_private *priv = iio_priv(indio_dev); |
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int ret; |
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mutex_lock(&priv->lock); |
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switch (m) { |
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case IIO_CHAN_INFO_RAW: |
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ret = ads124s_write_reg(indio_dev, ADS124S08_INPUT_MUX, |
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chan->channel); |
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if (ret) { |
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dev_err(&priv->spi->dev, "Set ADC CH failed\n"); |
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goto out; |
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} |
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ret = ads124s_write_cmd(indio_dev, ADS124S08_START_CONV); |
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if (ret) { |
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dev_err(&priv->spi->dev, "Start conversions failed\n"); |
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goto out; |
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} |
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ret = ads124s_read(indio_dev, chan->channel); |
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if (ret < 0) { |
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dev_err(&priv->spi->dev, "Read ADC failed\n"); |
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goto out; |
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} |
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*val = ret; |
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ret = ads124s_write_cmd(indio_dev, ADS124S08_STOP_CONV); |
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if (ret) { |
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dev_err(&priv->spi->dev, "Stop conversions failed\n"); |
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goto out; |
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} |
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ret = IIO_VAL_INT; |
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break; |
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default: |
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ret = -EINVAL; |
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break; |
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} |
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out: |
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mutex_unlock(&priv->lock); |
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return ret; |
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} |
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static const struct iio_info ads124s_info = { |
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.read_raw = &ads124s_read_raw, |
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}; |
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static irqreturn_t ads124s_trigger_handler(int irq, void *p) |
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{ |
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struct iio_poll_func *pf = p; |
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struct iio_dev *indio_dev = pf->indio_dev; |
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struct ads124s_private *priv = iio_priv(indio_dev); |
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int scan_index, j = 0; |
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int ret; |
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for_each_set_bit(scan_index, indio_dev->active_scan_mask, |
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indio_dev->masklength) { |
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ret = ads124s_write_reg(indio_dev, ADS124S08_INPUT_MUX, |
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scan_index); |
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if (ret) |
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dev_err(&priv->spi->dev, "Set ADC CH failed\n"); |
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ret = ads124s_write_cmd(indio_dev, ADS124S08_START_CONV); |
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if (ret) |
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dev_err(&priv->spi->dev, "Start ADC conversions failed\n"); |
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priv->buffer[j] = ads124s_read(indio_dev, scan_index); |
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ret = ads124s_write_cmd(indio_dev, ADS124S08_STOP_CONV); |
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if (ret) |
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dev_err(&priv->spi->dev, "Stop ADC conversions failed\n"); |
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j++; |
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} |
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iio_push_to_buffers_with_timestamp(indio_dev, priv->buffer, |
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pf->timestamp); |
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iio_trigger_notify_done(indio_dev->trig); |
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return IRQ_HANDLED; |
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} |
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static int ads124s_probe(struct spi_device *spi) |
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{ |
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struct ads124s_private *ads124s_priv; |
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struct iio_dev *indio_dev; |
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const struct spi_device_id *spi_id = spi_get_device_id(spi); |
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int ret; |
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indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*ads124s_priv)); |
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if (indio_dev == NULL) |
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return -ENOMEM; |
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ads124s_priv = iio_priv(indio_dev); |
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ads124s_priv->reset_gpio = devm_gpiod_get_optional(&spi->dev, |
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"reset", GPIOD_OUT_LOW); |
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if (IS_ERR(ads124s_priv->reset_gpio)) |
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dev_info(&spi->dev, "Reset GPIO not defined\n"); |
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ads124s_priv->chip_info = &ads124s_chip_info_tbl[spi_id->driver_data]; |
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ads124s_priv->spi = spi; |
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indio_dev->name = spi_id->name; |
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indio_dev->modes = INDIO_DIRECT_MODE; |
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indio_dev->channels = ads124s_priv->chip_info->channels; |
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indio_dev->num_channels = ads124s_priv->chip_info->num_channels; |
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indio_dev->info = &ads124s_info; |
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mutex_init(&ads124s_priv->lock); |
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ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL, |
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ads124s_trigger_handler, NULL); |
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if (ret) { |
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dev_err(&spi->dev, "iio triggered buffer setup failed\n"); |
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return ret; |
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} |
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ads124s_reset(indio_dev); |
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return devm_iio_device_register(&spi->dev, indio_dev); |
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} |
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static const struct spi_device_id ads124s_id[] = { |
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{ "ads124s06", ADS124S06_ID }, |
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{ "ads124s08", ADS124S08_ID }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(spi, ads124s_id); |
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static const struct of_device_id ads124s_of_table[] = { |
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{ .compatible = "ti,ads124s06" }, |
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{ .compatible = "ti,ads124s08" }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, ads124s_of_table); |
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static struct spi_driver ads124s_driver = { |
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.driver = { |
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.name = "ads124s08", |
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.of_match_table = ads124s_of_table, |
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}, |
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.probe = ads124s_probe, |
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.id_table = ads124s_id, |
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}; |
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module_spi_driver(ads124s_driver); |
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MODULE_AUTHOR("Dan Murphy <[email protected]>"); |
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MODULE_DESCRIPTION("TI TI_ADS12S0X ADC"); |
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MODULE_LICENSE("GPL v2");
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