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601 lines
16 KiB
601 lines
16 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 2016, 2017 Cavium Inc. |
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*/ |
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|
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#include <linux/bitops.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/spinlock.h> |
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#include <asm-generic/msi.h> |
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#define GPIO_RX_DAT 0x0 |
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#define GPIO_TX_SET 0x8 |
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#define GPIO_TX_CLR 0x10 |
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#define GPIO_CONST 0x90 |
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#define GPIO_CONST_GPIOS_MASK 0xff |
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#define GPIO_BIT_CFG 0x400 |
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#define GPIO_BIT_CFG_TX_OE BIT(0) |
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#define GPIO_BIT_CFG_PIN_XOR BIT(1) |
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#define GPIO_BIT_CFG_INT_EN BIT(2) |
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#define GPIO_BIT_CFG_INT_TYPE BIT(3) |
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#define GPIO_BIT_CFG_FIL_MASK GENMASK(11, 4) |
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#define GPIO_BIT_CFG_FIL_CNT_SHIFT 4 |
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#define GPIO_BIT_CFG_FIL_SEL_SHIFT 8 |
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#define GPIO_BIT_CFG_TX_OD BIT(12) |
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#define GPIO_BIT_CFG_PIN_SEL_MASK GENMASK(25, 16) |
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#define GPIO_INTR 0x800 |
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#define GPIO_INTR_INTR BIT(0) |
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#define GPIO_INTR_INTR_W1S BIT(1) |
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#define GPIO_INTR_ENA_W1C BIT(2) |
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#define GPIO_INTR_ENA_W1S BIT(3) |
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#define GPIO_2ND_BANK 0x1400 |
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#define GLITCH_FILTER_400NS ((4u << GPIO_BIT_CFG_FIL_SEL_SHIFT) | \ |
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(9u << GPIO_BIT_CFG_FIL_CNT_SHIFT)) |
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struct thunderx_gpio; |
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struct thunderx_line { |
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struct thunderx_gpio *txgpio; |
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unsigned int line; |
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unsigned int fil_bits; |
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}; |
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struct thunderx_gpio { |
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struct gpio_chip chip; |
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u8 __iomem *register_base; |
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struct msix_entry *msix_entries; /* per line MSI-X */ |
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struct thunderx_line *line_entries; /* per line irq info */ |
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raw_spinlock_t lock; |
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unsigned long invert_mask[2]; |
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unsigned long od_mask[2]; |
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int base_msi; |
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}; |
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static unsigned int bit_cfg_reg(unsigned int line) |
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{ |
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return 8 * line + GPIO_BIT_CFG; |
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} |
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static unsigned int intr_reg(unsigned int line) |
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{ |
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return 8 * line + GPIO_INTR; |
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} |
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static bool thunderx_gpio_is_gpio_nowarn(struct thunderx_gpio *txgpio, |
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unsigned int line) |
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{ |
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u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line)); |
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return (bit_cfg & GPIO_BIT_CFG_PIN_SEL_MASK) == 0; |
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} |
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/* |
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* Check (and WARN) that the pin is available for GPIO. We will not |
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* allow modification of the state of non-GPIO pins from this driver. |
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*/ |
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static bool thunderx_gpio_is_gpio(struct thunderx_gpio *txgpio, |
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unsigned int line) |
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{ |
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bool rv = thunderx_gpio_is_gpio_nowarn(txgpio, line); |
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WARN_RATELIMIT(!rv, "Pin %d not available for GPIO\n", line); |
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return rv; |
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} |
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static int thunderx_gpio_request(struct gpio_chip *chip, unsigned int line) |
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{ |
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struct thunderx_gpio *txgpio = gpiochip_get_data(chip); |
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return thunderx_gpio_is_gpio(txgpio, line) ? 0 : -EIO; |
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} |
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static int thunderx_gpio_dir_in(struct gpio_chip *chip, unsigned int line) |
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{ |
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struct thunderx_gpio *txgpio = gpiochip_get_data(chip); |
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if (!thunderx_gpio_is_gpio(txgpio, line)) |
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return -EIO; |
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raw_spin_lock(&txgpio->lock); |
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clear_bit(line, txgpio->invert_mask); |
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clear_bit(line, txgpio->od_mask); |
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writeq(txgpio->line_entries[line].fil_bits, |
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txgpio->register_base + bit_cfg_reg(line)); |
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raw_spin_unlock(&txgpio->lock); |
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return 0; |
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} |
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static void thunderx_gpio_set(struct gpio_chip *chip, unsigned int line, |
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int value) |
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{ |
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struct thunderx_gpio *txgpio = gpiochip_get_data(chip); |
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int bank = line / 64; |
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int bank_bit = line % 64; |
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void __iomem *reg = txgpio->register_base + |
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(bank * GPIO_2ND_BANK) + (value ? GPIO_TX_SET : GPIO_TX_CLR); |
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writeq(BIT_ULL(bank_bit), reg); |
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} |
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static int thunderx_gpio_dir_out(struct gpio_chip *chip, unsigned int line, |
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int value) |
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{ |
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struct thunderx_gpio *txgpio = gpiochip_get_data(chip); |
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u64 bit_cfg = txgpio->line_entries[line].fil_bits | GPIO_BIT_CFG_TX_OE; |
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if (!thunderx_gpio_is_gpio(txgpio, line)) |
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return -EIO; |
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raw_spin_lock(&txgpio->lock); |
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thunderx_gpio_set(chip, line, value); |
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if (test_bit(line, txgpio->invert_mask)) |
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bit_cfg |= GPIO_BIT_CFG_PIN_XOR; |
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if (test_bit(line, txgpio->od_mask)) |
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bit_cfg |= GPIO_BIT_CFG_TX_OD; |
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writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line)); |
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raw_spin_unlock(&txgpio->lock); |
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return 0; |
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} |
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static int thunderx_gpio_get_direction(struct gpio_chip *chip, unsigned int line) |
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{ |
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struct thunderx_gpio *txgpio = gpiochip_get_data(chip); |
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u64 bit_cfg; |
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if (!thunderx_gpio_is_gpio_nowarn(txgpio, line)) |
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/* |
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* Say it is input for now to avoid WARNing on |
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* gpiochip_add_data(). We will WARN if someone |
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* requests it or tries to use it. |
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*/ |
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return 1; |
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bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line)); |
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if (bit_cfg & GPIO_BIT_CFG_TX_OE) |
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return GPIO_LINE_DIRECTION_OUT; |
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return GPIO_LINE_DIRECTION_IN; |
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} |
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static int thunderx_gpio_set_config(struct gpio_chip *chip, |
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unsigned int line, |
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unsigned long cfg) |
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{ |
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bool orig_invert, orig_od, orig_dat, new_invert, new_od; |
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u32 arg, sel; |
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u64 bit_cfg; |
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int bank = line / 64; |
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int bank_bit = line % 64; |
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int ret = -ENOTSUPP; |
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struct thunderx_gpio *txgpio = gpiochip_get_data(chip); |
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void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET; |
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if (!thunderx_gpio_is_gpio(txgpio, line)) |
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return -EIO; |
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raw_spin_lock(&txgpio->lock); |
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orig_invert = test_bit(line, txgpio->invert_mask); |
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new_invert = orig_invert; |
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orig_od = test_bit(line, txgpio->od_mask); |
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new_od = orig_od; |
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orig_dat = ((readq(reg) >> bank_bit) & 1) ^ orig_invert; |
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bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line)); |
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switch (pinconf_to_config_param(cfg)) { |
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case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
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/* |
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* Weird, setting open-drain mode causes signal |
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* inversion. Note this so we can compensate in the |
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* dir_out function. |
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*/ |
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set_bit(line, txgpio->invert_mask); |
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new_invert = true; |
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set_bit(line, txgpio->od_mask); |
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new_od = true; |
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ret = 0; |
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break; |
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case PIN_CONFIG_DRIVE_PUSH_PULL: |
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clear_bit(line, txgpio->invert_mask); |
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new_invert = false; |
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clear_bit(line, txgpio->od_mask); |
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new_od = false; |
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ret = 0; |
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break; |
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case PIN_CONFIG_INPUT_DEBOUNCE: |
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arg = pinconf_to_config_argument(cfg); |
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if (arg > 1228) { /* 15 * 2^15 * 2.5nS maximum */ |
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ret = -EINVAL; |
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break; |
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} |
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arg *= 400; /* scale to 2.5nS clocks. */ |
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sel = 0; |
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while (arg > 15) { |
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sel++; |
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arg++; /* always round up */ |
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arg >>= 1; |
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} |
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txgpio->line_entries[line].fil_bits = |
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(sel << GPIO_BIT_CFG_FIL_SEL_SHIFT) | |
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(arg << GPIO_BIT_CFG_FIL_CNT_SHIFT); |
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bit_cfg &= ~GPIO_BIT_CFG_FIL_MASK; |
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bit_cfg |= txgpio->line_entries[line].fil_bits; |
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writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line)); |
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ret = 0; |
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break; |
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default: |
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break; |
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} |
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raw_spin_unlock(&txgpio->lock); |
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/* |
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* If currently output and OPEN_DRAIN changed, install the new |
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* settings |
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*/ |
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if ((new_invert != orig_invert || new_od != orig_od) && |
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(bit_cfg & GPIO_BIT_CFG_TX_OE)) |
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ret = thunderx_gpio_dir_out(chip, line, orig_dat ^ new_invert); |
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return ret; |
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} |
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static int thunderx_gpio_get(struct gpio_chip *chip, unsigned int line) |
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{ |
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struct thunderx_gpio *txgpio = gpiochip_get_data(chip); |
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int bank = line / 64; |
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int bank_bit = line % 64; |
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u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT); |
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u64 masked_bits = read_bits & BIT_ULL(bank_bit); |
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if (test_bit(line, txgpio->invert_mask)) |
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return masked_bits == 0; |
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else |
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return masked_bits != 0; |
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} |
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static void thunderx_gpio_set_multiple(struct gpio_chip *chip, |
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unsigned long *mask, |
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unsigned long *bits) |
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{ |
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int bank; |
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u64 set_bits, clear_bits; |
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struct thunderx_gpio *txgpio = gpiochip_get_data(chip); |
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for (bank = 0; bank <= chip->ngpio / 64; bank++) { |
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set_bits = bits[bank] & mask[bank]; |
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clear_bits = ~bits[bank] & mask[bank]; |
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writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET); |
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writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR); |
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} |
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} |
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static void thunderx_gpio_irq_ack(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct thunderx_gpio *txgpio = gpiochip_get_data(gc); |
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writeq(GPIO_INTR_INTR, |
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txgpio->register_base + intr_reg(irqd_to_hwirq(d))); |
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} |
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static void thunderx_gpio_irq_mask(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct thunderx_gpio *txgpio = gpiochip_get_data(gc); |
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writeq(GPIO_INTR_ENA_W1C, |
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txgpio->register_base + intr_reg(irqd_to_hwirq(d))); |
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} |
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static void thunderx_gpio_irq_mask_ack(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct thunderx_gpio *txgpio = gpiochip_get_data(gc); |
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writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR, |
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txgpio->register_base + intr_reg(irqd_to_hwirq(d))); |
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} |
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static void thunderx_gpio_irq_unmask(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct thunderx_gpio *txgpio = gpiochip_get_data(gc); |
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writeq(GPIO_INTR_ENA_W1S, |
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txgpio->register_base + intr_reg(irqd_to_hwirq(d))); |
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} |
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static int thunderx_gpio_irq_set_type(struct irq_data *d, |
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unsigned int flow_type) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct thunderx_gpio *txgpio = gpiochip_get_data(gc); |
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struct thunderx_line *txline = |
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&txgpio->line_entries[irqd_to_hwirq(d)]; |
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u64 bit_cfg; |
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irqd_set_trigger_type(d, flow_type); |
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bit_cfg = txline->fil_bits | GPIO_BIT_CFG_INT_EN; |
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if (flow_type & IRQ_TYPE_EDGE_BOTH) { |
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irq_set_handler_locked(d, handle_fasteoi_ack_irq); |
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bit_cfg |= GPIO_BIT_CFG_INT_TYPE; |
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} else { |
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irq_set_handler_locked(d, handle_fasteoi_mask_irq); |
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} |
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raw_spin_lock(&txgpio->lock); |
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if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)) { |
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bit_cfg |= GPIO_BIT_CFG_PIN_XOR; |
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set_bit(txline->line, txgpio->invert_mask); |
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} else { |
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clear_bit(txline->line, txgpio->invert_mask); |
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} |
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clear_bit(txline->line, txgpio->od_mask); |
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writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line)); |
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raw_spin_unlock(&txgpio->lock); |
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return IRQ_SET_MASK_OK; |
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} |
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static void thunderx_gpio_irq_enable(struct irq_data *data) |
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{ |
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irq_chip_enable_parent(data); |
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thunderx_gpio_irq_unmask(data); |
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} |
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static void thunderx_gpio_irq_disable(struct irq_data *data) |
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{ |
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thunderx_gpio_irq_mask(data); |
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irq_chip_disable_parent(data); |
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} |
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/* |
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* Interrupts are chained from underlying MSI-X vectors. We have |
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* these irq_chip functions to be able to handle level triggering |
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* semantics and other acknowledgment tasks associated with the GPIO |
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* mechanism. |
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*/ |
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static struct irq_chip thunderx_gpio_irq_chip = { |
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.name = "GPIO", |
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.irq_enable = thunderx_gpio_irq_enable, |
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.irq_disable = thunderx_gpio_irq_disable, |
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.irq_ack = thunderx_gpio_irq_ack, |
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.irq_mask = thunderx_gpio_irq_mask, |
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.irq_mask_ack = thunderx_gpio_irq_mask_ack, |
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.irq_unmask = thunderx_gpio_irq_unmask, |
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.irq_eoi = irq_chip_eoi_parent, |
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.irq_set_affinity = irq_chip_set_affinity_parent, |
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.irq_set_type = thunderx_gpio_irq_set_type, |
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.flags = IRQCHIP_SET_TYPE_MASKED |
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}; |
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static int thunderx_gpio_child_to_parent_hwirq(struct gpio_chip *gc, |
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unsigned int child, |
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unsigned int child_type, |
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unsigned int *parent, |
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unsigned int *parent_type) |
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{ |
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struct thunderx_gpio *txgpio = gpiochip_get_data(gc); |
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struct irq_data *irqd; |
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unsigned int irq; |
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irq = txgpio->msix_entries[child].vector; |
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irqd = irq_domain_get_irq_data(gc->irq.parent_domain, irq); |
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if (!irqd) |
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return -EINVAL; |
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*parent = irqd_to_hwirq(irqd); |
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*parent_type = IRQ_TYPE_LEVEL_HIGH; |
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return 0; |
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} |
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static void *thunderx_gpio_populate_parent_alloc_info(struct gpio_chip *chip, |
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unsigned int parent_hwirq, |
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unsigned int parent_type) |
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{ |
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msi_alloc_info_t *info; |
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info = kmalloc(sizeof(*info), GFP_KERNEL); |
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if (!info) |
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return NULL; |
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info->hwirq = parent_hwirq; |
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return info; |
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} |
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static int thunderx_gpio_probe(struct pci_dev *pdev, |
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const struct pci_device_id *id) |
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{ |
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void __iomem * const *tbl; |
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struct device *dev = &pdev->dev; |
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struct thunderx_gpio *txgpio; |
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struct gpio_chip *chip; |
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struct gpio_irq_chip *girq; |
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int ngpio, i; |
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int err = 0; |
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txgpio = devm_kzalloc(dev, sizeof(*txgpio), GFP_KERNEL); |
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if (!txgpio) |
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return -ENOMEM; |
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raw_spin_lock_init(&txgpio->lock); |
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chip = &txgpio->chip; |
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pci_set_drvdata(pdev, txgpio); |
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err = pcim_enable_device(pdev); |
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if (err) { |
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dev_err(dev, "Failed to enable PCI device: err %d\n", err); |
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goto out; |
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} |
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err = pcim_iomap_regions(pdev, 1 << 0, KBUILD_MODNAME); |
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if (err) { |
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dev_err(dev, "Failed to iomap PCI device: err %d\n", err); |
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goto out; |
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} |
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tbl = pcim_iomap_table(pdev); |
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txgpio->register_base = tbl[0]; |
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if (!txgpio->register_base) { |
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dev_err(dev, "Cannot map PCI resource\n"); |
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err = -ENOMEM; |
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goto out; |
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} |
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if (pdev->subsystem_device == 0xa10a) { |
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/* CN88XX has no GPIO_CONST register*/ |
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ngpio = 50; |
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txgpio->base_msi = 48; |
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} else { |
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u64 c = readq(txgpio->register_base + GPIO_CONST); |
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ngpio = c & GPIO_CONST_GPIOS_MASK; |
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txgpio->base_msi = (c >> 8) & 0xff; |
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} |
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txgpio->msix_entries = devm_kcalloc(dev, |
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ngpio, sizeof(struct msix_entry), |
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GFP_KERNEL); |
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if (!txgpio->msix_entries) { |
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err = -ENOMEM; |
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goto out; |
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} |
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txgpio->line_entries = devm_kcalloc(dev, |
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ngpio, |
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sizeof(struct thunderx_line), |
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GFP_KERNEL); |
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if (!txgpio->line_entries) { |
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err = -ENOMEM; |
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goto out; |
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} |
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for (i = 0; i < ngpio; i++) { |
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u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(i)); |
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txgpio->msix_entries[i].entry = txgpio->base_msi + (2 * i); |
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txgpio->line_entries[i].line = i; |
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txgpio->line_entries[i].txgpio = txgpio; |
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/* |
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* If something has already programmed the pin, use |
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* the existing glitch filter settings, otherwise go |
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* to 400nS. |
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*/ |
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txgpio->line_entries[i].fil_bits = bit_cfg ? |
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(bit_cfg & GPIO_BIT_CFG_FIL_MASK) : GLITCH_FILTER_400NS; |
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if ((bit_cfg & GPIO_BIT_CFG_TX_OE) && (bit_cfg & GPIO_BIT_CFG_TX_OD)) |
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set_bit(i, txgpio->od_mask); |
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if (bit_cfg & GPIO_BIT_CFG_PIN_XOR) |
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set_bit(i, txgpio->invert_mask); |
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} |
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/* Enable all MSI-X for interrupts on all possible lines. */ |
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err = pci_enable_msix_range(pdev, txgpio->msix_entries, ngpio, ngpio); |
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if (err < 0) |
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goto out; |
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chip->label = KBUILD_MODNAME; |
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chip->parent = dev; |
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chip->owner = THIS_MODULE; |
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chip->request = thunderx_gpio_request; |
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chip->base = -1; /* System allocated */ |
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chip->can_sleep = false; |
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chip->ngpio = ngpio; |
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chip->get_direction = thunderx_gpio_get_direction; |
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chip->direction_input = thunderx_gpio_dir_in; |
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chip->get = thunderx_gpio_get; |
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chip->direction_output = thunderx_gpio_dir_out; |
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chip->set = thunderx_gpio_set; |
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chip->set_multiple = thunderx_gpio_set_multiple; |
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chip->set_config = thunderx_gpio_set_config; |
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girq = &chip->irq; |
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girq->chip = &thunderx_gpio_irq_chip; |
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girq->fwnode = of_node_to_fwnode(dev->of_node); |
|
girq->parent_domain = |
|
irq_get_irq_data(txgpio->msix_entries[0].vector)->domain; |
|
girq->child_to_parent_hwirq = thunderx_gpio_child_to_parent_hwirq; |
|
girq->populate_parent_alloc_arg = thunderx_gpio_populate_parent_alloc_info; |
|
girq->handler = handle_bad_irq; |
|
girq->default_type = IRQ_TYPE_NONE; |
|
|
|
err = devm_gpiochip_add_data(dev, chip, txgpio); |
|
if (err) |
|
goto out; |
|
|
|
/* Push on irq_data and the domain for each line. */ |
|
for (i = 0; i < ngpio; i++) { |
|
struct irq_fwspec fwspec; |
|
|
|
fwspec.fwnode = of_node_to_fwnode(dev->of_node); |
|
fwspec.param_count = 2; |
|
fwspec.param[0] = i; |
|
fwspec.param[1] = IRQ_TYPE_NONE; |
|
err = irq_domain_push_irq(girq->domain, |
|
txgpio->msix_entries[i].vector, |
|
&fwspec); |
|
if (err < 0) |
|
dev_err(dev, "irq_domain_push_irq: %d\n", err); |
|
} |
|
|
|
dev_info(dev, "ThunderX GPIO: %d lines with base %d.\n", |
|
ngpio, chip->base); |
|
return 0; |
|
out: |
|
pci_set_drvdata(pdev, NULL); |
|
return err; |
|
} |
|
|
|
static void thunderx_gpio_remove(struct pci_dev *pdev) |
|
{ |
|
int i; |
|
struct thunderx_gpio *txgpio = pci_get_drvdata(pdev); |
|
|
|
for (i = 0; i < txgpio->chip.ngpio; i++) |
|
irq_domain_pop_irq(txgpio->chip.irq.domain, |
|
txgpio->msix_entries[i].vector); |
|
|
|
irq_domain_remove(txgpio->chip.irq.domain); |
|
|
|
pci_set_drvdata(pdev, NULL); |
|
} |
|
|
|
static const struct pci_device_id thunderx_gpio_id_table[] = { |
|
{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xA00A) }, |
|
{ 0, } /* end of table */ |
|
}; |
|
|
|
MODULE_DEVICE_TABLE(pci, thunderx_gpio_id_table); |
|
|
|
static struct pci_driver thunderx_gpio_driver = { |
|
.name = KBUILD_MODNAME, |
|
.id_table = thunderx_gpio_id_table, |
|
.probe = thunderx_gpio_probe, |
|
.remove = thunderx_gpio_remove, |
|
}; |
|
|
|
module_pci_driver(thunderx_gpio_driver); |
|
|
|
MODULE_DESCRIPTION("Cavium Inc. ThunderX/OCTEON-TX GPIO Driver"); |
|
MODULE_LICENSE("GPL");
|
|
|