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245 lines
5.4 KiB
245 lines
5.4 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* GPIO interface for Intel Sodaville SoCs. |
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* |
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* Copyright (c) 2010, 2011 Intel Corporation |
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* |
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* Author: Hans J. Koch <[email protected]> |
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*/ |
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#include <linux/errno.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/kernel.h> |
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#include <linux/of_irq.h> |
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#include <linux/pci.h> |
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#include <linux/platform_device.h> |
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#define DRV_NAME "sdv_gpio" |
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#define SDV_NUM_PUB_GPIOS 12 |
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#define PCI_DEVICE_ID_SDV_GPIO 0x2e67 |
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#define GPIO_BAR 0 |
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#define GPOUTR 0x00 |
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#define GPOER 0x04 |
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#define GPINR 0x08 |
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#define GPSTR 0x0c |
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#define GPIT1R0 0x10 |
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#define GPIO_INT 0x14 |
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#define GPIT1R1 0x18 |
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#define GPMUXCTL 0x1c |
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struct sdv_gpio_chip_data { |
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int irq_base; |
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void __iomem *gpio_pub_base; |
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struct irq_domain *id; |
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struct irq_chip_generic *gc; |
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struct gpio_chip chip; |
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}; |
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static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct sdv_gpio_chip_data *sd = gc->private; |
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void __iomem *type_reg; |
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u32 reg; |
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if (d->hwirq < 8) |
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type_reg = sd->gpio_pub_base + GPIT1R0; |
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else |
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type_reg = sd->gpio_pub_base + GPIT1R1; |
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reg = readl(type_reg); |
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switch (type) { |
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case IRQ_TYPE_LEVEL_HIGH: |
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reg &= ~BIT(4 * (d->hwirq % 8)); |
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break; |
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case IRQ_TYPE_LEVEL_LOW: |
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reg |= BIT(4 * (d->hwirq % 8)); |
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break; |
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default: |
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return -EINVAL; |
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} |
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writel(reg, type_reg); |
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return 0; |
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} |
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static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data) |
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{ |
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struct sdv_gpio_chip_data *sd = data; |
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unsigned long irq_stat = readl(sd->gpio_pub_base + GPSTR); |
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int irq_bit; |
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irq_stat &= readl(sd->gpio_pub_base + GPIO_INT); |
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if (!irq_stat) |
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return IRQ_NONE; |
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for_each_set_bit(irq_bit, &irq_stat, 32) |
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generic_handle_irq(irq_find_mapping(sd->id, irq_bit)); |
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return IRQ_HANDLED; |
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} |
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static int sdv_xlate(struct irq_domain *h, struct device_node *node, |
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const u32 *intspec, u32 intsize, irq_hw_number_t *out_hwirq, |
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u32 *out_type) |
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{ |
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u32 line, type; |
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if (node != irq_domain_get_of_node(h)) |
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return -EINVAL; |
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if (intsize < 2) |
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return -EINVAL; |
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line = *intspec; |
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*out_hwirq = line; |
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intspec++; |
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type = *intspec; |
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switch (type) { |
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case IRQ_TYPE_LEVEL_LOW: |
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case IRQ_TYPE_LEVEL_HIGH: |
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*out_type = type; |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static const struct irq_domain_ops irq_domain_sdv_ops = { |
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.xlate = sdv_xlate, |
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}; |
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static int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd, |
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struct pci_dev *pdev) |
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{ |
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struct irq_chip_type *ct; |
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int ret; |
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sd->irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, |
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SDV_NUM_PUB_GPIOS, -1); |
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if (sd->irq_base < 0) |
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return sd->irq_base; |
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/* mask + ACK all interrupt sources */ |
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writel(0, sd->gpio_pub_base + GPIO_INT); |
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writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR); |
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ret = devm_request_irq(&pdev->dev, pdev->irq, |
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sdv_gpio_pub_irq_handler, IRQF_SHARED, |
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"sdv_gpio", sd); |
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if (ret) |
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return ret; |
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/* |
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* This gpio irq controller latches level irqs. Testing shows that if |
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* we unmask & ACK the IRQ before the source of the interrupt is gone |
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* then the interrupt is active again. |
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*/ |
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sd->gc = devm_irq_alloc_generic_chip(&pdev->dev, "sdv-gpio", 1, |
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sd->irq_base, |
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sd->gpio_pub_base, |
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handle_fasteoi_irq); |
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if (!sd->gc) |
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return -ENOMEM; |
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sd->gc->private = sd; |
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ct = sd->gc->chip_types; |
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ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; |
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ct->regs.eoi = GPSTR; |
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ct->regs.mask = GPIO_INT; |
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ct->chip.irq_mask = irq_gc_mask_clr_bit; |
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ct->chip.irq_unmask = irq_gc_mask_set_bit; |
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ct->chip.irq_eoi = irq_gc_eoi; |
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ct->chip.irq_set_type = sdv_gpio_pub_set_type; |
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irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS), |
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IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, |
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IRQ_LEVEL | IRQ_NOPROBE); |
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sd->id = irq_domain_add_legacy(pdev->dev.of_node, SDV_NUM_PUB_GPIOS, |
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sd->irq_base, 0, &irq_domain_sdv_ops, sd); |
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if (!sd->id) |
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return -ENODEV; |
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return 0; |
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} |
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static int sdv_gpio_probe(struct pci_dev *pdev, |
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const struct pci_device_id *pci_id) |
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{ |
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struct sdv_gpio_chip_data *sd; |
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int ret; |
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u32 mux_val; |
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sd = devm_kzalloc(&pdev->dev, sizeof(*sd), GFP_KERNEL); |
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if (!sd) |
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return -ENOMEM; |
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ret = pcim_enable_device(pdev); |
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if (ret) { |
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dev_err(&pdev->dev, "can't enable device.\n"); |
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return ret; |
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} |
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ret = pcim_iomap_regions(pdev, 1 << GPIO_BAR, DRV_NAME); |
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if (ret) { |
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dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR); |
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return ret; |
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} |
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sd->gpio_pub_base = pcim_iomap_table(pdev)[GPIO_BAR]; |
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ret = of_property_read_u32(pdev->dev.of_node, "intel,muxctl", &mux_val); |
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if (!ret) |
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writel(mux_val, sd->gpio_pub_base + GPMUXCTL); |
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ret = bgpio_init(&sd->chip, &pdev->dev, 4, |
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sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR, |
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NULL, sd->gpio_pub_base + GPOER, NULL, 0); |
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if (ret) |
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return ret; |
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sd->chip.ngpio = SDV_NUM_PUB_GPIOS; |
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ret = devm_gpiochip_add_data(&pdev->dev, &sd->chip, sd); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "gpiochip_add() failed.\n"); |
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return ret; |
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} |
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ret = sdv_register_irqsupport(sd, pdev); |
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if (ret) |
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return ret; |
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pci_set_drvdata(pdev, sd); |
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dev_info(&pdev->dev, "Sodaville GPIO driver registered.\n"); |
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return 0; |
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} |
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static const struct pci_device_id sdv_gpio_pci_ids[] = { |
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SDV_GPIO) }, |
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{ 0, }, |
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}; |
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static struct pci_driver sdv_gpio_driver = { |
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.driver = { |
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.suppress_bind_attrs = true, |
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}, |
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.name = DRV_NAME, |
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.id_table = sdv_gpio_pci_ids, |
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.probe = sdv_gpio_probe, |
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}; |
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builtin_pci_driver(sdv_gpio_driver);
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