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323 lines
9.2 KiB
323 lines
9.2 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* Copyright (c) 2020 HiSilicon Limited. */ |
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#include <linux/gpio/driver.h> |
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#include <linux/module.h> |
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#include <linux/mod_devicetable.h> |
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#include <linux/platform_device.h> |
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#include <linux/property.h> |
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#define HISI_GPIO_SWPORT_DR_SET_WX 0x000 |
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#define HISI_GPIO_SWPORT_DR_CLR_WX 0x004 |
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#define HISI_GPIO_SWPORT_DDR_SET_WX 0x010 |
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#define HISI_GPIO_SWPORT_DDR_CLR_WX 0x014 |
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#define HISI_GPIO_SWPORT_DDR_ST_WX 0x018 |
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#define HISI_GPIO_INTEN_SET_WX 0x020 |
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#define HISI_GPIO_INTEN_CLR_WX 0x024 |
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#define HISI_GPIO_INTMASK_SET_WX 0x030 |
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#define HISI_GPIO_INTMASK_CLR_WX 0x034 |
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#define HISI_GPIO_INTTYPE_EDGE_SET_WX 0x040 |
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#define HISI_GPIO_INTTYPE_EDGE_CLR_WX 0x044 |
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#define HISI_GPIO_INT_POLARITY_SET_WX 0x050 |
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#define HISI_GPIO_INT_POLARITY_CLR_WX 0x054 |
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#define HISI_GPIO_DEBOUNCE_SET_WX 0x060 |
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#define HISI_GPIO_DEBOUNCE_CLR_WX 0x064 |
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#define HISI_GPIO_INTSTATUS_WX 0x070 |
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#define HISI_GPIO_PORTA_EOI_WX 0x078 |
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#define HISI_GPIO_EXT_PORT_WX 0x080 |
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#define HISI_GPIO_INTCOMB_MASK_WX 0x0a0 |
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#define HISI_GPIO_INT_DEDGE_SET 0x0b0 |
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#define HISI_GPIO_INT_DEDGE_CLR 0x0b4 |
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#define HISI_GPIO_INT_DEDGE_ST 0x0b8 |
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#define HISI_GPIO_LINE_NUM_MAX 32 |
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#define HISI_GPIO_DRIVER_NAME "gpio-hisi" |
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struct hisi_gpio { |
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struct gpio_chip chip; |
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struct device *dev; |
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void __iomem *reg_base; |
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unsigned int line_num; |
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struct irq_chip irq_chip; |
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int irq; |
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}; |
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static inline u32 hisi_gpio_read_reg(struct gpio_chip *chip, |
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unsigned int off) |
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{ |
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struct hisi_gpio *hisi_gpio = |
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container_of(chip, struct hisi_gpio, chip); |
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void __iomem *reg = hisi_gpio->reg_base + off; |
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return readl(reg); |
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} |
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static inline void hisi_gpio_write_reg(struct gpio_chip *chip, |
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unsigned int off, u32 val) |
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{ |
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struct hisi_gpio *hisi_gpio = |
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container_of(chip, struct hisi_gpio, chip); |
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void __iomem *reg = hisi_gpio->reg_base + off; |
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writel(val, reg); |
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} |
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static void hisi_gpio_set_debounce(struct gpio_chip *chip, unsigned int off, |
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u32 debounce) |
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{ |
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if (debounce) |
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hisi_gpio_write_reg(chip, HISI_GPIO_DEBOUNCE_SET_WX, BIT(off)); |
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else |
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hisi_gpio_write_reg(chip, HISI_GPIO_DEBOUNCE_CLR_WX, BIT(off)); |
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} |
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static int hisi_gpio_set_config(struct gpio_chip *chip, unsigned int offset, |
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unsigned long config) |
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{ |
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u32 config_para = pinconf_to_config_param(config); |
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u32 config_arg; |
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switch (config_para) { |
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case PIN_CONFIG_INPUT_DEBOUNCE: |
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config_arg = pinconf_to_config_argument(config); |
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hisi_gpio_set_debounce(chip, offset, config_arg); |
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break; |
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default: |
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return -ENOTSUPP; |
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} |
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return 0; |
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} |
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static void hisi_gpio_set_ack(struct irq_data *d) |
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{ |
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struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
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hisi_gpio_write_reg(chip, HISI_GPIO_PORTA_EOI_WX, BIT(irqd_to_hwirq(d))); |
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} |
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static void hisi_gpio_irq_set_mask(struct irq_data *d) |
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{ |
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struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
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hisi_gpio_write_reg(chip, HISI_GPIO_INTMASK_SET_WX, BIT(irqd_to_hwirq(d))); |
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} |
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static void hisi_gpio_irq_clr_mask(struct irq_data *d) |
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{ |
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struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
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hisi_gpio_write_reg(chip, HISI_GPIO_INTMASK_CLR_WX, BIT(irqd_to_hwirq(d))); |
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} |
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static int hisi_gpio_irq_set_type(struct irq_data *d, u32 type) |
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{ |
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struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
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unsigned int mask = BIT(irqd_to_hwirq(d)); |
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switch (type) { |
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case IRQ_TYPE_EDGE_BOTH: |
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hisi_gpio_write_reg(chip, HISI_GPIO_INT_DEDGE_SET, mask); |
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break; |
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case IRQ_TYPE_EDGE_RISING: |
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hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_SET_WX, mask); |
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hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_SET_WX, mask); |
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break; |
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case IRQ_TYPE_EDGE_FALLING: |
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hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_SET_WX, mask); |
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hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_CLR_WX, mask); |
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break; |
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case IRQ_TYPE_LEVEL_HIGH: |
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hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_CLR_WX, mask); |
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hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_SET_WX, mask); |
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break; |
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case IRQ_TYPE_LEVEL_LOW: |
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hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_CLR_WX, mask); |
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hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_CLR_WX, mask); |
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break; |
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default: |
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return -EINVAL; |
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} |
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/* |
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* The dual-edge interrupt and other interrupt's registers do not |
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* take effect at the same time. The registers of the two-edge |
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* interrupts have higher priorities, the configuration of |
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* the dual-edge interrupts must be disabled before the configuration |
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* of other kind of interrupts. |
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*/ |
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if (type != IRQ_TYPE_EDGE_BOTH) { |
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unsigned int both = hisi_gpio_read_reg(chip, HISI_GPIO_INT_DEDGE_ST); |
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if (both & mask) |
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hisi_gpio_write_reg(chip, HISI_GPIO_INT_DEDGE_CLR, mask); |
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} |
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if (type & IRQ_TYPE_LEVEL_MASK) |
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irq_set_handler_locked(d, handle_level_irq); |
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else if (type & IRQ_TYPE_EDGE_BOTH) |
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irq_set_handler_locked(d, handle_edge_irq); |
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return 0; |
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} |
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static void hisi_gpio_irq_enable(struct irq_data *d) |
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{ |
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struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
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hisi_gpio_irq_clr_mask(d); |
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hisi_gpio_write_reg(chip, HISI_GPIO_INTEN_SET_WX, BIT(irqd_to_hwirq(d))); |
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} |
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static void hisi_gpio_irq_disable(struct irq_data *d) |
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{ |
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struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
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hisi_gpio_irq_set_mask(d); |
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hisi_gpio_write_reg(chip, HISI_GPIO_INTEN_CLR_WX, BIT(irqd_to_hwirq(d))); |
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} |
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static void hisi_gpio_irq_handler(struct irq_desc *desc) |
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{ |
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struct hisi_gpio *hisi_gpio = irq_desc_get_handler_data(desc); |
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unsigned long irq_msk = hisi_gpio_read_reg(&hisi_gpio->chip, |
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HISI_GPIO_INTSTATUS_WX); |
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struct irq_chip *irq_c = irq_desc_get_chip(desc); |
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int hwirq; |
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chained_irq_enter(irq_c, desc); |
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for_each_set_bit(hwirq, &irq_msk, HISI_GPIO_LINE_NUM_MAX) |
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generic_handle_irq(irq_find_mapping(hisi_gpio->chip.irq.domain, |
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hwirq)); |
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chained_irq_exit(irq_c, desc); |
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} |
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static void hisi_gpio_init_irq(struct hisi_gpio *hisi_gpio) |
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{ |
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struct gpio_chip *chip = &hisi_gpio->chip; |
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struct gpio_irq_chip *girq_chip = &chip->irq; |
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/* Set hooks for irq_chip */ |
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hisi_gpio->irq_chip.irq_ack = hisi_gpio_set_ack; |
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hisi_gpio->irq_chip.irq_mask = hisi_gpio_irq_set_mask; |
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hisi_gpio->irq_chip.irq_unmask = hisi_gpio_irq_clr_mask; |
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hisi_gpio->irq_chip.irq_set_type = hisi_gpio_irq_set_type; |
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hisi_gpio->irq_chip.irq_enable = hisi_gpio_irq_enable; |
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hisi_gpio->irq_chip.irq_disable = hisi_gpio_irq_disable; |
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girq_chip->chip = &hisi_gpio->irq_chip; |
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girq_chip->default_type = IRQ_TYPE_NONE; |
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girq_chip->num_parents = 1; |
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girq_chip->parents = &hisi_gpio->irq; |
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girq_chip->parent_handler = hisi_gpio_irq_handler; |
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girq_chip->parent_handler_data = hisi_gpio; |
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/* Clear Mask of GPIO controller combine IRQ */ |
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hisi_gpio_write_reg(chip, HISI_GPIO_INTCOMB_MASK_WX, 1); |
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} |
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static const struct acpi_device_id hisi_gpio_acpi_match[] = { |
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{"HISI0184", 0}, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(acpi, hisi_gpio_acpi_match); |
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static void hisi_gpio_get_pdata(struct device *dev, |
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struct hisi_gpio *hisi_gpio) |
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{ |
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struct platform_device *pdev = to_platform_device(dev); |
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struct fwnode_handle *fwnode; |
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int idx = 0; |
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device_for_each_child_node(dev, fwnode) { |
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/* Cycle for once, no need for an array to save line_num */ |
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if (fwnode_property_read_u32(fwnode, "ngpios", |
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&hisi_gpio->line_num)) { |
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dev_err(dev, |
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"failed to get number of lines for port%d and use default value instead\n", |
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idx); |
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hisi_gpio->line_num = HISI_GPIO_LINE_NUM_MAX; |
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} |
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if (WARN_ON(hisi_gpio->line_num > HISI_GPIO_LINE_NUM_MAX)) |
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hisi_gpio->line_num = HISI_GPIO_LINE_NUM_MAX; |
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hisi_gpio->irq = platform_get_irq(pdev, idx); |
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dev_info(dev, |
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"get hisi_gpio[%d] with %d lines\n", idx, |
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hisi_gpio->line_num); |
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idx++; |
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} |
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} |
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static int hisi_gpio_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct hisi_gpio *hisi_gpio; |
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int port_num; |
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int ret; |
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/* |
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* One GPIO controller own one port currently, |
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* if we get more from ACPI table, return error. |
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*/ |
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port_num = device_get_child_node_count(dev); |
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if (WARN_ON(port_num != 1)) |
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return -ENODEV; |
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hisi_gpio = devm_kzalloc(dev, sizeof(*hisi_gpio), GFP_KERNEL); |
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if (!hisi_gpio) |
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return -ENOMEM; |
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hisi_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(hisi_gpio->reg_base)) |
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return PTR_ERR(hisi_gpio->reg_base); |
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hisi_gpio_get_pdata(dev, hisi_gpio); |
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hisi_gpio->dev = dev; |
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ret = bgpio_init(&hisi_gpio->chip, hisi_gpio->dev, 0x4, |
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hisi_gpio->reg_base + HISI_GPIO_EXT_PORT_WX, |
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hisi_gpio->reg_base + HISI_GPIO_SWPORT_DR_SET_WX, |
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hisi_gpio->reg_base + HISI_GPIO_SWPORT_DR_CLR_WX, |
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hisi_gpio->reg_base + HISI_GPIO_SWPORT_DDR_SET_WX, |
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hisi_gpio->reg_base + HISI_GPIO_SWPORT_DDR_CLR_WX, |
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BGPIOF_NO_SET_ON_INPUT); |
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if (ret) { |
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dev_err(dev, "failed to init, ret = %d\n", ret); |
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return ret; |
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} |
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hisi_gpio->chip.set_config = hisi_gpio_set_config; |
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hisi_gpio->chip.ngpio = hisi_gpio->line_num; |
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hisi_gpio->chip.bgpio_dir_unreadable = 1; |
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hisi_gpio->chip.base = -1; |
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if (hisi_gpio->irq > 0) |
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hisi_gpio_init_irq(hisi_gpio); |
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ret = devm_gpiochip_add_data(dev, &hisi_gpio->chip, hisi_gpio); |
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if (ret) { |
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dev_err(dev, "failed to register gpiochip, ret = %d\n", ret); |
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return ret; |
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} |
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return 0; |
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} |
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static struct platform_driver hisi_gpio_driver = { |
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.driver = { |
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.name = HISI_GPIO_DRIVER_NAME, |
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.acpi_match_table = hisi_gpio_acpi_match, |
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}, |
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.probe = hisi_gpio_probe, |
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}; |
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module_platform_driver(hisi_gpio_driver); |
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MODULE_LICENSE("GPL"); |
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MODULE_AUTHOR("Luo Jiaxing <[email protected]>"); |
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MODULE_DESCRIPTION("HiSilicon GPIO controller driver"); |
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MODULE_ALIAS("platform:" HISI_GPIO_DRIVER_NAME);
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