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651 lines
17 KiB
651 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* TI DaVinci GPIO Support |
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* |
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* Copyright (c) 2006-2007 David Brownell |
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* Copyright (c) 2007, MontaVista Software, Inc. <[email protected]> |
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*/ |
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|
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#include <linux/gpio/driver.h> |
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#include <linux/errno.h> |
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#include <linux/kernel.h> |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/irqdomain.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/pinctrl/consumer.h> |
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#include <linux/platform_device.h> |
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#include <linux/platform_data/gpio-davinci.h> |
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#include <linux/irqchip/chained_irq.h> |
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#include <linux/spinlock.h> |
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#include <asm-generic/gpio.h> |
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#define MAX_REGS_BANKS 5 |
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#define MAX_INT_PER_BANK 32 |
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struct davinci_gpio_regs { |
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u32 dir; |
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u32 out_data; |
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u32 set_data; |
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u32 clr_data; |
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u32 in_data; |
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u32 set_rising; |
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u32 clr_rising; |
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u32 set_falling; |
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u32 clr_falling; |
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u32 intstat; |
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}; |
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typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq); |
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#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ |
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static void __iomem *gpio_base; |
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static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0}; |
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struct davinci_gpio_irq_data { |
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void __iomem *regs; |
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struct davinci_gpio_controller *chip; |
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int bank_num; |
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}; |
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struct davinci_gpio_controller { |
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struct gpio_chip chip; |
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struct irq_domain *irq_domain; |
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/* Serialize access to GPIO registers */ |
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spinlock_t lock; |
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void __iomem *regs[MAX_REGS_BANKS]; |
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int gpio_unbanked; |
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int irqs[MAX_INT_PER_BANK]; |
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}; |
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static inline u32 __gpio_mask(unsigned gpio) |
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{ |
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return 1 << (gpio % 32); |
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} |
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static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d) |
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{ |
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struct davinci_gpio_regs __iomem *g; |
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g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d); |
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return g; |
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} |
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static int davinci_gpio_irq_setup(struct platform_device *pdev); |
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/*--------------------------------------------------------------------------*/ |
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|
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/* board setup code *MUST* setup pinmux and enable the GPIO clock. */ |
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static inline int __davinci_direction(struct gpio_chip *chip, |
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unsigned offset, bool out, int value) |
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{ |
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struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
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struct davinci_gpio_regs __iomem *g; |
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unsigned long flags; |
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u32 temp; |
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int bank = offset / 32; |
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u32 mask = __gpio_mask(offset); |
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g = d->regs[bank]; |
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spin_lock_irqsave(&d->lock, flags); |
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temp = readl_relaxed(&g->dir); |
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if (out) { |
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temp &= ~mask; |
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writel_relaxed(mask, value ? &g->set_data : &g->clr_data); |
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} else { |
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temp |= mask; |
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} |
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writel_relaxed(temp, &g->dir); |
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spin_unlock_irqrestore(&d->lock, flags); |
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return 0; |
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} |
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static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) |
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{ |
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return __davinci_direction(chip, offset, false, 0); |
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} |
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static int |
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davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) |
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{ |
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return __davinci_direction(chip, offset, true, value); |
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} |
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/* |
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* Read the pin's value (works even if it's set up as output); |
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* returns zero/nonzero. |
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* |
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* Note that changes are synched to the GPIO clock, so reading values back |
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* right after you've set them may give old values. |
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*/ |
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static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) |
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{ |
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struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
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struct davinci_gpio_regs __iomem *g; |
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int bank = offset / 32; |
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g = d->regs[bank]; |
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return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data)); |
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} |
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/* |
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* Assuming the pin is muxed as a gpio output, set its output value. |
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*/ |
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static void |
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davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
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{ |
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struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
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struct davinci_gpio_regs __iomem *g; |
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int bank = offset / 32; |
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g = d->regs[bank]; |
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writel_relaxed(__gpio_mask(offset), |
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value ? &g->set_data : &g->clr_data); |
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} |
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static struct davinci_gpio_platform_data * |
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davinci_gpio_get_pdata(struct platform_device *pdev) |
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{ |
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struct device_node *dn = pdev->dev.of_node; |
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struct davinci_gpio_platform_data *pdata; |
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int ret; |
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u32 val; |
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if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) |
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return dev_get_platdata(&pdev->dev); |
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pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
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if (!pdata) |
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return NULL; |
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ret = of_property_read_u32(dn, "ti,ngpio", &val); |
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if (ret) |
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goto of_err; |
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pdata->ngpio = val; |
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ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val); |
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if (ret) |
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goto of_err; |
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pdata->gpio_unbanked = val; |
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return pdata; |
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of_err: |
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dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret); |
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return NULL; |
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} |
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static int davinci_gpio_probe(struct platform_device *pdev) |
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{ |
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int bank, i, ret = 0; |
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unsigned int ngpio, nbank, nirq; |
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struct davinci_gpio_controller *chips; |
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struct davinci_gpio_platform_data *pdata; |
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struct device *dev = &pdev->dev; |
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pdata = davinci_gpio_get_pdata(pdev); |
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if (!pdata) { |
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dev_err(dev, "No platform data found\n"); |
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return -EINVAL; |
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} |
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dev->platform_data = pdata; |
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/* |
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* The gpio banks conceptually expose a segmented bitmap, |
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* and "ngpio" is one more than the largest zero-based |
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* bit index that's valid. |
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*/ |
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ngpio = pdata->ngpio; |
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if (ngpio == 0) { |
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dev_err(dev, "How many GPIOs?\n"); |
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return -EINVAL; |
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} |
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if (WARN_ON(ARCH_NR_GPIOS < ngpio)) |
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ngpio = ARCH_NR_GPIOS; |
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/* |
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* If there are unbanked interrupts then the number of |
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* interrupts is equal to number of gpios else all are banked so |
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* number of interrupts is equal to number of banks(each with 16 gpios) |
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*/ |
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if (pdata->gpio_unbanked) |
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nirq = pdata->gpio_unbanked; |
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else |
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nirq = DIV_ROUND_UP(ngpio, 16); |
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chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL); |
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if (!chips) |
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return -ENOMEM; |
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gpio_base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(gpio_base)) |
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return PTR_ERR(gpio_base); |
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for (i = 0; i < nirq; i++) { |
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chips->irqs[i] = platform_get_irq(pdev, i); |
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if (chips->irqs[i] < 0) |
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return dev_err_probe(dev, chips->irqs[i], "IRQ not populated\n"); |
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} |
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chips->chip.label = dev_name(dev); |
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chips->chip.direction_input = davinci_direction_in; |
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chips->chip.get = davinci_gpio_get; |
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chips->chip.direction_output = davinci_direction_out; |
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chips->chip.set = davinci_gpio_set; |
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chips->chip.ngpio = ngpio; |
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chips->chip.base = pdata->no_auto_base ? pdata->base : -1; |
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#ifdef CONFIG_OF_GPIO |
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chips->chip.of_gpio_n_cells = 2; |
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chips->chip.parent = dev; |
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chips->chip.of_node = dev->of_node; |
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chips->chip.request = gpiochip_generic_request; |
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chips->chip.free = gpiochip_generic_free; |
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#endif |
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spin_lock_init(&chips->lock); |
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nbank = DIV_ROUND_UP(ngpio, 32); |
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for (bank = 0; bank < nbank; bank++) |
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chips->regs[bank] = gpio_base + offset_array[bank]; |
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ret = devm_gpiochip_add_data(dev, &chips->chip, chips); |
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if (ret) |
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return ret; |
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platform_set_drvdata(pdev, chips); |
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ret = davinci_gpio_irq_setup(pdev); |
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if (ret) |
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return ret; |
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return 0; |
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} |
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/*--------------------------------------------------------------------------*/ |
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/* |
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* We expect irqs will normally be set up as input pins, but they can also be |
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* used as output pins ... which is convenient for testing. |
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* |
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* NOTE: The first few GPIOs also have direct INTC hookups in addition |
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* to their GPIOBNK0 irq, with a bit less overhead. |
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* |
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* All those INTC hookups (direct, plus several IRQ banks) can also |
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* serve as EDMA event triggers. |
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*/ |
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static void gpio_irq_disable(struct irq_data *d) |
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{ |
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struct davinci_gpio_regs __iomem *g = irq2regs(d); |
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uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d); |
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writel_relaxed(mask, &g->clr_falling); |
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writel_relaxed(mask, &g->clr_rising); |
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} |
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static void gpio_irq_enable(struct irq_data *d) |
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{ |
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struct davinci_gpio_regs __iomem *g = irq2regs(d); |
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uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d); |
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unsigned status = irqd_get_trigger_type(d); |
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status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
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if (!status) |
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status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
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if (status & IRQ_TYPE_EDGE_FALLING) |
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writel_relaxed(mask, &g->set_falling); |
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if (status & IRQ_TYPE_EDGE_RISING) |
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writel_relaxed(mask, &g->set_rising); |
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} |
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static int gpio_irq_type(struct irq_data *d, unsigned trigger) |
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{ |
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if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
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return -EINVAL; |
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return 0; |
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} |
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static struct irq_chip gpio_irqchip = { |
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.name = "GPIO", |
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.irq_enable = gpio_irq_enable, |
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.irq_disable = gpio_irq_disable, |
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.irq_set_type = gpio_irq_type, |
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.flags = IRQCHIP_SET_TYPE_MASKED, |
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}; |
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static void gpio_irq_handler(struct irq_desc *desc) |
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{ |
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struct davinci_gpio_regs __iomem *g; |
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u32 mask = 0xffff; |
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int bank_num; |
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struct davinci_gpio_controller *d; |
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struct davinci_gpio_irq_data *irqdata; |
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irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc); |
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bank_num = irqdata->bank_num; |
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g = irqdata->regs; |
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d = irqdata->chip; |
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/* we only care about one bank */ |
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if ((bank_num % 2) == 1) |
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mask <<= 16; |
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/* temporarily mask (level sensitive) parent IRQ */ |
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chained_irq_enter(irq_desc_get_chip(desc), desc); |
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while (1) { |
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u32 status; |
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int bit; |
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irq_hw_number_t hw_irq; |
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/* ack any irqs */ |
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status = readl_relaxed(&g->intstat) & mask; |
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if (!status) |
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break; |
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writel_relaxed(status, &g->intstat); |
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/* now demux them to the right lowlevel handler */ |
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while (status) { |
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bit = __ffs(status); |
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status &= ~BIT(bit); |
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/* Max number of gpios per controller is 144 so |
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* hw_irq will be in [0..143] |
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*/ |
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hw_irq = (bank_num / 2) * 32 + bit; |
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generic_handle_irq( |
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irq_find_mapping(d->irq_domain, hw_irq)); |
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} |
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} |
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chained_irq_exit(irq_desc_get_chip(desc), desc); |
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/* now it may re-trigger */ |
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} |
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static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) |
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{ |
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struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
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if (d->irq_domain) |
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return irq_create_mapping(d->irq_domain, offset); |
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else |
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return -ENXIO; |
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} |
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static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) |
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{ |
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struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
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/* |
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* NOTE: we assume for now that only irqs in the first gpio_chip |
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* can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). |
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*/ |
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if (offset < d->gpio_unbanked) |
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return d->irqs[offset]; |
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else |
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return -ENODEV; |
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} |
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static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) |
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{ |
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struct davinci_gpio_controller *d; |
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struct davinci_gpio_regs __iomem *g; |
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u32 mask, i; |
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d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data); |
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g = (struct davinci_gpio_regs __iomem *)d->regs[0]; |
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for (i = 0; i < MAX_INT_PER_BANK; i++) |
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if (data->irq == d->irqs[i]) |
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break; |
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if (i == MAX_INT_PER_BANK) |
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return -EINVAL; |
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mask = __gpio_mask(i); |
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if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
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return -EINVAL; |
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writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING) |
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? &g->set_falling : &g->clr_falling); |
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writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING) |
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? &g->set_rising : &g->clr_rising); |
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return 0; |
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} |
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static int |
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davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq, |
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irq_hw_number_t hw) |
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{ |
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struct davinci_gpio_controller *chips = |
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(struct davinci_gpio_controller *)d->host_data; |
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struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32]; |
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irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, |
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"davinci_gpio"); |
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irq_set_irq_type(irq, IRQ_TYPE_NONE); |
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irq_set_chip_data(irq, (__force void *)g); |
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irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw)); |
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return 0; |
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} |
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static const struct irq_domain_ops davinci_gpio_irq_ops = { |
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.map = davinci_gpio_irq_map, |
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.xlate = irq_domain_xlate_onetwocell, |
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}; |
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static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq) |
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{ |
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static struct irq_chip_type gpio_unbanked; |
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gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq)); |
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return &gpio_unbanked.chip; |
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}; |
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static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq) |
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{ |
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static struct irq_chip gpio_unbanked; |
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gpio_unbanked = *irq_get_chip(irq); |
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return &gpio_unbanked; |
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}; |
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static const struct of_device_id davinci_gpio_ids[]; |
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|
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/* |
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* NOTE: for suspend/resume, probably best to make a platform_device with |
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* suspend_late/resume_resume calls hooking into results of the set_wake() |
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* calls ... so if no gpios are wakeup events the clock can be disabled, |
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* with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 |
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* (dm6446) can be set appropriately for GPIOV33 pins. |
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*/ |
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static int davinci_gpio_irq_setup(struct platform_device *pdev) |
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{ |
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unsigned gpio, bank; |
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int irq; |
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int ret; |
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struct clk *clk; |
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u32 binten = 0; |
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unsigned ngpio; |
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struct device *dev = &pdev->dev; |
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struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); |
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struct davinci_gpio_platform_data *pdata = dev->platform_data; |
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struct davinci_gpio_regs __iomem *g; |
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struct irq_domain *irq_domain = NULL; |
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const struct of_device_id *match; |
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struct irq_chip *irq_chip; |
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struct davinci_gpio_irq_data *irqdata; |
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gpio_get_irq_chip_cb_t gpio_get_irq_chip; |
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|
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/* |
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* Use davinci_gpio_get_irq_chip by default to handle non DT cases |
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*/ |
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gpio_get_irq_chip = davinci_gpio_get_irq_chip; |
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match = of_match_device(of_match_ptr(davinci_gpio_ids), |
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dev); |
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if (match) |
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gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data; |
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ngpio = pdata->ngpio; |
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clk = devm_clk_get(dev, "gpio"); |
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if (IS_ERR(clk)) { |
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dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk)); |
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return PTR_ERR(clk); |
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} |
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ret = clk_prepare_enable(clk); |
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if (ret) |
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return ret; |
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|
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if (!pdata->gpio_unbanked) { |
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irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0); |
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if (irq < 0) { |
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dev_err(dev, "Couldn't allocate IRQ numbers\n"); |
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clk_disable_unprepare(clk); |
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return irq; |
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} |
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irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0, |
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&davinci_gpio_irq_ops, |
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chips); |
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if (!irq_domain) { |
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dev_err(dev, "Couldn't register an IRQ domain\n"); |
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clk_disable_unprepare(clk); |
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return -ENODEV; |
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} |
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} |
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|
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/* |
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* Arrange gpio_to_irq() support, handling either direct IRQs or |
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* banked IRQs. Having GPIOs in the first GPIO bank use direct |
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* IRQs, while the others use banked IRQs, would need some setup |
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* tweaks to recognize hardware which can do that. |
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*/ |
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chips->chip.to_irq = gpio_to_irq_banked; |
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chips->irq_domain = irq_domain; |
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|
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/* |
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* AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO |
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* controller only handling trigger modes. We currently assume no |
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* IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. |
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*/ |
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if (pdata->gpio_unbanked) { |
|
/* pass "bank 0" GPIO IRQs to AINTC */ |
|
chips->chip.to_irq = gpio_to_irq_unbanked; |
|
chips->gpio_unbanked = pdata->gpio_unbanked; |
|
binten = GENMASK(pdata->gpio_unbanked / 16, 0); |
|
|
|
/* AINTC handles mask/unmask; GPIO handles triggering */ |
|
irq = chips->irqs[0]; |
|
irq_chip = gpio_get_irq_chip(irq); |
|
irq_chip->name = "GPIO-AINTC"; |
|
irq_chip->irq_set_type = gpio_irq_type_unbanked; |
|
|
|
/* default trigger: both edges */ |
|
g = chips->regs[0]; |
|
writel_relaxed(~0, &g->set_falling); |
|
writel_relaxed(~0, &g->set_rising); |
|
|
|
/* set the direct IRQs up to use that irqchip */ |
|
for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) { |
|
irq_set_chip(chips->irqs[gpio], irq_chip); |
|
irq_set_handler_data(chips->irqs[gpio], chips); |
|
irq_set_status_flags(chips->irqs[gpio], |
|
IRQ_TYPE_EDGE_BOTH); |
|
} |
|
|
|
goto done; |
|
} |
|
|
|
/* |
|
* Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we |
|
* then chain through our own handler. |
|
*/ |
|
for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) { |
|
/* disabled by default, enabled only as needed |
|
* There are register sets for 32 GPIOs. 2 banks of 16 |
|
* GPIOs are covered by each set of registers hence divide by 2 |
|
*/ |
|
g = chips->regs[bank / 2]; |
|
writel_relaxed(~0, &g->clr_falling); |
|
writel_relaxed(~0, &g->clr_rising); |
|
|
|
/* |
|
* Each chip handles 32 gpios, and each irq bank consists of 16 |
|
* gpio irqs. Pass the irq bank's corresponding controller to |
|
* the chained irq handler. |
|
*/ |
|
irqdata = devm_kzalloc(&pdev->dev, |
|
sizeof(struct |
|
davinci_gpio_irq_data), |
|
GFP_KERNEL); |
|
if (!irqdata) { |
|
clk_disable_unprepare(clk); |
|
return -ENOMEM; |
|
} |
|
|
|
irqdata->regs = g; |
|
irqdata->bank_num = bank; |
|
irqdata->chip = chips; |
|
|
|
irq_set_chained_handler_and_data(chips->irqs[bank], |
|
gpio_irq_handler, irqdata); |
|
|
|
binten |= BIT(bank); |
|
} |
|
|
|
done: |
|
/* |
|
* BINTEN -- per-bank interrupt enable. genirq would also let these |
|
* bits be set/cleared dynamically. |
|
*/ |
|
writel_relaxed(binten, gpio_base + BINTEN); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id davinci_gpio_ids[] = { |
|
{ .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip}, |
|
{ .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip}, |
|
{ .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip}, |
|
{ /* sentinel */ }, |
|
}; |
|
MODULE_DEVICE_TABLE(of, davinci_gpio_ids); |
|
|
|
static struct platform_driver davinci_gpio_driver = { |
|
.probe = davinci_gpio_probe, |
|
.driver = { |
|
.name = "davinci_gpio", |
|
.of_match_table = of_match_ptr(davinci_gpio_ids), |
|
}, |
|
}; |
|
|
|
/** |
|
* GPIO driver registration needs to be done before machine_init functions |
|
* access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall. |
|
*/ |
|
static int __init davinci_gpio_drv_reg(void) |
|
{ |
|
return platform_driver_register(&davinci_gpio_driver); |
|
} |
|
postcore_initcall(davinci_gpio_drv_reg);
|
|
|