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560 lines
16 KiB
560 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* CPU frequency scaling support for Armada 37xx platform. |
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* |
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* Copyright (C) 2017 Marvell |
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* |
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* Gregory CLEMENT <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/cpu.h> |
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#include <linux/cpufreq.h> |
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#include <linux/err.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/module.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/of_irq.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_opp.h> |
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#include <linux/regmap.h> |
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#include <linux/slab.h> |
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#include "cpufreq-dt.h" |
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/* Clk register set */ |
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#define ARMADA_37XX_CLK_TBG_SEL 0 |
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#define ARMADA_37XX_CLK_TBG_SEL_CPU_OFF 22 |
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/* Power management in North Bridge register set */ |
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#define ARMADA_37XX_NB_L0L1 0x18 |
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#define ARMADA_37XX_NB_L2L3 0x1C |
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#define ARMADA_37XX_NB_TBG_DIV_OFF 13 |
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#define ARMADA_37XX_NB_TBG_DIV_MASK 0x7 |
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#define ARMADA_37XX_NB_CLK_SEL_OFF 11 |
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#define ARMADA_37XX_NB_CLK_SEL_MASK 0x1 |
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#define ARMADA_37XX_NB_CLK_SEL_TBG 0x1 |
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#define ARMADA_37XX_NB_TBG_SEL_OFF 9 |
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#define ARMADA_37XX_NB_TBG_SEL_MASK 0x3 |
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#define ARMADA_37XX_NB_VDD_SEL_OFF 6 |
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#define ARMADA_37XX_NB_VDD_SEL_MASK 0x3 |
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#define ARMADA_37XX_NB_CONFIG_SHIFT 16 |
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#define ARMADA_37XX_NB_DYN_MOD 0x24 |
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#define ARMADA_37XX_NB_CLK_SEL_EN BIT(26) |
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#define ARMADA_37XX_NB_TBG_EN BIT(28) |
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#define ARMADA_37XX_NB_DIV_EN BIT(29) |
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#define ARMADA_37XX_NB_VDD_EN BIT(30) |
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#define ARMADA_37XX_NB_DFS_EN BIT(31) |
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#define ARMADA_37XX_NB_CPU_LOAD 0x30 |
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#define ARMADA_37XX_NB_CPU_LOAD_MASK 0x3 |
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#define ARMADA_37XX_DVFS_LOAD_0 0 |
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#define ARMADA_37XX_DVFS_LOAD_1 1 |
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#define ARMADA_37XX_DVFS_LOAD_2 2 |
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#define ARMADA_37XX_DVFS_LOAD_3 3 |
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/* AVS register set */ |
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#define ARMADA_37XX_AVS_CTL0 0x0 |
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#define ARMADA_37XX_AVS_ENABLE BIT(30) |
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#define ARMADA_37XX_AVS_HIGH_VDD_LIMIT 16 |
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#define ARMADA_37XX_AVS_LOW_VDD_LIMIT 22 |
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#define ARMADA_37XX_AVS_VDD_MASK 0x3F |
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#define ARMADA_37XX_AVS_CTL2 0x8 |
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#define ARMADA_37XX_AVS_LOW_VDD_EN BIT(6) |
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#define ARMADA_37XX_AVS_VSET(x) (0x1C + 4 * (x)) |
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/* |
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* On Armada 37xx the Power management manages 4 level of CPU load, |
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* each level can be associated with a CPU clock source, a CPU |
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* divider, a VDD level, etc... |
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*/ |
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#define LOAD_LEVEL_NR 4 |
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#define MIN_VOLT_MV 1000 |
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#define MIN_VOLT_MV_FOR_L1_1000MHZ 1108 |
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#define MIN_VOLT_MV_FOR_L1_1200MHZ 1155 |
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/* AVS value for the corresponding voltage (in mV) */ |
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static int avs_map[] = { |
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747, 758, 770, 782, 793, 805, 817, 828, 840, 852, 863, 875, 887, 898, |
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910, 922, 933, 945, 957, 968, 980, 992, 1003, 1015, 1027, 1038, 1050, |
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1062, 1073, 1085, 1097, 1108, 1120, 1132, 1143, 1155, 1167, 1178, 1190, |
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1202, 1213, 1225, 1237, 1248, 1260, 1272, 1283, 1295, 1307, 1318, 1330, |
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1342 |
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}; |
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struct armada37xx_cpufreq_state { |
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struct platform_device *pdev; |
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struct device *cpu_dev; |
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struct regmap *regmap; |
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u32 nb_l0l1; |
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u32 nb_l2l3; |
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u32 nb_dyn_mod; |
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u32 nb_cpu_load; |
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}; |
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static struct armada37xx_cpufreq_state *armada37xx_cpufreq_state; |
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struct armada_37xx_dvfs { |
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u32 cpu_freq_max; |
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u8 divider[LOAD_LEVEL_NR]; |
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u32 avs[LOAD_LEVEL_NR]; |
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}; |
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static struct armada_37xx_dvfs armada_37xx_dvfs[] = { |
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{.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} }, |
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{.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} }, |
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{.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} }, |
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{.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} }, |
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}; |
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static struct armada_37xx_dvfs *armada_37xx_cpu_freq_info_get(u32 freq) |
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{ |
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int i; |
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for (i = 0; i < ARRAY_SIZE(armada_37xx_dvfs); i++) { |
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if (freq == armada_37xx_dvfs[i].cpu_freq_max) |
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return &armada_37xx_dvfs[i]; |
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} |
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pr_err("Unsupported CPU frequency %d MHz\n", freq/1000000); |
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return NULL; |
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} |
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/* |
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* Setup the four level managed by the hardware. Once the four level |
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* will be configured then the DVFS will be enabled. |
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*/ |
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static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base, |
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struct regmap *clk_base, u8 *divider) |
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{ |
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u32 cpu_tbg_sel; |
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int load_lvl; |
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/* Determine to which TBG clock is CPU connected */ |
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regmap_read(clk_base, ARMADA_37XX_CLK_TBG_SEL, &cpu_tbg_sel); |
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cpu_tbg_sel >>= ARMADA_37XX_CLK_TBG_SEL_CPU_OFF; |
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cpu_tbg_sel &= ARMADA_37XX_NB_TBG_SEL_MASK; |
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for (load_lvl = 0; load_lvl < LOAD_LEVEL_NR; load_lvl++) { |
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unsigned int reg, mask, val, offset = 0; |
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if (load_lvl <= ARMADA_37XX_DVFS_LOAD_1) |
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reg = ARMADA_37XX_NB_L0L1; |
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else |
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reg = ARMADA_37XX_NB_L2L3; |
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if (load_lvl == ARMADA_37XX_DVFS_LOAD_0 || |
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load_lvl == ARMADA_37XX_DVFS_LOAD_2) |
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offset += ARMADA_37XX_NB_CONFIG_SHIFT; |
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/* Set cpu clock source, for all the level we use TBG */ |
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val = ARMADA_37XX_NB_CLK_SEL_TBG << ARMADA_37XX_NB_CLK_SEL_OFF; |
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mask = (ARMADA_37XX_NB_CLK_SEL_MASK |
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<< ARMADA_37XX_NB_CLK_SEL_OFF); |
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/* Set TBG index, for all levels we use the same TBG */ |
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val = cpu_tbg_sel << ARMADA_37XX_NB_TBG_SEL_OFF; |
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mask = (ARMADA_37XX_NB_TBG_SEL_MASK |
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<< ARMADA_37XX_NB_TBG_SEL_OFF); |
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/* |
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* Set cpu divider based on the pre-computed array in |
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* order to have balanced step. |
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*/ |
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val |= divider[load_lvl] << ARMADA_37XX_NB_TBG_DIV_OFF; |
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mask |= (ARMADA_37XX_NB_TBG_DIV_MASK |
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<< ARMADA_37XX_NB_TBG_DIV_OFF); |
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/* Set VDD divider which is actually the load level. */ |
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val |= load_lvl << ARMADA_37XX_NB_VDD_SEL_OFF; |
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mask |= (ARMADA_37XX_NB_VDD_SEL_MASK |
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<< ARMADA_37XX_NB_VDD_SEL_OFF); |
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val <<= offset; |
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mask <<= offset; |
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regmap_update_bits(base, reg, mask, val); |
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} |
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} |
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/* |
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* Find out the armada 37x supported AVS value whose voltage value is |
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* the round-up closest to the target voltage value. |
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*/ |
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static u32 armada_37xx_avs_val_match(int target_vm) |
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{ |
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u32 avs; |
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/* Find out the round-up closest supported voltage value */ |
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for (avs = 0; avs < ARRAY_SIZE(avs_map); avs++) |
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if (avs_map[avs] >= target_vm) |
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break; |
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/* |
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* If all supported voltages are smaller than target one, |
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* choose the largest supported voltage |
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*/ |
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if (avs == ARRAY_SIZE(avs_map)) |
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avs = ARRAY_SIZE(avs_map) - 1; |
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return avs; |
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} |
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/* |
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* For Armada 37xx soc, L0(VSET0) VDD AVS value is set to SVC revision |
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* value or a default value when SVC is not supported. |
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* - L0 can be read out from the register of AVS_CTRL_0 and L0 voltage |
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* can be got from the mapping table of avs_map. |
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* - L1 voltage should be about 100mv smaller than L0 voltage |
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* - L2 & L3 voltage should be about 150mv smaller than L0 voltage. |
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* This function calculates L1 & L2 & L3 AVS values dynamically based |
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* on L0 voltage and fill all AVS values to the AVS value table. |
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* When base CPU frequency is 1000 or 1200 MHz then there is additional |
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* minimal avs value for load L1. |
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*/ |
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static void __init armada37xx_cpufreq_avs_configure(struct regmap *base, |
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struct armada_37xx_dvfs *dvfs) |
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{ |
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unsigned int target_vm; |
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int load_level = 0; |
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u32 l0_vdd_min; |
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if (base == NULL) |
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return; |
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/* Get L0 VDD min value */ |
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regmap_read(base, ARMADA_37XX_AVS_CTL0, &l0_vdd_min); |
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l0_vdd_min = (l0_vdd_min >> ARMADA_37XX_AVS_LOW_VDD_LIMIT) & |
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ARMADA_37XX_AVS_VDD_MASK; |
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if (l0_vdd_min >= ARRAY_SIZE(avs_map)) { |
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pr_err("L0 VDD MIN %d is not correct.\n", l0_vdd_min); |
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return; |
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} |
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dvfs->avs[0] = l0_vdd_min; |
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if (avs_map[l0_vdd_min] <= MIN_VOLT_MV) { |
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/* |
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* If L0 voltage is smaller than 1000mv, then all VDD sets |
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* use L0 voltage; |
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*/ |
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u32 avs_min = armada_37xx_avs_val_match(MIN_VOLT_MV); |
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for (load_level = 1; load_level < LOAD_LEVEL_NR; load_level++) |
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dvfs->avs[load_level] = avs_min; |
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/* |
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* Set the avs values for load L0 and L1 when base CPU frequency |
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* is 1000/1200 MHz to its typical initial values according to |
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* the Armada 3700 Hardware Specifications. |
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*/ |
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if (dvfs->cpu_freq_max >= 1000*1000*1000) { |
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if (dvfs->cpu_freq_max >= 1200*1000*1000) |
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avs_min = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L1_1200MHZ); |
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else |
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avs_min = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L1_1000MHZ); |
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dvfs->avs[0] = dvfs->avs[1] = avs_min; |
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} |
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return; |
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} |
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/* |
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* L1 voltage is equal to L0 voltage - 100mv and it must be |
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* larger than 1000mv |
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*/ |
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target_vm = avs_map[l0_vdd_min] - 100; |
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target_vm = target_vm > MIN_VOLT_MV ? target_vm : MIN_VOLT_MV; |
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dvfs->avs[1] = armada_37xx_avs_val_match(target_vm); |
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/* |
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* L2 & L3 voltage is equal to L0 voltage - 150mv and it must |
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* be larger than 1000mv |
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*/ |
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target_vm = avs_map[l0_vdd_min] - 150; |
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target_vm = target_vm > MIN_VOLT_MV ? target_vm : MIN_VOLT_MV; |
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dvfs->avs[2] = dvfs->avs[3] = armada_37xx_avs_val_match(target_vm); |
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/* |
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* Fix the avs value for load L1 when base CPU frequency is 1000/1200 MHz, |
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* otherwise the CPU gets stuck when switching from load L1 to load L0. |
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* Also ensure that avs value for load L1 is not higher than for L0. |
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*/ |
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if (dvfs->cpu_freq_max >= 1000*1000*1000) { |
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u32 avs_min_l1; |
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if (dvfs->cpu_freq_max >= 1200*1000*1000) |
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avs_min_l1 = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L1_1200MHZ); |
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else |
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avs_min_l1 = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L1_1000MHZ); |
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if (avs_min_l1 > dvfs->avs[0]) |
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avs_min_l1 = dvfs->avs[0]; |
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if (dvfs->avs[1] < avs_min_l1) |
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dvfs->avs[1] = avs_min_l1; |
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} |
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} |
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static void __init armada37xx_cpufreq_avs_setup(struct regmap *base, |
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struct armada_37xx_dvfs *dvfs) |
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{ |
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unsigned int avs_val = 0; |
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int load_level = 0; |
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if (base == NULL) |
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return; |
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/* Disable AVS before the configuration */ |
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regmap_update_bits(base, ARMADA_37XX_AVS_CTL0, |
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ARMADA_37XX_AVS_ENABLE, 0); |
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/* Enable low voltage mode */ |
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regmap_update_bits(base, ARMADA_37XX_AVS_CTL2, |
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ARMADA_37XX_AVS_LOW_VDD_EN, |
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ARMADA_37XX_AVS_LOW_VDD_EN); |
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for (load_level = 1; load_level < LOAD_LEVEL_NR; load_level++) { |
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avs_val = dvfs->avs[load_level]; |
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regmap_update_bits(base, ARMADA_37XX_AVS_VSET(load_level-1), |
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ARMADA_37XX_AVS_VDD_MASK << ARMADA_37XX_AVS_HIGH_VDD_LIMIT | |
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ARMADA_37XX_AVS_VDD_MASK << ARMADA_37XX_AVS_LOW_VDD_LIMIT, |
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avs_val << ARMADA_37XX_AVS_HIGH_VDD_LIMIT | |
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avs_val << ARMADA_37XX_AVS_LOW_VDD_LIMIT); |
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} |
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/* Enable AVS after the configuration */ |
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regmap_update_bits(base, ARMADA_37XX_AVS_CTL0, |
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ARMADA_37XX_AVS_ENABLE, |
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ARMADA_37XX_AVS_ENABLE); |
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} |
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static void armada37xx_cpufreq_disable_dvfs(struct regmap *base) |
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{ |
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unsigned int reg = ARMADA_37XX_NB_DYN_MOD, |
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mask = ARMADA_37XX_NB_DFS_EN; |
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regmap_update_bits(base, reg, mask, 0); |
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} |
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static void __init armada37xx_cpufreq_enable_dvfs(struct regmap *base) |
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{ |
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unsigned int val, reg = ARMADA_37XX_NB_CPU_LOAD, |
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mask = ARMADA_37XX_NB_CPU_LOAD_MASK; |
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/* Start with the highest load (0) */ |
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val = ARMADA_37XX_DVFS_LOAD_0; |
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regmap_update_bits(base, reg, mask, val); |
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/* Now enable DVFS for the CPUs */ |
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reg = ARMADA_37XX_NB_DYN_MOD; |
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mask = ARMADA_37XX_NB_CLK_SEL_EN | ARMADA_37XX_NB_TBG_EN | |
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ARMADA_37XX_NB_DIV_EN | ARMADA_37XX_NB_VDD_EN | |
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ARMADA_37XX_NB_DFS_EN; |
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regmap_update_bits(base, reg, mask, mask); |
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} |
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static int armada37xx_cpufreq_suspend(struct cpufreq_policy *policy) |
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{ |
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struct armada37xx_cpufreq_state *state = armada37xx_cpufreq_state; |
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regmap_read(state->regmap, ARMADA_37XX_NB_L0L1, &state->nb_l0l1); |
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regmap_read(state->regmap, ARMADA_37XX_NB_L2L3, &state->nb_l2l3); |
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regmap_read(state->regmap, ARMADA_37XX_NB_CPU_LOAD, |
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&state->nb_cpu_load); |
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regmap_read(state->regmap, ARMADA_37XX_NB_DYN_MOD, &state->nb_dyn_mod); |
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return 0; |
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} |
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static int armada37xx_cpufreq_resume(struct cpufreq_policy *policy) |
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{ |
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struct armada37xx_cpufreq_state *state = armada37xx_cpufreq_state; |
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/* Ensure DVFS is disabled otherwise the following registers are RO */ |
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armada37xx_cpufreq_disable_dvfs(state->regmap); |
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regmap_write(state->regmap, ARMADA_37XX_NB_L0L1, state->nb_l0l1); |
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regmap_write(state->regmap, ARMADA_37XX_NB_L2L3, state->nb_l2l3); |
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regmap_write(state->regmap, ARMADA_37XX_NB_CPU_LOAD, |
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state->nb_cpu_load); |
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/* |
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* NB_DYN_MOD register is the one that actually enable back DVFS if it |
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* was enabled before the suspend operation. This must be done last |
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* otherwise other registers are not writable. |
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*/ |
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regmap_write(state->regmap, ARMADA_37XX_NB_DYN_MOD, state->nb_dyn_mod); |
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return 0; |
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} |
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static int __init armada37xx_cpufreq_driver_init(void) |
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{ |
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struct cpufreq_dt_platform_data pdata; |
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struct armada_37xx_dvfs *dvfs; |
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struct platform_device *pdev; |
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unsigned long freq; |
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unsigned int base_frequency; |
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struct regmap *nb_clk_base, *nb_pm_base, *avs_base; |
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struct device *cpu_dev; |
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int load_lvl, ret; |
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struct clk *clk, *parent; |
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nb_clk_base = |
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syscon_regmap_lookup_by_compatible("marvell,armada-3700-periph-clock-nb"); |
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if (IS_ERR(nb_clk_base)) |
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return -ENODEV; |
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nb_pm_base = |
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syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm"); |
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if (IS_ERR(nb_pm_base)) |
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return -ENODEV; |
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avs_base = |
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syscon_regmap_lookup_by_compatible("marvell,armada-3700-avs"); |
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/* if AVS is not present don't use it but still try to setup dvfs */ |
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if (IS_ERR(avs_base)) { |
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pr_info("Syscon failed for Adapting Voltage Scaling: skip it\n"); |
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avs_base = NULL; |
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} |
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/* Before doing any configuration on the DVFS first, disable it */ |
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armada37xx_cpufreq_disable_dvfs(nb_pm_base); |
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/* |
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* On CPU 0 register the operating points supported (which are |
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* the nominal CPU frequency and full integer divisions of |
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* it). |
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*/ |
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cpu_dev = get_cpu_device(0); |
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if (!cpu_dev) { |
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dev_err(cpu_dev, "Cannot get CPU\n"); |
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return -ENODEV; |
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} |
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clk = clk_get(cpu_dev, 0); |
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if (IS_ERR(clk)) { |
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dev_err(cpu_dev, "Cannot get clock for CPU0\n"); |
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return PTR_ERR(clk); |
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} |
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parent = clk_get_parent(clk); |
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if (IS_ERR(parent)) { |
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dev_err(cpu_dev, "Cannot get parent clock for CPU0\n"); |
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clk_put(clk); |
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return PTR_ERR(parent); |
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} |
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/* Get parent CPU frequency */ |
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base_frequency = clk_get_rate(parent); |
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if (!base_frequency) { |
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dev_err(cpu_dev, "Failed to get parent clock rate for CPU\n"); |
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clk_put(clk); |
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return -EINVAL; |
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} |
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dvfs = armada_37xx_cpu_freq_info_get(base_frequency); |
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if (!dvfs) { |
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clk_put(clk); |
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return -EINVAL; |
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} |
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armada37xx_cpufreq_state = kmalloc(sizeof(*armada37xx_cpufreq_state), |
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GFP_KERNEL); |
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if (!armada37xx_cpufreq_state) { |
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clk_put(clk); |
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return -ENOMEM; |
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} |
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armada37xx_cpufreq_state->regmap = nb_pm_base; |
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armada37xx_cpufreq_avs_configure(avs_base, dvfs); |
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armada37xx_cpufreq_avs_setup(avs_base, dvfs); |
|
|
|
armada37xx_cpufreq_dvfs_setup(nb_pm_base, nb_clk_base, dvfs->divider); |
|
clk_put(clk); |
|
|
|
for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR; |
|
load_lvl++) { |
|
unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000; |
|
freq = base_frequency / dvfs->divider[load_lvl]; |
|
ret = dev_pm_opp_add(cpu_dev, freq, u_volt); |
|
if (ret) |
|
goto remove_opp; |
|
|
|
|
|
} |
|
|
|
/* Now that everything is setup, enable the DVFS at hardware level */ |
|
armada37xx_cpufreq_enable_dvfs(nb_pm_base); |
|
|
|
memset(&pdata, 0, sizeof(pdata)); |
|
pdata.suspend = armada37xx_cpufreq_suspend; |
|
pdata.resume = armada37xx_cpufreq_resume; |
|
|
|
pdev = platform_device_register_data(NULL, "cpufreq-dt", -1, &pdata, |
|
sizeof(pdata)); |
|
ret = PTR_ERR_OR_ZERO(pdev); |
|
if (ret) |
|
goto disable_dvfs; |
|
|
|
armada37xx_cpufreq_state->cpu_dev = cpu_dev; |
|
armada37xx_cpufreq_state->pdev = pdev; |
|
platform_set_drvdata(pdev, dvfs); |
|
return 0; |
|
|
|
disable_dvfs: |
|
armada37xx_cpufreq_disable_dvfs(nb_pm_base); |
|
remove_opp: |
|
/* clean-up the already added opp before leaving */ |
|
while (load_lvl-- > ARMADA_37XX_DVFS_LOAD_0) { |
|
freq = base_frequency / dvfs->divider[load_lvl]; |
|
dev_pm_opp_remove(cpu_dev, freq); |
|
} |
|
|
|
kfree(armada37xx_cpufreq_state); |
|
|
|
return ret; |
|
} |
|
/* late_initcall, to guarantee the driver is loaded after A37xx clock driver */ |
|
late_initcall(armada37xx_cpufreq_driver_init); |
|
|
|
static void __exit armada37xx_cpufreq_driver_exit(void) |
|
{ |
|
struct platform_device *pdev = armada37xx_cpufreq_state->pdev; |
|
struct armada_37xx_dvfs *dvfs = platform_get_drvdata(pdev); |
|
unsigned long freq; |
|
int load_lvl; |
|
|
|
platform_device_unregister(pdev); |
|
|
|
armada37xx_cpufreq_disable_dvfs(armada37xx_cpufreq_state->regmap); |
|
|
|
for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR; load_lvl++) { |
|
freq = dvfs->cpu_freq_max / dvfs->divider[load_lvl]; |
|
dev_pm_opp_remove(armada37xx_cpufreq_state->cpu_dev, freq); |
|
} |
|
|
|
kfree(armada37xx_cpufreq_state); |
|
} |
|
module_exit(armada37xx_cpufreq_driver_exit); |
|
|
|
static const struct of_device_id __maybe_unused armada37xx_cpufreq_of_match[] = { |
|
{ .compatible = "marvell,armada-3700-nb-pm" }, |
|
{ }, |
|
}; |
|
MODULE_DEVICE_TABLE(of, armada37xx_cpufreq_of_match); |
|
|
|
MODULE_AUTHOR("Gregory CLEMENT <[email protected]>"); |
|
MODULE_DESCRIPTION("Armada 37xx cpufreq driver"); |
|
MODULE_LICENSE("GPL");
|
|
|