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719 lines
19 KiB
719 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// |
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// Register map access API - SPI AVMM support |
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// |
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// Copyright (C) 2018-2020 Intel Corporation. All rights reserved. |
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#include <linux/module.h> |
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#include <linux/regmap.h> |
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#include <linux/spi/spi.h> |
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|
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/* |
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* This driver implements the regmap operations for a generic SPI |
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* master to access the registers of the spi slave chip which has an |
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* Avalone bus in it. |
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* |
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* The "SPI slave to Avalon Master Bridge" (spi-avmm) IP should be integrated |
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* in the spi slave chip. The IP acts as a bridge to convert encoded streams of |
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* bytes from the host to the internal register read/write on Avalon bus. In |
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* order to issue register access requests to the slave chip, the host should |
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* send formatted bytes that conform to the transfer protocol. |
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* The transfer protocol contains 3 layers: transaction layer, packet layer |
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* and physical layer. |
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* |
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* Reference Documents could be found at: |
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* https://www.intel.com/content/www/us/en/programmable/documentation/sfo1400787952932.html |
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* |
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* Chapter "SPI Slave/JTAG to Avalon Master Bridge Cores" is a general |
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* introduction to the protocol. |
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* |
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* Chapter "Avalon Packets to Transactions Converter Core" describes |
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* the transaction layer. |
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* |
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* Chapter "Avalon-ST Bytes to Packets and Packets to Bytes Converter Cores" |
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* describes the packet layer. |
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* |
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* Chapter "Avalon-ST Serial Peripheral Interface Core" describes the |
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* physical layer. |
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* |
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* |
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* When host issues a regmap read/write, the driver will transform the request |
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* to byte stream layer by layer. It formats the register addr, value and |
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* length to the transaction layer request, then converts the request to packet |
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* layer bytes stream and then to physical layer bytes stream. Finally the |
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* driver sends the formatted byte stream over SPI bus to the slave chip. |
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* |
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* The spi-avmm IP on the slave chip decodes the byte stream and initiates |
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* register read/write on its internal Avalon bus, and then encodes the |
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* response to byte stream and sends back to host. |
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* |
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* The driver receives the byte stream, reverses the 3 layers transformation, |
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* and finally gets the response value (read out data for register read, |
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* successful written size for register write). |
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*/ |
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#define PKT_SOP 0x7a |
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#define PKT_EOP 0x7b |
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#define PKT_CHANNEL 0x7c |
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#define PKT_ESC 0x7d |
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#define PHY_IDLE 0x4a |
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#define PHY_ESC 0x4d |
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#define TRANS_CODE_WRITE 0x0 |
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#define TRANS_CODE_SEQ_WRITE 0x4 |
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#define TRANS_CODE_READ 0x10 |
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#define TRANS_CODE_SEQ_READ 0x14 |
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#define TRANS_CODE_NO_TRANS 0x7f |
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#define SPI_AVMM_XFER_TIMEOUT (msecs_to_jiffies(200)) |
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/* slave's register addr is 32 bits */ |
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#define SPI_AVMM_REG_SIZE 4UL |
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/* slave's register value is 32 bits */ |
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#define SPI_AVMM_VAL_SIZE 4UL |
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/* |
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* max rx size could be larger. But considering the buffer consuming, |
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* it is proper that we limit 1KB xfer at max. |
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*/ |
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#define MAX_READ_CNT 256UL |
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#define MAX_WRITE_CNT 1UL |
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struct trans_req_header { |
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u8 code; |
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u8 rsvd; |
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__be16 size; |
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__be32 addr; |
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} __packed; |
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struct trans_resp_header { |
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u8 r_code; |
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u8 rsvd; |
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__be16 size; |
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} __packed; |
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#define TRANS_REQ_HD_SIZE (sizeof(struct trans_req_header)) |
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#define TRANS_RESP_HD_SIZE (sizeof(struct trans_resp_header)) |
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/* |
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* In transaction layer, |
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* the write request format is: Transaction request header + data |
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* the read request format is: Transaction request header |
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* the write response format is: Transaction response header |
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* the read response format is: pure data, no Transaction response header |
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*/ |
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#define TRANS_WR_TX_SIZE(n) (TRANS_REQ_HD_SIZE + SPI_AVMM_VAL_SIZE * (n)) |
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#define TRANS_RD_TX_SIZE TRANS_REQ_HD_SIZE |
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#define TRANS_TX_MAX TRANS_WR_TX_SIZE(MAX_WRITE_CNT) |
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#define TRANS_RD_RX_SIZE(n) (SPI_AVMM_VAL_SIZE * (n)) |
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#define TRANS_WR_RX_SIZE TRANS_RESP_HD_SIZE |
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#define TRANS_RX_MAX TRANS_RD_RX_SIZE(MAX_READ_CNT) |
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/* tx & rx share one transaction layer buffer */ |
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#define TRANS_BUF_SIZE ((TRANS_TX_MAX > TRANS_RX_MAX) ? \ |
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TRANS_TX_MAX : TRANS_RX_MAX) |
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/* |
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* In tx phase, the host prepares all the phy layer bytes of a request in the |
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* phy buffer and sends them in a batch. |
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* |
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* The packet layer and physical layer defines several special chars for |
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* various purpose, when a transaction layer byte hits one of these special |
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* chars, it should be escaped. The escape rule is, "Escape char first, |
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* following the byte XOR'ed with 0x20". |
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* |
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* This macro defines the max possible length of the phy data. In the worst |
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* case, all transaction layer bytes need to be escaped (so the data length |
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* doubles), plus 4 special chars (SOP, CHANNEL, CHANNEL_NUM, EOP). Finally |
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* we should make sure the length is aligned to SPI BPW. |
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*/ |
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#define PHY_TX_MAX ALIGN(2 * TRANS_TX_MAX + 4, 4) |
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/* |
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* Unlike tx, phy rx is affected by possible PHY_IDLE bytes from slave, the max |
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* length of the rx bit stream is unpredictable. So the driver reads the words |
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* one by one, and parses each word immediately into transaction layer buffer. |
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* Only one word length of phy buffer is used for rx. |
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*/ |
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#define PHY_BUF_SIZE PHY_TX_MAX |
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/** |
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* struct spi_avmm_bridge - SPI slave to AVMM bus master bridge |
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* |
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* @spi: spi slave associated with this bridge. |
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* @word_len: bytes of word for spi transfer. |
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* @trans_len: length of valid data in trans_buf. |
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* @phy_len: length of valid data in phy_buf. |
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* @trans_buf: the bridge buffer for transaction layer data. |
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* @phy_buf: the bridge buffer for physical layer data. |
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* @swap_words: the word swapping cb for phy data. NULL if not needed. |
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* |
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* As a device's registers are implemented on the AVMM bus address space, it |
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* requires the driver to issue formatted requests to spi slave to AVMM bus |
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* master bridge to perform register access. |
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*/ |
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struct spi_avmm_bridge { |
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struct spi_device *spi; |
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unsigned char word_len; |
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unsigned int trans_len; |
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unsigned int phy_len; |
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/* bridge buffer used in translation between protocol layers */ |
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char trans_buf[TRANS_BUF_SIZE]; |
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char phy_buf[PHY_BUF_SIZE]; |
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void (*swap_words)(char *buf, unsigned int len); |
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}; |
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static void br_swap_words_32(char *buf, unsigned int len) |
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{ |
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u32 *p = (u32 *)buf; |
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unsigned int count; |
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count = len / 4; |
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while (count--) { |
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*p = swab32p(p); |
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p++; |
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} |
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} |
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/* |
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* Format transaction layer data in br->trans_buf according to the register |
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* access request, Store valid transaction layer data length in br->trans_len. |
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*/ |
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static int br_trans_tx_prepare(struct spi_avmm_bridge *br, bool is_read, u32 reg, |
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u32 *wr_val, u32 count) |
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{ |
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struct trans_req_header *header; |
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unsigned int trans_len; |
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u8 code; |
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__le32 *data; |
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int i; |
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if (is_read) { |
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if (count == 1) |
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code = TRANS_CODE_READ; |
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else |
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code = TRANS_CODE_SEQ_READ; |
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} else { |
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if (count == 1) |
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code = TRANS_CODE_WRITE; |
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else |
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code = TRANS_CODE_SEQ_WRITE; |
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} |
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header = (struct trans_req_header *)br->trans_buf; |
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header->code = code; |
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header->rsvd = 0; |
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header->size = cpu_to_be16((u16)count * SPI_AVMM_VAL_SIZE); |
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header->addr = cpu_to_be32(reg); |
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trans_len = TRANS_REQ_HD_SIZE; |
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if (!is_read) { |
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trans_len += SPI_AVMM_VAL_SIZE * count; |
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if (trans_len > sizeof(br->trans_buf)) |
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return -ENOMEM; |
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data = (__le32 *)(br->trans_buf + TRANS_REQ_HD_SIZE); |
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for (i = 0; i < count; i++) |
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*data++ = cpu_to_le32(*wr_val++); |
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} |
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/* Store valid trans data length for next layer */ |
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br->trans_len = trans_len; |
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return 0; |
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} |
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/* |
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* Convert transaction layer data (in br->trans_buf) to phy layer data, store |
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* them in br->phy_buf. Pad the phy_buf aligned with SPI's BPW. Store valid phy |
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* layer data length in br->phy_len. |
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* |
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* phy_buf len should be aligned with SPI's BPW. Spare bytes should be padded |
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* with PHY_IDLE, then the slave will just drop them. |
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* |
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* The driver will not simply pad 4a at the tail. The concern is that driver |
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* will not store MISO data during tx phase, if the driver pads 4a at the tail, |
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* it is possible that if the slave is fast enough to response at the padding |
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* time. As a result these rx bytes are lost. In the following case, 7a,7c,00 |
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* will lost. |
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* MOSI ...|7a|7c|00|10| |00|00|04|02| |4b|7d|5a|7b| |40|4a|4a|4a| |XX|XX|... |
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* MISO ...|4a|4a|4a|4a| |4a|4a|4a|4a| |4a|4a|4a|4a| |4a|7a|7c|00| |78|56|... |
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* |
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* So the driver moves EOP and bytes after EOP to the end of the aligned size, |
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* then fill the hole with PHY_IDLE. As following: |
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* before pad ...|7a|7c|00|10| |00|00|04|02| |4b|7d|5a|7b| |40| |
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* after pad ...|7a|7c|00|10| |00|00|04|02| |4b|7d|5a|4a| |4a|4a|7b|40| |
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* Then if the slave will not get the entire packet before the tx phase is |
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* over, it can't responsed to anything either. |
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*/ |
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static int br_pkt_phy_tx_prepare(struct spi_avmm_bridge *br) |
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{ |
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char *tb, *tb_end, *pb, *pb_limit, *pb_eop = NULL; |
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unsigned int aligned_phy_len, move_size; |
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bool need_esc = false; |
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tb = br->trans_buf; |
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tb_end = tb + br->trans_len; |
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pb = br->phy_buf; |
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pb_limit = pb + ARRAY_SIZE(br->phy_buf); |
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*pb++ = PKT_SOP; |
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/* |
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* The driver doesn't support multiple channels so the channel number |
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* is always 0. |
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*/ |
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*pb++ = PKT_CHANNEL; |
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*pb++ = 0x0; |
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for (; pb < pb_limit && tb < tb_end; pb++) { |
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if (need_esc) { |
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*pb = *tb++ ^ 0x20; |
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need_esc = false; |
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continue; |
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} |
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/* EOP should be inserted before the last valid char */ |
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if (tb == tb_end - 1 && !pb_eop) { |
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*pb = PKT_EOP; |
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pb_eop = pb; |
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continue; |
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} |
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/* |
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* insert an ESCAPE char if the data value equals any special |
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* char. |
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*/ |
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switch (*tb) { |
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case PKT_SOP: |
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case PKT_EOP: |
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case PKT_CHANNEL: |
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case PKT_ESC: |
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*pb = PKT_ESC; |
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need_esc = true; |
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break; |
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case PHY_IDLE: |
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case PHY_ESC: |
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*pb = PHY_ESC; |
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need_esc = true; |
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break; |
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default: |
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*pb = *tb++; |
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break; |
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} |
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} |
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/* The phy buffer is used out but transaction layer data remains */ |
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if (tb < tb_end) |
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return -ENOMEM; |
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/* Store valid phy data length for spi transfer */ |
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br->phy_len = pb - br->phy_buf; |
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if (br->word_len == 1) |
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return 0; |
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/* Do phy buf padding if word_len > 1 byte. */ |
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aligned_phy_len = ALIGN(br->phy_len, br->word_len); |
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if (aligned_phy_len > sizeof(br->phy_buf)) |
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return -ENOMEM; |
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if (aligned_phy_len == br->phy_len) |
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return 0; |
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/* move EOP and bytes after EOP to the end of aligned size */ |
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move_size = pb - pb_eop; |
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memmove(&br->phy_buf[aligned_phy_len - move_size], pb_eop, move_size); |
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/* fill the hole with PHY_IDLEs */ |
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memset(pb_eop, PHY_IDLE, aligned_phy_len - br->phy_len); |
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/* update the phy data length */ |
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br->phy_len = aligned_phy_len; |
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return 0; |
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} |
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/* |
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* In tx phase, the slave only returns PHY_IDLE (0x4a). So the driver will |
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* ignore rx in tx phase. |
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*/ |
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static int br_do_tx(struct spi_avmm_bridge *br) |
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{ |
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/* reorder words for spi transfer */ |
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if (br->swap_words) |
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br->swap_words(br->phy_buf, br->phy_len); |
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/* send all data in phy_buf */ |
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return spi_write(br->spi, br->phy_buf, br->phy_len); |
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} |
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/* |
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* This function read the rx byte stream from SPI word by word and convert |
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* them to transaction layer data in br->trans_buf. It also stores the length |
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* of rx transaction layer data in br->trans_len |
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* |
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* The slave may send an unknown number of PHY_IDLEs in rx phase, so we cannot |
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* prepare a fixed length buffer to receive all of the rx data in a batch. We |
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* have to read word by word and convert them to transaction layer data at |
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* once. |
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*/ |
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static int br_do_rx_and_pkt_phy_parse(struct spi_avmm_bridge *br) |
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{ |
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bool eop_found = false, channel_found = false, esc_found = false; |
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bool valid_word = false, last_try = false; |
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struct device *dev = &br->spi->dev; |
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char *pb, *tb_limit, *tb = NULL; |
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unsigned long poll_timeout; |
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int ret, i; |
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tb_limit = br->trans_buf + ARRAY_SIZE(br->trans_buf); |
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pb = br->phy_buf; |
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poll_timeout = jiffies + SPI_AVMM_XFER_TIMEOUT; |
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while (tb < tb_limit) { |
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ret = spi_read(br->spi, pb, br->word_len); |
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if (ret) |
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return ret; |
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/* reorder the word back */ |
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if (br->swap_words) |
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br->swap_words(pb, br->word_len); |
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valid_word = false; |
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for (i = 0; i < br->word_len; i++) { |
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/* drop everything before first SOP */ |
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if (!tb && pb[i] != PKT_SOP) |
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continue; |
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/* drop PHY_IDLE */ |
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if (pb[i] == PHY_IDLE) |
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continue; |
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valid_word = true; |
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/* |
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* We don't support multiple channels, so error out if |
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* a non-zero channel number is found. |
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*/ |
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if (channel_found) { |
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if (pb[i] != 0) { |
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dev_err(dev, "%s channel num != 0\n", |
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__func__); |
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return -EFAULT; |
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} |
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channel_found = false; |
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continue; |
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} |
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switch (pb[i]) { |
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case PKT_SOP: |
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/* |
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* reset the parsing if a second SOP appears. |
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*/ |
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tb = br->trans_buf; |
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eop_found = false; |
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channel_found = false; |
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esc_found = false; |
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break; |
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case PKT_EOP: |
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/* |
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* No special char is expected after ESC char. |
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* No special char (except ESC & PHY_IDLE) is |
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* expected after EOP char. |
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* |
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* The special chars are all dropped. |
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*/ |
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if (esc_found || eop_found) |
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return -EFAULT; |
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|
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eop_found = true; |
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break; |
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case PKT_CHANNEL: |
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if (esc_found || eop_found) |
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return -EFAULT; |
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|
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channel_found = true; |
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break; |
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case PKT_ESC: |
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case PHY_ESC: |
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if (esc_found) |
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return -EFAULT; |
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|
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esc_found = true; |
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break; |
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default: |
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/* Record the normal byte in trans_buf. */ |
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if (esc_found) { |
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*tb++ = pb[i] ^ 0x20; |
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esc_found = false; |
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} else { |
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*tb++ = pb[i]; |
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} |
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|
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/* |
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* We get the last normal byte after EOP, it is |
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* time we finish. Normally the function should |
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* return here. |
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*/ |
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if (eop_found) { |
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br->trans_len = tb - br->trans_buf; |
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return 0; |
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} |
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} |
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} |
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|
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if (valid_word) { |
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/* update poll timeout when we get valid word */ |
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poll_timeout = jiffies + SPI_AVMM_XFER_TIMEOUT; |
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last_try = false; |
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} else { |
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/* |
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* We timeout when rx keeps invalid for some time. But |
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* it is possible we are scheduled out for long time |
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* after a spi_read. So when we are scheduled in, a SW |
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* timeout happens. But actually HW may have worked fine and |
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* has been ready long time ago. So we need to do an extra |
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* read, if we get a valid word then we could continue rx, |
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* otherwise real a HW issue happens. |
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*/ |
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if (last_try) |
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return -ETIMEDOUT; |
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|
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if (time_after(jiffies, poll_timeout)) |
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last_try = true; |
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} |
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} |
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|
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/* |
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* We have used out all transfer layer buffer but cannot find the end |
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* of the byte stream. |
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*/ |
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dev_err(dev, "%s transfer buffer is full but rx doesn't end\n", |
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__func__); |
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|
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return -EFAULT; |
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} |
|
|
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/* |
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* For read transactions, the avmm bus will directly return register values |
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* without transaction response header. |
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*/ |
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static int br_rd_trans_rx_parse(struct spi_avmm_bridge *br, |
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u32 *val, unsigned int expected_count) |
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{ |
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unsigned int i, trans_len = br->trans_len; |
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__le32 *data; |
|
|
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if (expected_count * SPI_AVMM_VAL_SIZE != trans_len) |
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return -EFAULT; |
|
|
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data = (__le32 *)br->trans_buf; |
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for (i = 0; i < expected_count; i++) |
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*val++ = le32_to_cpu(*data++); |
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|
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return 0; |
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} |
|
|
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/* |
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* For write transactions, the slave will return a transaction response |
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* header. |
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*/ |
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static int br_wr_trans_rx_parse(struct spi_avmm_bridge *br, |
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unsigned int expected_count) |
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{ |
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unsigned int trans_len = br->trans_len; |
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struct trans_resp_header *resp; |
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u8 code; |
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u16 val_len; |
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|
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if (trans_len != TRANS_RESP_HD_SIZE) |
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return -EFAULT; |
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|
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resp = (struct trans_resp_header *)br->trans_buf; |
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|
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code = resp->r_code ^ 0x80; |
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val_len = be16_to_cpu(resp->size); |
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if (!val_len || val_len != expected_count * SPI_AVMM_VAL_SIZE) |
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return -EFAULT; |
|
|
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/* error out if the trans code doesn't align with the val size */ |
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if ((val_len == SPI_AVMM_VAL_SIZE && code != TRANS_CODE_WRITE) || |
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(val_len > SPI_AVMM_VAL_SIZE && code != TRANS_CODE_SEQ_WRITE)) |
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return -EFAULT; |
|
|
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return 0; |
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} |
|
|
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static int do_reg_access(void *context, bool is_read, unsigned int reg, |
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unsigned int *value, unsigned int count) |
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{ |
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struct spi_avmm_bridge *br = context; |
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int ret; |
|
|
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/* invalidate bridge buffers first */ |
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br->trans_len = 0; |
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br->phy_len = 0; |
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|
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ret = br_trans_tx_prepare(br, is_read, reg, value, count); |
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if (ret) |
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return ret; |
|
|
|
ret = br_pkt_phy_tx_prepare(br); |
|
if (ret) |
|
return ret; |
|
|
|
ret = br_do_tx(br); |
|
if (ret) |
|
return ret; |
|
|
|
ret = br_do_rx_and_pkt_phy_parse(br); |
|
if (ret) |
|
return ret; |
|
|
|
if (is_read) |
|
return br_rd_trans_rx_parse(br, value, count); |
|
else |
|
return br_wr_trans_rx_parse(br, count); |
|
} |
|
|
|
static int regmap_spi_avmm_gather_write(void *context, |
|
const void *reg_buf, size_t reg_len, |
|
const void *val_buf, size_t val_len) |
|
{ |
|
if (reg_len != SPI_AVMM_REG_SIZE) |
|
return -EINVAL; |
|
|
|
if (!IS_ALIGNED(val_len, SPI_AVMM_VAL_SIZE)) |
|
return -EINVAL; |
|
|
|
return do_reg_access(context, false, *(u32 *)reg_buf, (u32 *)val_buf, |
|
val_len / SPI_AVMM_VAL_SIZE); |
|
} |
|
|
|
static int regmap_spi_avmm_write(void *context, const void *data, size_t bytes) |
|
{ |
|
if (bytes < SPI_AVMM_REG_SIZE + SPI_AVMM_VAL_SIZE) |
|
return -EINVAL; |
|
|
|
return regmap_spi_avmm_gather_write(context, data, SPI_AVMM_REG_SIZE, |
|
data + SPI_AVMM_REG_SIZE, |
|
bytes - SPI_AVMM_REG_SIZE); |
|
} |
|
|
|
static int regmap_spi_avmm_read(void *context, |
|
const void *reg_buf, size_t reg_len, |
|
void *val_buf, size_t val_len) |
|
{ |
|
if (reg_len != SPI_AVMM_REG_SIZE) |
|
return -EINVAL; |
|
|
|
if (!IS_ALIGNED(val_len, SPI_AVMM_VAL_SIZE)) |
|
return -EINVAL; |
|
|
|
return do_reg_access(context, true, *(u32 *)reg_buf, val_buf, |
|
(val_len / SPI_AVMM_VAL_SIZE)); |
|
} |
|
|
|
static struct spi_avmm_bridge * |
|
spi_avmm_bridge_ctx_gen(struct spi_device *spi) |
|
{ |
|
struct spi_avmm_bridge *br; |
|
|
|
if (!spi) |
|
return ERR_PTR(-ENODEV); |
|
|
|
/* Only support BPW == 8 or 32 now. Try 32 BPW first. */ |
|
spi->mode = SPI_MODE_1; |
|
spi->bits_per_word = 32; |
|
if (spi_setup(spi)) { |
|
spi->bits_per_word = 8; |
|
if (spi_setup(spi)) |
|
return ERR_PTR(-EINVAL); |
|
} |
|
|
|
br = kzalloc(sizeof(*br), GFP_KERNEL); |
|
if (!br) |
|
return ERR_PTR(-ENOMEM); |
|
|
|
br->spi = spi; |
|
br->word_len = spi->bits_per_word / 8; |
|
if (br->word_len == 4) { |
|
/* |
|
* The protocol requires little endian byte order but MSB |
|
* first. So driver needs to swap the byte order word by word |
|
* if word length > 1. |
|
*/ |
|
br->swap_words = br_swap_words_32; |
|
} |
|
|
|
return br; |
|
} |
|
|
|
static void spi_avmm_bridge_ctx_free(void *context) |
|
{ |
|
kfree(context); |
|
} |
|
|
|
static const struct regmap_bus regmap_spi_avmm_bus = { |
|
.write = regmap_spi_avmm_write, |
|
.gather_write = regmap_spi_avmm_gather_write, |
|
.read = regmap_spi_avmm_read, |
|
.reg_format_endian_default = REGMAP_ENDIAN_NATIVE, |
|
.val_format_endian_default = REGMAP_ENDIAN_NATIVE, |
|
.max_raw_read = SPI_AVMM_VAL_SIZE * MAX_READ_CNT, |
|
.max_raw_write = SPI_AVMM_VAL_SIZE * MAX_WRITE_CNT, |
|
.free_context = spi_avmm_bridge_ctx_free, |
|
}; |
|
|
|
struct regmap *__regmap_init_spi_avmm(struct spi_device *spi, |
|
const struct regmap_config *config, |
|
struct lock_class_key *lock_key, |
|
const char *lock_name) |
|
{ |
|
struct spi_avmm_bridge *bridge; |
|
struct regmap *map; |
|
|
|
bridge = spi_avmm_bridge_ctx_gen(spi); |
|
if (IS_ERR(bridge)) |
|
return ERR_CAST(bridge); |
|
|
|
map = __regmap_init(&spi->dev, ®map_spi_avmm_bus, |
|
bridge, config, lock_key, lock_name); |
|
if (IS_ERR(map)) { |
|
spi_avmm_bridge_ctx_free(bridge); |
|
return ERR_CAST(map); |
|
} |
|
|
|
return map; |
|
} |
|
EXPORT_SYMBOL_GPL(__regmap_init_spi_avmm); |
|
|
|
struct regmap *__devm_regmap_init_spi_avmm(struct spi_device *spi, |
|
const struct regmap_config *config, |
|
struct lock_class_key *lock_key, |
|
const char *lock_name) |
|
{ |
|
struct spi_avmm_bridge *bridge; |
|
struct regmap *map; |
|
|
|
bridge = spi_avmm_bridge_ctx_gen(spi); |
|
if (IS_ERR(bridge)) |
|
return ERR_CAST(bridge); |
|
|
|
map = __devm_regmap_init(&spi->dev, ®map_spi_avmm_bus, |
|
bridge, config, lock_key, lock_name); |
|
if (IS_ERR(map)) { |
|
spi_avmm_bridge_ctx_free(bridge); |
|
return ERR_CAST(map); |
|
} |
|
|
|
return map; |
|
} |
|
EXPORT_SYMBOL_GPL(__devm_regmap_init_spi_avmm); |
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|