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116 lines
3.3 KiB
116 lines
3.3 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* sbi.h: SBI (Sbus Interface on sun4d) definitions |
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* |
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* Copyright (C) 1997 Jakub Jelinek <[email protected]> |
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*/ |
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#ifndef _SPARC_SBI_H |
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#define _SPARC_SBI_H |
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#include <asm/obio.h> |
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/* SBI */ |
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struct sbi_regs { |
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/* 0x0000 */ u32 cid; /* Component ID */ |
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/* 0x0004 */ u32 ctl; /* Control */ |
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/* 0x0008 */ u32 status; /* Status */ |
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u32 _unused1; |
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/* 0x0010 */ u32 cfg0; /* Slot0 config reg */ |
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/* 0x0014 */ u32 cfg1; /* Slot1 config reg */ |
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/* 0x0018 */ u32 cfg2; /* Slot2 config reg */ |
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/* 0x001c */ u32 cfg3; /* Slot3 config reg */ |
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/* 0x0020 */ u32 stb0; /* Streaming buf control for slot 0 */ |
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/* 0x0024 */ u32 stb1; /* Streaming buf control for slot 1 */ |
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/* 0x0028 */ u32 stb2; /* Streaming buf control for slot 2 */ |
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/* 0x002c */ u32 stb3; /* Streaming buf control for slot 3 */ |
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/* 0x0030 */ u32 intr_state; /* Interrupt state */ |
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/* 0x0034 */ u32 intr_tid; /* Interrupt target ID */ |
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/* 0x0038 */ u32 intr_diag; /* Interrupt diagnostics */ |
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}; |
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#define SBI_CID 0x02800000 |
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#define SBI_CTL 0x02800004 |
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#define SBI_STATUS 0x02800008 |
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#define SBI_CFG0 0x02800010 |
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#define SBI_CFG1 0x02800014 |
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#define SBI_CFG2 0x02800018 |
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#define SBI_CFG3 0x0280001c |
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#define SBI_STB0 0x02800020 |
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#define SBI_STB1 0x02800024 |
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#define SBI_STB2 0x02800028 |
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#define SBI_STB3 0x0280002c |
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#define SBI_INTR_STATE 0x02800030 |
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#define SBI_INTR_TID 0x02800034 |
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#define SBI_INTR_DIAG 0x02800038 |
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/* Burst bits for 8, 16, 32, 64 are in cfgX registers at bits 2, 3, 4, 5 respectively */ |
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#define SBI_CFG_BURST_MASK 0x0000001e |
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/* How to make devid from sbi no */ |
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#define SBI2DEVID(sbino) ((sbino<<4)|2) |
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/* intr_state has 4 bits for slots 0 .. 3 and these bits are repeated for each sbus irq level |
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* |
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* +-------+-------+-------+-------+-------+-------+-------+-------+ |
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* SBUS IRQ LEVEL | 7 | 6 | 5 | 4 | 3 | 2 | 1 | | |
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ Reser | |
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* SLOT # |3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0| ved | |
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------+ |
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* Bits 31 27 23 19 15 11 7 3 0 |
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*/ |
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#ifndef __ASSEMBLY__ |
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static inline int acquire_sbi(int devid, int mask) |
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{ |
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__asm__ __volatile__ ("swapa [%2] %3, %0" : |
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"=r" (mask) : |
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"0" (mask), |
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"r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE), |
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"i" (ASI_M_CTL)); |
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return mask; |
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} |
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static inline void release_sbi(int devid, int mask) |
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{ |
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__asm__ __volatile__ ("sta %0, [%1] %2" : : |
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"r" (mask), |
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"r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE), |
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"i" (ASI_M_CTL)); |
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} |
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static inline void set_sbi_tid(int devid, int targetid) |
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{ |
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__asm__ __volatile__ ("sta %0, [%1] %2" : : |
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"r" (targetid), |
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"r" (ECSR_DEV_BASE(devid) | SBI_INTR_TID), |
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"i" (ASI_M_CTL)); |
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} |
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static inline int get_sbi_ctl(int devid, int cfgno) |
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{ |
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int cfg; |
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__asm__ __volatile__ ("lda [%1] %2, %0" : |
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"=r" (cfg) : |
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"r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)), |
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"i" (ASI_M_CTL)); |
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return cfg; |
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} |
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static inline void set_sbi_ctl(int devid, int cfgno, int cfg) |
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{ |
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__asm__ __volatile__ ("sta %0, [%1] %2" : : |
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"r" (cfg), |
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"r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)), |
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"i" (ASI_M_CTL)); |
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} |
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#endif /* !__ASSEMBLY__ */ |
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#endif /* !(_SPARC_SBI_H) */
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