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324 lines
8.9 KiB
324 lines
8.9 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* OMAP Multi-Channel Buffered Serial Port |
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* |
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* Contact: Jarkko Nikula <[email protected]> |
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* Peter Ujfalusi <[email protected]> |
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*/ |
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#ifndef __OMAP_MCBSP_PRIV_H__ |
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#define __OMAP_MCBSP_PRIV_H__ |
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#include <linux/platform_data/asoc-ti-mcbsp.h> |
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#ifdef CONFIG_ARCH_OMAP1 |
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#define mcbsp_omap1() 1 |
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#else |
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#define mcbsp_omap1() 0 |
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#endif |
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/* McBSP register numbers. Register address offset = num * reg_step */ |
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enum { |
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/* Common registers */ |
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OMAP_MCBSP_REG_SPCR2 = 4, |
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OMAP_MCBSP_REG_SPCR1, |
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OMAP_MCBSP_REG_RCR2, |
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OMAP_MCBSP_REG_RCR1, |
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OMAP_MCBSP_REG_XCR2, |
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OMAP_MCBSP_REG_XCR1, |
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OMAP_MCBSP_REG_SRGR2, |
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OMAP_MCBSP_REG_SRGR1, |
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OMAP_MCBSP_REG_MCR2, |
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OMAP_MCBSP_REG_MCR1, |
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OMAP_MCBSP_REG_RCERA, |
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OMAP_MCBSP_REG_RCERB, |
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OMAP_MCBSP_REG_XCERA, |
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OMAP_MCBSP_REG_XCERB, |
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OMAP_MCBSP_REG_PCR0, |
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OMAP_MCBSP_REG_RCERC, |
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OMAP_MCBSP_REG_RCERD, |
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OMAP_MCBSP_REG_XCERC, |
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OMAP_MCBSP_REG_XCERD, |
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OMAP_MCBSP_REG_RCERE, |
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OMAP_MCBSP_REG_RCERF, |
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OMAP_MCBSP_REG_XCERE, |
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OMAP_MCBSP_REG_XCERF, |
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OMAP_MCBSP_REG_RCERG, |
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OMAP_MCBSP_REG_RCERH, |
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OMAP_MCBSP_REG_XCERG, |
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OMAP_MCBSP_REG_XCERH, |
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/* OMAP1-OMAP2420 registers */ |
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OMAP_MCBSP_REG_DRR2 = 0, |
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OMAP_MCBSP_REG_DRR1, |
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OMAP_MCBSP_REG_DXR2, |
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OMAP_MCBSP_REG_DXR1, |
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/* OMAP2430 and onwards */ |
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OMAP_MCBSP_REG_DRR = 0, |
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OMAP_MCBSP_REG_DXR = 2, |
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OMAP_MCBSP_REG_SYSCON = 35, |
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OMAP_MCBSP_REG_THRSH2, |
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OMAP_MCBSP_REG_THRSH1, |
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OMAP_MCBSP_REG_IRQST = 40, |
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OMAP_MCBSP_REG_IRQEN, |
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OMAP_MCBSP_REG_WAKEUPEN, |
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OMAP_MCBSP_REG_XCCR, |
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OMAP_MCBSP_REG_RCCR, |
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OMAP_MCBSP_REG_XBUFFSTAT, |
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OMAP_MCBSP_REG_RBUFFSTAT, |
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OMAP_MCBSP_REG_SSELCR, |
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}; |
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/************************** McBSP SPCR1 bit definitions ***********************/ |
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#define RRST BIT(0) |
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#define RRDY BIT(1) |
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#define RFULL BIT(2) |
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#define RSYNC_ERR BIT(3) |
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#define RINTM(value) (((value) & 0x3) << 4) /* bits 4:5 */ |
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#define ABIS BIT(6) |
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#define DXENA BIT(7) |
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#define CLKSTP(value) (((value) & 0x3) << 11) /* bits 11:12 */ |
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#define RJUST(value) (((value) & 0x3) << 13) /* bits 13:14 */ |
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#define ALB BIT(15) |
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#define DLB BIT(15) |
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/************************** McBSP SPCR2 bit definitions ***********************/ |
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#define XRST BIT(0) |
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#define XRDY BIT(1) |
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#define XEMPTY BIT(2) |
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#define XSYNC_ERR BIT(3) |
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#define XINTM(value) (((value) & 0x3) << 4) /* bits 4:5 */ |
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#define GRST BIT(6) |
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#define FRST BIT(7) |
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#define SOFT BIT(8) |
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#define FREE BIT(9) |
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/************************** McBSP PCR bit definitions *************************/ |
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#define CLKRP BIT(0) |
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#define CLKXP BIT(1) |
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#define FSRP BIT(2) |
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#define FSXP BIT(3) |
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#define DR_STAT BIT(4) |
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#define DX_STAT BIT(5) |
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#define CLKS_STAT BIT(6) |
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#define SCLKME BIT(7) |
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#define CLKRM BIT(8) |
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#define CLKXM BIT(9) |
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#define FSRM BIT(10) |
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#define FSXM BIT(11) |
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#define RIOEN BIT(12) |
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#define XIOEN BIT(13) |
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#define IDLE_EN BIT(14) |
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/************************** McBSP RCR1 bit definitions ************************/ |
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#define RWDLEN1(value) (((value) & 0x7) << 5) /* Bits 5:7 */ |
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#define RFRLEN1(value) (((value) & 0x7f) << 8) /* Bits 8:14 */ |
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/************************** McBSP XCR1 bit definitions ************************/ |
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#define XWDLEN1(value) (((value) & 0x7) << 5) /* Bits 5:7 */ |
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#define XFRLEN1(value) (((value) & 0x7f) << 8) /* Bits 8:14 */ |
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/*************************** McBSP RCR2 bit definitions ***********************/ |
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#define RDATDLY(value) ((value) & 0x3) /* Bits 0:1 */ |
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#define RFIG BIT(2) |
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#define RCOMPAND(value) (((value) & 0x3) << 3) /* Bits 3:4 */ |
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#define RWDLEN2(value) (((value) & 0x7) << 5) /* Bits 5:7 */ |
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#define RFRLEN2(value) (((value) & 0x7f) << 8) /* Bits 8:14 */ |
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#define RPHASE BIT(15) |
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/*************************** McBSP XCR2 bit definitions ***********************/ |
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#define XDATDLY(value) ((value) & 0x3) /* Bits 0:1 */ |
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#define XFIG BIT(2) |
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#define XCOMPAND(value) (((value) & 0x3) << 3) /* Bits 3:4 */ |
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#define XWDLEN2(value) (((value) & 0x7) << 5) /* Bits 5:7 */ |
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#define XFRLEN2(value) (((value) & 0x7f) << 8) /* Bits 8:14 */ |
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#define XPHASE BIT(15) |
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/************************* McBSP SRGR1 bit definitions ************************/ |
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#define CLKGDV(value) ((value) & 0x7f) /* Bits 0:7 */ |
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#define FWID(value) (((value) & 0xff) << 8) /* Bits 8:15 */ |
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/************************* McBSP SRGR2 bit definitions ************************/ |
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#define FPER(value) ((value) & 0x0fff) /* Bits 0:11 */ |
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#define FSGM BIT(12) |
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#define CLKSM BIT(13) |
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#define CLKSP BIT(14) |
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#define GSYNC BIT(15) |
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/************************* McBSP MCR1 bit definitions *************************/ |
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#define RMCM BIT(0) |
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#define RCBLK(value) (((value) & 0x7) << 2) /* Bits 2:4 */ |
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#define RPABLK(value) (((value) & 0x3) << 5) /* Bits 5:6 */ |
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#define RPBBLK(value) (((value) & 0x3) << 7) /* Bits 7:8 */ |
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/************************* McBSP MCR2 bit definitions *************************/ |
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#define XMCM(value) ((value) & 0x3) /* Bits 0:1 */ |
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#define XCBLK(value) (((value) & 0x7) << 2) /* Bits 2:4 */ |
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#define XPABLK(value) (((value) & 0x3) << 5) /* Bits 5:6 */ |
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#define XPBBLK(value) (((value) & 0x3) << 7) /* Bits 7:8 */ |
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/*********************** McBSP XCCR bit definitions *************************/ |
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#define XDISABLE BIT(0) |
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#define XDMAEN BIT(3) |
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#define DILB BIT(5) |
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#define XFULL_CYCLE BIT(11) |
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#define DXENDLY(value) (((value) & 0x3) << 12) /* Bits 12:13 */ |
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#define PPCONNECT BIT(14) |
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#define EXTCLKGATE BIT(15) |
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/********************** McBSP RCCR bit definitions *************************/ |
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#define RDISABLE BIT(0) |
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#define RDMAEN BIT(3) |
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#define RFULL_CYCLE BIT(11) |
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/********************** McBSP SYSCONFIG bit definitions ********************/ |
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#define SOFTRST BIT(1) |
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#define ENAWAKEUP BIT(2) |
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#define SIDLEMODE(value) (((value) & 0x3) << 3) |
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#define CLOCKACTIVITY(value) (((value) & 0x3) << 8) |
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/********************** McBSP DMA operating modes **************************/ |
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#define MCBSP_DMA_MODE_ELEMENT 0 |
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#define MCBSP_DMA_MODE_THRESHOLD 1 |
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/********************** McBSP WAKEUPEN/IRQST/IRQEN bit definitions *********/ |
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#define RSYNCERREN BIT(0) |
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#define RFSREN BIT(1) |
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#define REOFEN BIT(2) |
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#define RRDYEN BIT(3) |
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#define RUNDFLEN BIT(4) |
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#define ROVFLEN BIT(5) |
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#define XSYNCERREN BIT(7) |
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#define XFSXEN BIT(8) |
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#define XEOFEN BIT(9) |
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#define XRDYEN BIT(10) |
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#define XUNDFLEN BIT(11) |
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#define XOVFLEN BIT(12) |
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#define XEMPTYEOFEN BIT(14) |
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/* Clock signal muxing options */ |
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#define CLKR_SRC_CLKR 0 /* CLKR signal is from the CLKR pin */ |
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#define CLKR_SRC_CLKX 1 /* CLKR signal is from the CLKX pin */ |
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#define FSR_SRC_FSR 2 /* FSR signal is from the FSR pin */ |
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#define FSR_SRC_FSX 3 /* FSR signal is from the FSX pin */ |
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/* McBSP functional clock sources */ |
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#define MCBSP_CLKS_PRCM_SRC 0 |
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#define MCBSP_CLKS_PAD_SRC 1 |
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/* we don't do multichannel for now */ |
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struct omap_mcbsp_reg_cfg { |
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u16 spcr2; |
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u16 spcr1; |
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u16 rcr2; |
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u16 rcr1; |
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u16 xcr2; |
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u16 xcr1; |
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u16 srgr2; |
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u16 srgr1; |
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u16 mcr2; |
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u16 mcr1; |
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u16 pcr0; |
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u16 rcerc; |
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u16 rcerd; |
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u16 xcerc; |
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u16 xcerd; |
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u16 rcere; |
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u16 rcerf; |
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u16 xcere; |
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u16 xcerf; |
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u16 rcerg; |
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u16 rcerh; |
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u16 xcerg; |
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u16 xcerh; |
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u16 xccr; |
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u16 rccr; |
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}; |
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struct omap_mcbsp_st_data; |
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struct omap_mcbsp { |
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struct device *dev; |
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struct clk *fclk; |
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spinlock_t lock; |
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unsigned long phys_base; |
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unsigned long phys_dma_base; |
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void __iomem *io_base; |
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u8 id; |
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/* |
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* Flags indicating is the bus already activated and configured by |
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* another substream |
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*/ |
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int active; |
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int configured; |
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u8 free; |
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int irq; |
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int rx_irq; |
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int tx_irq; |
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/* Protect the field .free, while checking if the mcbsp is in use */ |
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struct omap_mcbsp_platform_data *pdata; |
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struct omap_mcbsp_st_data *st_data; |
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struct omap_mcbsp_reg_cfg cfg_regs; |
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struct snd_dmaengine_dai_dma_data dma_data[2]; |
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unsigned int dma_req[2]; |
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int dma_op_mode; |
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u16 max_tx_thres; |
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u16 max_rx_thres; |
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void *reg_cache; |
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int reg_cache_size; |
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unsigned int fmt; |
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unsigned int in_freq; |
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unsigned int latency[2]; |
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int clk_div; |
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int wlen; |
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struct pm_qos_request pm_qos_req; |
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}; |
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static inline void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) |
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{ |
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void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step; |
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if (mcbsp->pdata->reg_size == 2) { |
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((u16 *)mcbsp->reg_cache)[reg] = (u16)val; |
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writew_relaxed((u16)val, addr); |
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} else { |
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((u32 *)mcbsp->reg_cache)[reg] = val; |
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writel_relaxed(val, addr); |
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} |
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} |
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static inline int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, |
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bool from_cache) |
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{ |
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void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step; |
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if (mcbsp->pdata->reg_size == 2) { |
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return !from_cache ? readw_relaxed(addr) : |
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((u16 *)mcbsp->reg_cache)[reg]; |
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} else { |
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return !from_cache ? readl_relaxed(addr) : |
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((u32 *)mcbsp->reg_cache)[reg]; |
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} |
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} |
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#define MCBSP_READ(mcbsp, reg) \ |
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omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0) |
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#define MCBSP_WRITE(mcbsp, reg, val) \ |
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omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val) |
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#define MCBSP_READ_CACHE(mcbsp, reg) \ |
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omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1) |
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/* Sidetone specific API */ |
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int omap_mcbsp_st_init(struct platform_device *pdev); |
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void omap_mcbsp_st_cleanup(struct platform_device *pdev); |
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int omap_mcbsp_st_start(struct omap_mcbsp *mcbsp); |
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int omap_mcbsp_st_stop(struct omap_mcbsp *mcbsp); |
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#endif /* __OMAP_MCBSP_PRIV_H__ */
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