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614 lines
17 KiB
614 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// |
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// mt8183-afe-clk.c -- Mediatek 8183 afe clock ctrl |
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// |
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// Copyright (c) 2018 MediaTek Inc. |
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// Author: KaiChieh Chuang <[email protected]> |
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#include <linux/clk.h> |
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#include "mt8183-afe-common.h" |
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#include "mt8183-afe-clk.h" |
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#include "mt8183-reg.h" |
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enum { |
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CLK_AFE = 0, |
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CLK_TML, |
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CLK_APLL22M, |
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CLK_APLL24M, |
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CLK_APLL1_TUNER, |
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CLK_APLL2_TUNER, |
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CLK_I2S1_BCLK_SW, |
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CLK_I2S2_BCLK_SW, |
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CLK_I2S3_BCLK_SW, |
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CLK_I2S4_BCLK_SW, |
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CLK_INFRA_SYS_AUDIO, |
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CLK_MUX_AUDIO, |
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CLK_MUX_AUDIOINTBUS, |
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CLK_TOP_SYSPLL_D2_D4, |
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/* apll related mux */ |
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CLK_TOP_MUX_AUD_1, |
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CLK_TOP_APLL1_CK, |
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CLK_TOP_MUX_AUD_2, |
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CLK_TOP_APLL2_CK, |
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CLK_TOP_MUX_AUD_ENG1, |
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CLK_TOP_APLL1_D8, |
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CLK_TOP_MUX_AUD_ENG2, |
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CLK_TOP_APLL2_D8, |
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CLK_TOP_I2S0_M_SEL, |
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CLK_TOP_I2S1_M_SEL, |
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CLK_TOP_I2S2_M_SEL, |
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CLK_TOP_I2S3_M_SEL, |
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CLK_TOP_I2S4_M_SEL, |
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CLK_TOP_I2S5_M_SEL, |
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CLK_TOP_APLL12_DIV0, |
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CLK_TOP_APLL12_DIV1, |
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CLK_TOP_APLL12_DIV2, |
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CLK_TOP_APLL12_DIV3, |
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CLK_TOP_APLL12_DIV4, |
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CLK_TOP_APLL12_DIVB, |
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CLK_CLK26M, |
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CLK_NUM |
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}; |
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static const char *aud_clks[CLK_NUM] = { |
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[CLK_AFE] = "aud_afe_clk", |
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[CLK_TML] = "aud_tml_clk", |
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[CLK_APLL22M] = "aud_apll22m_clk", |
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[CLK_APLL24M] = "aud_apll24m_clk", |
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[CLK_APLL1_TUNER] = "aud_apll1_tuner_clk", |
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[CLK_APLL2_TUNER] = "aud_apll2_tuner_clk", |
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[CLK_I2S1_BCLK_SW] = "aud_i2s1_bclk_sw", |
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[CLK_I2S2_BCLK_SW] = "aud_i2s2_bclk_sw", |
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[CLK_I2S3_BCLK_SW] = "aud_i2s3_bclk_sw", |
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[CLK_I2S4_BCLK_SW] = "aud_i2s4_bclk_sw", |
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[CLK_INFRA_SYS_AUDIO] = "aud_infra_clk", |
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[CLK_MUX_AUDIO] = "top_mux_audio", |
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[CLK_MUX_AUDIOINTBUS] = "top_mux_aud_intbus", |
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[CLK_TOP_SYSPLL_D2_D4] = "top_syspll_d2_d4", |
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[CLK_TOP_MUX_AUD_1] = "top_mux_aud_1", |
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[CLK_TOP_APLL1_CK] = "top_apll1_ck", |
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[CLK_TOP_MUX_AUD_2] = "top_mux_aud_2", |
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[CLK_TOP_APLL2_CK] = "top_apll2_ck", |
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[CLK_TOP_MUX_AUD_ENG1] = "top_mux_aud_eng1", |
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[CLK_TOP_APLL1_D8] = "top_apll1_d8", |
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[CLK_TOP_MUX_AUD_ENG2] = "top_mux_aud_eng2", |
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[CLK_TOP_APLL2_D8] = "top_apll2_d8", |
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[CLK_TOP_I2S0_M_SEL] = "top_i2s0_m_sel", |
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[CLK_TOP_I2S1_M_SEL] = "top_i2s1_m_sel", |
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[CLK_TOP_I2S2_M_SEL] = "top_i2s2_m_sel", |
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[CLK_TOP_I2S3_M_SEL] = "top_i2s3_m_sel", |
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[CLK_TOP_I2S4_M_SEL] = "top_i2s4_m_sel", |
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[CLK_TOP_I2S5_M_SEL] = "top_i2s5_m_sel", |
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[CLK_TOP_APLL12_DIV0] = "top_apll12_div0", |
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[CLK_TOP_APLL12_DIV1] = "top_apll12_div1", |
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[CLK_TOP_APLL12_DIV2] = "top_apll12_div2", |
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[CLK_TOP_APLL12_DIV3] = "top_apll12_div3", |
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[CLK_TOP_APLL12_DIV4] = "top_apll12_div4", |
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[CLK_TOP_APLL12_DIVB] = "top_apll12_divb", |
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[CLK_CLK26M] = "top_clk26m_clk", |
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}; |
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int mt8183_init_clock(struct mtk_base_afe *afe) |
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{ |
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struct mt8183_afe_private *afe_priv = afe->platform_priv; |
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int i; |
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afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk), |
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GFP_KERNEL); |
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if (!afe_priv->clk) |
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return -ENOMEM; |
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for (i = 0; i < CLK_NUM; i++) { |
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afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]); |
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if (IS_ERR(afe_priv->clk[i])) { |
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dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n", |
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__func__, aud_clks[i], |
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PTR_ERR(afe_priv->clk[i])); |
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return PTR_ERR(afe_priv->clk[i]); |
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} |
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} |
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return 0; |
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} |
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int mt8183_afe_enable_clock(struct mtk_base_afe *afe) |
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{ |
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struct mt8183_afe_private *afe_priv = afe->platform_priv; |
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int ret; |
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ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]); |
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if (ret) { |
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dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n", |
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__func__, aud_clks[CLK_INFRA_SYS_AUDIO], ret); |
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goto CLK_INFRA_SYS_AUDIO_ERR; |
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} |
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ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]); |
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if (ret) { |
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dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n", |
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__func__, aud_clks[CLK_MUX_AUDIO], ret); |
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goto CLK_MUX_AUDIO_ERR; |
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} |
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ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO], |
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afe_priv->clk[CLK_CLK26M]); |
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if (ret) { |
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dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n", |
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__func__, aud_clks[CLK_MUX_AUDIO], |
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aud_clks[CLK_CLK26M], ret); |
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goto CLK_MUX_AUDIO_ERR; |
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} |
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ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); |
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if (ret) { |
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dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n", |
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__func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret); |
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goto CLK_MUX_AUDIO_INTBUS_ERR; |
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} |
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ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], |
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afe_priv->clk[CLK_TOP_SYSPLL_D2_D4]); |
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if (ret) { |
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dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n", |
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__func__, aud_clks[CLK_MUX_AUDIOINTBUS], |
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aud_clks[CLK_TOP_SYSPLL_D2_D4], ret); |
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goto CLK_MUX_AUDIO_INTBUS_ERR; |
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} |
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ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]); |
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if (ret) { |
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dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", |
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__func__, aud_clks[CLK_AFE], ret); |
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goto CLK_AFE_ERR; |
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} |
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ret = clk_prepare_enable(afe_priv->clk[CLK_I2S1_BCLK_SW]); |
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if (ret) { |
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dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", |
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__func__, aud_clks[CLK_I2S1_BCLK_SW], ret); |
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goto CLK_I2S1_BCLK_SW_ERR; |
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} |
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ret = clk_prepare_enable(afe_priv->clk[CLK_I2S2_BCLK_SW]); |
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if (ret) { |
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dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", |
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__func__, aud_clks[CLK_I2S2_BCLK_SW], ret); |
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goto CLK_I2S2_BCLK_SW_ERR; |
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} |
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ret = clk_prepare_enable(afe_priv->clk[CLK_I2S3_BCLK_SW]); |
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if (ret) { |
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dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", |
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__func__, aud_clks[CLK_I2S3_BCLK_SW], ret); |
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goto CLK_I2S3_BCLK_SW_ERR; |
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} |
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ret = clk_prepare_enable(afe_priv->clk[CLK_I2S4_BCLK_SW]); |
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if (ret) { |
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dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", |
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__func__, aud_clks[CLK_I2S4_BCLK_SW], ret); |
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goto CLK_I2S4_BCLK_SW_ERR; |
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} |
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return 0; |
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CLK_I2S4_BCLK_SW_ERR: |
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clk_disable_unprepare(afe_priv->clk[CLK_I2S3_BCLK_SW]); |
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CLK_I2S3_BCLK_SW_ERR: |
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clk_disable_unprepare(afe_priv->clk[CLK_I2S2_BCLK_SW]); |
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CLK_I2S2_BCLK_SW_ERR: |
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clk_disable_unprepare(afe_priv->clk[CLK_I2S1_BCLK_SW]); |
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CLK_I2S1_BCLK_SW_ERR: |
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clk_disable_unprepare(afe_priv->clk[CLK_AFE]); |
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CLK_AFE_ERR: |
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clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); |
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CLK_MUX_AUDIO_INTBUS_ERR: |
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clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]); |
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CLK_MUX_AUDIO_ERR: |
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clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]); |
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CLK_INFRA_SYS_AUDIO_ERR: |
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return ret; |
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} |
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int mt8183_afe_disable_clock(struct mtk_base_afe *afe) |
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{ |
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struct mt8183_afe_private *afe_priv = afe->platform_priv; |
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clk_disable_unprepare(afe_priv->clk[CLK_I2S4_BCLK_SW]); |
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clk_disable_unprepare(afe_priv->clk[CLK_I2S3_BCLK_SW]); |
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clk_disable_unprepare(afe_priv->clk[CLK_I2S2_BCLK_SW]); |
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clk_disable_unprepare(afe_priv->clk[CLK_I2S1_BCLK_SW]); |
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clk_disable_unprepare(afe_priv->clk[CLK_AFE]); |
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clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); |
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clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]); |
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clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]); |
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return 0; |
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} |
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/* apll */ |
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static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable) |
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{ |
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struct mt8183_afe_private *afe_priv = afe->platform_priv; |
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int ret; |
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if (enable) { |
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ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]); |
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if (ret) { |
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dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", |
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__func__, aud_clks[CLK_TOP_MUX_AUD_1], ret); |
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goto ERR_ENABLE_CLK_TOP_MUX_AUD_1; |
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} |
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ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], |
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afe_priv->clk[CLK_TOP_APLL1_CK]); |
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if (ret) { |
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dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", |
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__func__, aud_clks[CLK_TOP_MUX_AUD_1], |
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aud_clks[CLK_TOP_APLL1_CK], ret); |
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goto ERR_SELECT_CLK_TOP_MUX_AUD_1; |
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} |
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/* 180.6336 / 8 = 22.5792MHz */ |
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ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]); |
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if (ret) { |
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dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", |
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__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], ret); |
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goto ERR_ENABLE_CLK_TOP_MUX_AUD_ENG1; |
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} |
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ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], |
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afe_priv->clk[CLK_TOP_APLL1_D8]); |
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if (ret) { |
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dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", |
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__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], |
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aud_clks[CLK_TOP_APLL1_D8], ret); |
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goto ERR_SELECT_CLK_TOP_MUX_AUD_ENG1; |
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} |
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} else { |
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ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], |
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afe_priv->clk[CLK_CLK26M]); |
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if (ret) { |
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dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", |
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__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], |
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aud_clks[CLK_CLK26M], ret); |
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goto EXIT; |
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} |
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clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]); |
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ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], |
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afe_priv->clk[CLK_CLK26M]); |
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if (ret) { |
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dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", |
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__func__, aud_clks[CLK_TOP_MUX_AUD_1], |
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aud_clks[CLK_CLK26M], ret); |
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goto EXIT; |
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} |
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clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]); |
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} |
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return 0; |
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ERR_SELECT_CLK_TOP_MUX_AUD_ENG1: |
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clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], |
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afe_priv->clk[CLK_CLK26M]); |
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clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]); |
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ERR_ENABLE_CLK_TOP_MUX_AUD_ENG1: |
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ERR_SELECT_CLK_TOP_MUX_AUD_1: |
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clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], |
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afe_priv->clk[CLK_CLK26M]); |
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clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]); |
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ERR_ENABLE_CLK_TOP_MUX_AUD_1: |
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EXIT: |
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return ret; |
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} |
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static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable) |
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{ |
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struct mt8183_afe_private *afe_priv = afe->platform_priv; |
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int ret; |
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if (enable) { |
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ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]); |
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if (ret) { |
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dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", |
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__func__, aud_clks[CLK_TOP_MUX_AUD_2], ret); |
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goto ERR_ENABLE_CLK_TOP_MUX_AUD_2; |
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} |
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ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], |
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afe_priv->clk[CLK_TOP_APLL2_CK]); |
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if (ret) { |
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dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", |
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__func__, aud_clks[CLK_TOP_MUX_AUD_2], |
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aud_clks[CLK_TOP_APLL2_CK], ret); |
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goto ERR_SELECT_CLK_TOP_MUX_AUD_2; |
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} |
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/* 196.608 / 8 = 24.576MHz */ |
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ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]); |
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if (ret) { |
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dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", |
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__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], ret); |
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goto ERR_ENABLE_CLK_TOP_MUX_AUD_ENG2; |
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} |
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ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], |
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afe_priv->clk[CLK_TOP_APLL2_D8]); |
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if (ret) { |
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dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", |
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__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], |
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aud_clks[CLK_TOP_APLL2_D8], ret); |
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goto ERR_SELECT_CLK_TOP_MUX_AUD_ENG2; |
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} |
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} else { |
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ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], |
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afe_priv->clk[CLK_CLK26M]); |
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if (ret) { |
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dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", |
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__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], |
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aud_clks[CLK_CLK26M], ret); |
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goto EXIT; |
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} |
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clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]); |
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ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], |
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afe_priv->clk[CLK_CLK26M]); |
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if (ret) { |
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dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", |
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__func__, aud_clks[CLK_TOP_MUX_AUD_2], |
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aud_clks[CLK_CLK26M], ret); |
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goto EXIT; |
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} |
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clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]); |
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} |
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return 0; |
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ERR_SELECT_CLK_TOP_MUX_AUD_ENG2: |
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clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], |
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afe_priv->clk[CLK_CLK26M]); |
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clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]); |
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ERR_ENABLE_CLK_TOP_MUX_AUD_ENG2: |
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ERR_SELECT_CLK_TOP_MUX_AUD_2: |
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clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], |
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afe_priv->clk[CLK_CLK26M]); |
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clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]); |
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ERR_ENABLE_CLK_TOP_MUX_AUD_2: |
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EXIT: |
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return ret; |
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} |
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int mt8183_apll1_enable(struct mtk_base_afe *afe) |
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{ |
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struct mt8183_afe_private *afe_priv = afe->platform_priv; |
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int ret; |
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/* setting for APLL */ |
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apll1_mux_setting(afe, true); |
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ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]); |
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if (ret) { |
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dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", |
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__func__, aud_clks[CLK_APLL22M], ret); |
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goto ERR_CLK_APLL22M; |
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} |
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ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]); |
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if (ret) { |
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dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", |
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__func__, aud_clks[CLK_APLL1_TUNER], ret); |
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goto ERR_CLK_APLL1_TUNER; |
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} |
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regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, |
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0x0000FFF7, 0x00000832); |
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regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1); |
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regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, |
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AFE_22M_ON_MASK_SFT, |
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0x1 << AFE_22M_ON_SFT); |
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return 0; |
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ERR_CLK_APLL1_TUNER: |
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clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]); |
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ERR_CLK_APLL22M: |
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return ret; |
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} |
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void mt8183_apll1_disable(struct mtk_base_afe *afe) |
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{ |
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struct mt8183_afe_private *afe_priv = afe->platform_priv; |
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regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, |
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AFE_22M_ON_MASK_SFT, |
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0x0 << AFE_22M_ON_SFT); |
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regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x0); |
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clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]); |
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clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]); |
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apll1_mux_setting(afe, false); |
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} |
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int mt8183_apll2_enable(struct mtk_base_afe *afe) |
|
{ |
|
struct mt8183_afe_private *afe_priv = afe->platform_priv; |
|
int ret; |
|
|
|
/* setting for APLL */ |
|
apll2_mux_setting(afe, true); |
|
|
|
ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]); |
|
if (ret) { |
|
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", |
|
__func__, aud_clks[CLK_APLL24M], ret); |
|
goto ERR_CLK_APLL24M; |
|
} |
|
|
|
ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]); |
|
if (ret) { |
|
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", |
|
__func__, aud_clks[CLK_APLL2_TUNER], ret); |
|
goto ERR_CLK_APLL2_TUNER; |
|
} |
|
|
|
regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, |
|
0x0000FFF7, 0x00000634); |
|
regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1); |
|
|
|
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, |
|
AFE_24M_ON_MASK_SFT, |
|
0x1 << AFE_24M_ON_SFT); |
|
|
|
return 0; |
|
|
|
ERR_CLK_APLL2_TUNER: |
|
clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]); |
|
ERR_CLK_APLL24M: |
|
return ret; |
|
} |
|
|
|
void mt8183_apll2_disable(struct mtk_base_afe *afe) |
|
{ |
|
struct mt8183_afe_private *afe_priv = afe->platform_priv; |
|
|
|
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, |
|
AFE_24M_ON_MASK_SFT, |
|
0x0 << AFE_24M_ON_SFT); |
|
|
|
regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x0); |
|
|
|
clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]); |
|
clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]); |
|
|
|
apll2_mux_setting(afe, false); |
|
} |
|
|
|
int mt8183_get_apll_rate(struct mtk_base_afe *afe, int apll) |
|
{ |
|
return (apll == MT8183_APLL1) ? 180633600 : 196608000; |
|
} |
|
|
|
int mt8183_get_apll_by_rate(struct mtk_base_afe *afe, int rate) |
|
{ |
|
return ((rate % 8000) == 0) ? MT8183_APLL2 : MT8183_APLL1; |
|
} |
|
|
|
int mt8183_get_apll_by_name(struct mtk_base_afe *afe, const char *name) |
|
{ |
|
if (strcmp(name, APLL1_W_NAME) == 0) |
|
return MT8183_APLL1; |
|
else |
|
return MT8183_APLL2; |
|
} |
|
|
|
/* mck */ |
|
struct mt8183_mck_div { |
|
int m_sel_id; |
|
int div_clk_id; |
|
}; |
|
|
|
static const struct mt8183_mck_div mck_div[MT8183_MCK_NUM] = { |
|
[MT8183_I2S0_MCK] = { |
|
.m_sel_id = CLK_TOP_I2S0_M_SEL, |
|
.div_clk_id = CLK_TOP_APLL12_DIV0, |
|
}, |
|
[MT8183_I2S1_MCK] = { |
|
.m_sel_id = CLK_TOP_I2S1_M_SEL, |
|
.div_clk_id = CLK_TOP_APLL12_DIV1, |
|
}, |
|
[MT8183_I2S2_MCK] = { |
|
.m_sel_id = CLK_TOP_I2S2_M_SEL, |
|
.div_clk_id = CLK_TOP_APLL12_DIV2, |
|
}, |
|
[MT8183_I2S3_MCK] = { |
|
.m_sel_id = CLK_TOP_I2S3_M_SEL, |
|
.div_clk_id = CLK_TOP_APLL12_DIV3, |
|
}, |
|
[MT8183_I2S4_MCK] = { |
|
.m_sel_id = CLK_TOP_I2S4_M_SEL, |
|
.div_clk_id = CLK_TOP_APLL12_DIV4, |
|
}, |
|
[MT8183_I2S4_BCK] = { |
|
.m_sel_id = -1, |
|
.div_clk_id = CLK_TOP_APLL12_DIVB, |
|
}, |
|
[MT8183_I2S5_MCK] = { |
|
.m_sel_id = -1, |
|
.div_clk_id = -1, |
|
}, |
|
}; |
|
|
|
int mt8183_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate) |
|
{ |
|
struct mt8183_afe_private *afe_priv = afe->platform_priv; |
|
int apll = mt8183_get_apll_by_rate(afe, rate); |
|
int apll_clk_id = apll == MT8183_APLL1 ? |
|
CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2; |
|
int m_sel_id = mck_div[mck_id].m_sel_id; |
|
int div_clk_id = mck_div[mck_id].div_clk_id; |
|
int ret; |
|
|
|
/* i2s5 mck not support */ |
|
if (mck_id == MT8183_I2S5_MCK) |
|
return 0; |
|
|
|
/* select apll */ |
|
if (m_sel_id >= 0) { |
|
ret = clk_prepare_enable(afe_priv->clk[m_sel_id]); |
|
if (ret) { |
|
dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n", |
|
__func__, aud_clks[m_sel_id], ret); |
|
goto ERR_ENABLE_MCLK; |
|
} |
|
ret = clk_set_parent(afe_priv->clk[m_sel_id], |
|
afe_priv->clk[apll_clk_id]); |
|
if (ret) { |
|
dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n", |
|
__func__, aud_clks[m_sel_id], |
|
aud_clks[apll_clk_id], ret); |
|
goto ERR_SELECT_MCLK; |
|
} |
|
} |
|
|
|
/* enable div, set rate */ |
|
ret = clk_prepare_enable(afe_priv->clk[div_clk_id]); |
|
if (ret) { |
|
dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n", |
|
__func__, aud_clks[div_clk_id], ret); |
|
goto ERR_ENABLE_MCLK_DIV; |
|
} |
|
ret = clk_set_rate(afe_priv->clk[div_clk_id], rate); |
|
if (ret) { |
|
dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n", |
|
__func__, aud_clks[div_clk_id], |
|
rate, ret); |
|
goto ERR_SET_MCLK_RATE; |
|
} |
|
|
|
return 0; |
|
|
|
ERR_SET_MCLK_RATE: |
|
clk_disable_unprepare(afe_priv->clk[div_clk_id]); |
|
ERR_ENABLE_MCLK_DIV: |
|
ERR_SELECT_MCLK: |
|
if (m_sel_id >= 0) |
|
clk_disable_unprepare(afe_priv->clk[m_sel_id]); |
|
ERR_ENABLE_MCLK: |
|
return ret; |
|
} |
|
|
|
void mt8183_mck_disable(struct mtk_base_afe *afe, int mck_id) |
|
{ |
|
struct mt8183_afe_private *afe_priv = afe->platform_priv; |
|
int m_sel_id = mck_div[mck_id].m_sel_id; |
|
int div_clk_id = mck_div[mck_id].div_clk_id; |
|
|
|
/* i2s5 mck not support */ |
|
if (mck_id == MT8183_I2S5_MCK) |
|
return; |
|
|
|
clk_disable_unprepare(afe_priv->clk[div_clk_id]); |
|
if (m_sel_id >= 0) |
|
clk_disable_unprepare(afe_priv->clk[m_sel_id]); |
|
}
|
|
|