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1192 lines
28 KiB
1192 lines
28 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* skl.c - Implementation of ASoC Intel SKL HD Audio driver |
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* |
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* Copyright (C) 2014-2015 Intel Corp |
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* Author: Jeeja KP <[email protected]> |
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* |
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* Derived mostly from Intel HDA driver with following copyrights: |
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* Copyright (c) 2004 Takashi Iwai <[email protected]> |
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* PeiSen Hou <[email protected]> |
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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* |
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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*/ |
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|
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/platform_device.h> |
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#include <linux/firmware.h> |
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#include <linux/delay.h> |
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#include <sound/pcm.h> |
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#include <sound/soc-acpi.h> |
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#include <sound/soc-acpi-intel-match.h> |
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#include <sound/hda_register.h> |
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#include <sound/hdaudio.h> |
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#include <sound/hda_i915.h> |
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#include <sound/hda_codec.h> |
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#include <sound/intel-nhlt.h> |
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#include <sound/intel-dsp-config.h> |
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#include "skl.h" |
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#include "skl-sst-dsp.h" |
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#include "skl-sst-ipc.h" |
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|
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#if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) |
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#include "../../../soc/codecs/hdac_hda.h" |
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#endif |
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static int skl_pci_binding; |
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module_param_named(pci_binding, skl_pci_binding, int, 0444); |
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MODULE_PARM_DESC(pci_binding, "PCI binding (0=auto, 1=only legacy, 2=only asoc"); |
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|
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/* |
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* initialize the PCI registers |
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*/ |
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static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg, |
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unsigned char mask, unsigned char val) |
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{ |
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unsigned char data; |
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|
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pci_read_config_byte(pci, reg, &data); |
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data &= ~mask; |
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data |= (val & mask); |
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pci_write_config_byte(pci, reg, data); |
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} |
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static void skl_init_pci(struct skl_dev *skl) |
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{ |
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struct hdac_bus *bus = skl_to_bus(skl); |
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|
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/* |
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* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) |
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* TCSEL == Traffic Class Select Register, which sets PCI express QOS |
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* Ensuring these bits are 0 clears playback static on some HD Audio |
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* codecs. |
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* The PCI register TCSEL is defined in the Intel manuals. |
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*/ |
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dev_dbg(bus->dev, "Clearing TCSEL\n"); |
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skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0); |
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} |
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|
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static void update_pci_dword(struct pci_dev *pci, |
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unsigned int reg, u32 mask, u32 val) |
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{ |
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u32 data = 0; |
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pci_read_config_dword(pci, reg, &data); |
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data &= ~mask; |
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data |= (val & mask); |
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pci_write_config_dword(pci, reg, data); |
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} |
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|
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/* |
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* skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits |
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* |
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* @dev: device pointer |
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* @enable: enable/disable flag |
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*/ |
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static void skl_enable_miscbdcge(struct device *dev, bool enable) |
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{ |
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struct pci_dev *pci = to_pci_dev(dev); |
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u32 val; |
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val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0; |
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update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); |
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} |
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/** |
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* skl_clock_power_gating: Enable/Disable clock and power gating |
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* |
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* @dev: Device pointer |
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* @enable: Enable/Disable flag |
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*/ |
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static void skl_clock_power_gating(struct device *dev, bool enable) |
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{ |
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struct pci_dev *pci = to_pci_dev(dev); |
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struct hdac_bus *bus = pci_get_drvdata(pci); |
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u32 val; |
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|
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/* Update PDCGE bit of CGCTL register */ |
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val = enable ? AZX_CGCTL_ADSPDCGE : 0; |
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update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val); |
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|
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/* Update L1SEN bit of EM2 register */ |
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val = enable ? AZX_REG_VS_EM2_L1SEN : 0; |
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snd_hdac_chip_updatel(bus, VS_EM2, AZX_REG_VS_EM2_L1SEN, val); |
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|
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/* Update ADSPPGD bit of PGCTL register */ |
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val = enable ? 0 : AZX_PGCTL_ADSPPGD; |
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update_pci_dword(pci, AZX_PCIREG_PGCTL, AZX_PGCTL_ADSPPGD, val); |
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} |
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/* |
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* While performing reset, controller may not come back properly causing |
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* issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset |
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* (init chip) and then again set CGCTL.MISCBDCGE to 1 |
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*/ |
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static int skl_init_chip(struct hdac_bus *bus, bool full_reset) |
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{ |
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struct hdac_ext_link *hlink; |
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int ret; |
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snd_hdac_set_codec_wakeup(bus, true); |
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skl_enable_miscbdcge(bus->dev, false); |
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ret = snd_hdac_bus_init_chip(bus, full_reset); |
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|
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/* Reset stream-to-link mapping */ |
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list_for_each_entry(hlink, &bus->hlink_list, list) |
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writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV); |
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skl_enable_miscbdcge(bus->dev, true); |
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snd_hdac_set_codec_wakeup(bus, false); |
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return ret; |
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} |
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void skl_update_d0i3c(struct device *dev, bool enable) |
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{ |
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struct pci_dev *pci = to_pci_dev(dev); |
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struct hdac_bus *bus = pci_get_drvdata(pci); |
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u8 reg; |
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int timeout = 50; |
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reg = snd_hdac_chip_readb(bus, VS_D0I3C); |
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/* Do not write to D0I3C until command in progress bit is cleared */ |
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while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { |
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udelay(10); |
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reg = snd_hdac_chip_readb(bus, VS_D0I3C); |
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} |
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/* Highly unlikely. But if it happens, flag error explicitly */ |
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if (!timeout) { |
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dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n"); |
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return; |
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} |
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if (enable) |
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reg = reg | AZX_REG_VS_D0I3C_I3; |
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else |
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reg = reg & (~AZX_REG_VS_D0I3C_I3); |
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snd_hdac_chip_writeb(bus, VS_D0I3C, reg); |
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timeout = 50; |
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/* Wait for cmd in progress to be cleared before exiting the function */ |
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reg = snd_hdac_chip_readb(bus, VS_D0I3C); |
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while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { |
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udelay(10); |
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reg = snd_hdac_chip_readb(bus, VS_D0I3C); |
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} |
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/* Highly unlikely. But if it happens, flag error explicitly */ |
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if (!timeout) { |
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dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n"); |
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return; |
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} |
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dev_dbg(bus->dev, "D0I3C register = 0x%x\n", |
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snd_hdac_chip_readb(bus, VS_D0I3C)); |
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} |
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/** |
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* skl_dum_set - set DUM bit in EM2 register |
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* @bus: HD-audio core bus |
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* |
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* Addresses incorrect position reporting for capture streams. |
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* Used on device power up. |
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*/ |
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static void skl_dum_set(struct hdac_bus *bus) |
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{ |
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/* For the DUM bit to be set, CRST needs to be out of reset state */ |
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if (!(snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET)) { |
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skl_enable_miscbdcge(bus->dev, false); |
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snd_hdac_bus_exit_link_reset(bus); |
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skl_enable_miscbdcge(bus->dev, true); |
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} |
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snd_hdac_chip_updatel(bus, VS_EM2, AZX_VS_EM2_DUM, AZX_VS_EM2_DUM); |
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} |
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/* called from IRQ */ |
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static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr) |
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{ |
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snd_pcm_period_elapsed(hstr->substream); |
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} |
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static irqreturn_t skl_interrupt(int irq, void *dev_id) |
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{ |
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struct hdac_bus *bus = dev_id; |
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u32 status; |
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if (!pm_runtime_active(bus->dev)) |
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return IRQ_NONE; |
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spin_lock(&bus->reg_lock); |
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status = snd_hdac_chip_readl(bus, INTSTS); |
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if (status == 0 || status == 0xffffffff) { |
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spin_unlock(&bus->reg_lock); |
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return IRQ_NONE; |
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} |
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/* clear rirb int */ |
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status = snd_hdac_chip_readb(bus, RIRBSTS); |
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if (status & RIRB_INT_MASK) { |
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if (status & RIRB_INT_RESPONSE) |
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snd_hdac_bus_update_rirb(bus); |
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snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); |
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} |
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spin_unlock(&bus->reg_lock); |
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return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED; |
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} |
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static irqreturn_t skl_threaded_handler(int irq, void *dev_id) |
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{ |
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struct hdac_bus *bus = dev_id; |
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u32 status; |
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status = snd_hdac_chip_readl(bus, INTSTS); |
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snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update); |
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return IRQ_HANDLED; |
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} |
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static int skl_acquire_irq(struct hdac_bus *bus, int do_disconnect) |
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{ |
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struct skl_dev *skl = bus_to_skl(bus); |
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int ret; |
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ret = request_threaded_irq(skl->pci->irq, skl_interrupt, |
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skl_threaded_handler, |
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IRQF_SHARED, |
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KBUILD_MODNAME, bus); |
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if (ret) { |
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dev_err(bus->dev, |
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"unable to grab IRQ %d, disabling device\n", |
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skl->pci->irq); |
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return ret; |
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} |
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bus->irq = skl->pci->irq; |
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pci_intx(skl->pci, 1); |
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return 0; |
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} |
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static int skl_suspend_late(struct device *dev) |
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{ |
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struct pci_dev *pci = to_pci_dev(dev); |
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struct hdac_bus *bus = pci_get_drvdata(pci); |
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struct skl_dev *skl = bus_to_skl(bus); |
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return skl_suspend_late_dsp(skl); |
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} |
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#ifdef CONFIG_PM |
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static int _skl_suspend(struct hdac_bus *bus) |
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{ |
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struct skl_dev *skl = bus_to_skl(bus); |
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struct pci_dev *pci = to_pci_dev(bus->dev); |
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int ret; |
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snd_hdac_ext_bus_link_power_down_all(bus); |
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ret = skl_suspend_dsp(skl); |
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if (ret < 0) |
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return ret; |
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snd_hdac_bus_stop_chip(bus); |
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update_pci_dword(pci, AZX_PCIREG_PGCTL, |
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AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK); |
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skl_enable_miscbdcge(bus->dev, false); |
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snd_hdac_bus_enter_link_reset(bus); |
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skl_enable_miscbdcge(bus->dev, true); |
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skl_cleanup_resources(skl); |
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return 0; |
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} |
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static int _skl_resume(struct hdac_bus *bus) |
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{ |
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struct skl_dev *skl = bus_to_skl(bus); |
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skl_init_pci(skl); |
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skl_dum_set(bus); |
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skl_init_chip(bus, true); |
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return skl_resume_dsp(skl); |
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} |
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#endif |
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#ifdef CONFIG_PM_SLEEP |
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/* |
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* power management |
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*/ |
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static int skl_suspend(struct device *dev) |
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{ |
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struct pci_dev *pci = to_pci_dev(dev); |
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struct hdac_bus *bus = pci_get_drvdata(pci); |
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struct skl_dev *skl = bus_to_skl(bus); |
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int ret; |
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|
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/* |
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* Do not suspend if streams which are marked ignore suspend are |
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* running, we need to save the state for these and continue |
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*/ |
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if (skl->supend_active) { |
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/* turn off the links and stop the CORB/RIRB DMA if it is On */ |
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snd_hdac_ext_bus_link_power_down_all(bus); |
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if (bus->cmd_dma_state) |
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snd_hdac_bus_stop_cmd_io(bus); |
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enable_irq_wake(bus->irq); |
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pci_save_state(pci); |
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} else { |
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ret = _skl_suspend(bus); |
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if (ret < 0) |
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return ret; |
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skl->fw_loaded = false; |
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} |
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|
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return 0; |
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} |
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static int skl_resume(struct device *dev) |
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{ |
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struct pci_dev *pci = to_pci_dev(dev); |
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struct hdac_bus *bus = pci_get_drvdata(pci); |
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struct skl_dev *skl = bus_to_skl(bus); |
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struct hdac_ext_link *hlink; |
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int ret; |
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/* |
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* resume only when we are not in suspend active, otherwise need to |
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* restore the device |
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*/ |
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if (skl->supend_active) { |
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pci_restore_state(pci); |
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snd_hdac_ext_bus_link_power_up_all(bus); |
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disable_irq_wake(bus->irq); |
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/* |
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* turn On the links which are On before active suspend |
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* and start the CORB/RIRB DMA if On before |
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* active suspend. |
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*/ |
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list_for_each_entry(hlink, &bus->hlink_list, list) { |
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if (hlink->ref_count) |
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snd_hdac_ext_bus_link_power_up(hlink); |
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} |
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ret = 0; |
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if (bus->cmd_dma_state) |
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snd_hdac_bus_init_cmd_io(bus); |
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} else { |
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ret = _skl_resume(bus); |
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|
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/* turn off the links which are off before suspend */ |
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list_for_each_entry(hlink, &bus->hlink_list, list) { |
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if (!hlink->ref_count) |
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snd_hdac_ext_bus_link_power_down(hlink); |
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} |
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if (!bus->cmd_dma_state) |
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snd_hdac_bus_stop_cmd_io(bus); |
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} |
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return ret; |
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} |
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#endif /* CONFIG_PM_SLEEP */ |
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#ifdef CONFIG_PM |
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static int skl_runtime_suspend(struct device *dev) |
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{ |
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struct pci_dev *pci = to_pci_dev(dev); |
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struct hdac_bus *bus = pci_get_drvdata(pci); |
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dev_dbg(bus->dev, "in %s\n", __func__); |
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return _skl_suspend(bus); |
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} |
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static int skl_runtime_resume(struct device *dev) |
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{ |
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struct pci_dev *pci = to_pci_dev(dev); |
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struct hdac_bus *bus = pci_get_drvdata(pci); |
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dev_dbg(bus->dev, "in %s\n", __func__); |
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return _skl_resume(bus); |
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} |
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#endif /* CONFIG_PM */ |
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static const struct dev_pm_ops skl_pm = { |
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SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume) |
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SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL) |
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.suspend_late = skl_suspend_late, |
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}; |
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|
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/* |
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* destructor |
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*/ |
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static int skl_free(struct hdac_bus *bus) |
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{ |
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struct skl_dev *skl = bus_to_skl(bus); |
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|
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skl->init_done = 0; /* to be sure */ |
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snd_hdac_ext_stop_streams(bus); |
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|
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if (bus->irq >= 0) |
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free_irq(bus->irq, (void *)bus); |
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snd_hdac_bus_free_stream_pages(bus); |
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snd_hdac_stream_free_all(bus); |
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snd_hdac_link_free_all(bus); |
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|
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if (bus->remap_addr) |
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iounmap(bus->remap_addr); |
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|
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pci_release_regions(skl->pci); |
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pci_disable_device(skl->pci); |
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snd_hdac_ext_bus_exit(bus); |
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|
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if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { |
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snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); |
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snd_hdac_i915_exit(bus); |
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} |
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|
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return 0; |
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} |
|
|
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/* |
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* For each ssp there are 3 clocks (mclk/sclk/sclkfs). |
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* e.g. for ssp0, clocks will be named as |
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* "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs" |
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* So for skl+, there are 6 ssps, so 18 clocks will be created. |
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*/ |
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static struct skl_ssp_clk skl_ssp_clks[] = { |
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{.name = "ssp0_mclk"}, {.name = "ssp1_mclk"}, {.name = "ssp2_mclk"}, |
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{.name = "ssp3_mclk"}, {.name = "ssp4_mclk"}, {.name = "ssp5_mclk"}, |
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{.name = "ssp0_sclk"}, {.name = "ssp1_sclk"}, {.name = "ssp2_sclk"}, |
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{.name = "ssp3_sclk"}, {.name = "ssp4_sclk"}, {.name = "ssp5_sclk"}, |
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{.name = "ssp0_sclkfs"}, {.name = "ssp1_sclkfs"}, |
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{.name = "ssp2_sclkfs"}, |
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{.name = "ssp3_sclkfs"}, {.name = "ssp4_sclkfs"}, |
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{.name = "ssp5_sclkfs"}, |
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}; |
|
|
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static struct snd_soc_acpi_mach *skl_find_hda_machine(struct skl_dev *skl, |
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struct snd_soc_acpi_mach *machines) |
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{ |
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struct snd_soc_acpi_mach *mach; |
|
|
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/* point to common table */ |
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mach = snd_soc_acpi_intel_hda_machines; |
|
|
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/* all entries in the machine table use the same firmware */ |
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mach->fw_filename = machines->fw_filename; |
|
|
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return mach; |
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} |
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|
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static int skl_find_machine(struct skl_dev *skl, void *driver_data) |
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{ |
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struct hdac_bus *bus = skl_to_bus(skl); |
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struct snd_soc_acpi_mach *mach = driver_data; |
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struct skl_machine_pdata *pdata; |
|
|
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mach = snd_soc_acpi_find_machine(mach); |
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if (!mach) { |
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dev_dbg(bus->dev, "No matching I2S machine driver found\n"); |
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mach = skl_find_hda_machine(skl, driver_data); |
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if (!mach) { |
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dev_err(bus->dev, "No matching machine driver found\n"); |
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return -ENODEV; |
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} |
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} |
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|
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skl->mach = mach; |
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skl->fw_name = mach->fw_filename; |
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pdata = mach->pdata; |
|
|
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if (pdata) { |
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skl->use_tplg_pcm = pdata->use_tplg_pcm; |
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mach->mach_params.dmic_num = |
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intel_nhlt_get_dmic_geo(&skl->pci->dev, |
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skl->nhlt); |
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} |
|
|
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return 0; |
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} |
|
|
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static int skl_machine_device_register(struct skl_dev *skl) |
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{ |
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struct snd_soc_acpi_mach *mach = skl->mach; |
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struct hdac_bus *bus = skl_to_bus(skl); |
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struct platform_device *pdev; |
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int ret; |
|
|
|
pdev = platform_device_alloc(mach->drv_name, -1); |
|
if (pdev == NULL) { |
|
dev_err(bus->dev, "platform device alloc failed\n"); |
|
return -EIO; |
|
} |
|
|
|
mach->mach_params.platform = dev_name(bus->dev); |
|
mach->mach_params.codec_mask = bus->codec_mask; |
|
|
|
ret = platform_device_add_data(pdev, (const void *)mach, sizeof(*mach)); |
|
if (ret) { |
|
dev_err(bus->dev, "failed to add machine device platform data\n"); |
|
platform_device_put(pdev); |
|
return ret; |
|
} |
|
|
|
ret = platform_device_add(pdev); |
|
if (ret) { |
|
dev_err(bus->dev, "failed to add machine device\n"); |
|
platform_device_put(pdev); |
|
return -EIO; |
|
} |
|
|
|
|
|
skl->i2s_dev = pdev; |
|
|
|
return 0; |
|
} |
|
|
|
static void skl_machine_device_unregister(struct skl_dev *skl) |
|
{ |
|
if (skl->i2s_dev) |
|
platform_device_unregister(skl->i2s_dev); |
|
} |
|
|
|
static int skl_dmic_device_register(struct skl_dev *skl) |
|
{ |
|
struct hdac_bus *bus = skl_to_bus(skl); |
|
struct platform_device *pdev; |
|
int ret; |
|
|
|
/* SKL has one dmic port, so allocate dmic device for this */ |
|
pdev = platform_device_alloc("dmic-codec", -1); |
|
if (!pdev) { |
|
dev_err(bus->dev, "failed to allocate dmic device\n"); |
|
return -ENOMEM; |
|
} |
|
|
|
ret = platform_device_add(pdev); |
|
if (ret) { |
|
dev_err(bus->dev, "failed to add dmic device: %d\n", ret); |
|
platform_device_put(pdev); |
|
return ret; |
|
} |
|
skl->dmic_dev = pdev; |
|
|
|
return 0; |
|
} |
|
|
|
static void skl_dmic_device_unregister(struct skl_dev *skl) |
|
{ |
|
if (skl->dmic_dev) |
|
platform_device_unregister(skl->dmic_dev); |
|
} |
|
|
|
static struct skl_clk_parent_src skl_clk_src[] = { |
|
{ .clk_id = SKL_XTAL, .name = "xtal" }, |
|
{ .clk_id = SKL_CARDINAL, .name = "cardinal", .rate = 24576000 }, |
|
{ .clk_id = SKL_PLL, .name = "pll", .rate = 96000000 }, |
|
}; |
|
|
|
struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id) |
|
{ |
|
unsigned int i; |
|
|
|
for (i = 0; i < ARRAY_SIZE(skl_clk_src); i++) { |
|
if (skl_clk_src[i].clk_id == clk_id) |
|
return &skl_clk_src[i]; |
|
} |
|
|
|
return NULL; |
|
} |
|
|
|
static void init_skl_xtal_rate(int pci_id) |
|
{ |
|
switch (pci_id) { |
|
case 0x9d70: |
|
case 0x9d71: |
|
skl_clk_src[0].rate = 24000000; |
|
return; |
|
|
|
default: |
|
skl_clk_src[0].rate = 19200000; |
|
return; |
|
} |
|
} |
|
|
|
static int skl_clock_device_register(struct skl_dev *skl) |
|
{ |
|
struct platform_device_info pdevinfo = {NULL}; |
|
struct skl_clk_pdata *clk_pdata; |
|
|
|
if (!skl->nhlt) |
|
return 0; |
|
|
|
clk_pdata = devm_kzalloc(&skl->pci->dev, sizeof(*clk_pdata), |
|
GFP_KERNEL); |
|
if (!clk_pdata) |
|
return -ENOMEM; |
|
|
|
init_skl_xtal_rate(skl->pci->device); |
|
|
|
clk_pdata->parent_clks = skl_clk_src; |
|
clk_pdata->ssp_clks = skl_ssp_clks; |
|
clk_pdata->num_clks = ARRAY_SIZE(skl_ssp_clks); |
|
|
|
/* Query NHLT to fill the rates and parent */ |
|
skl_get_clks(skl, clk_pdata->ssp_clks); |
|
clk_pdata->pvt_data = skl; |
|
|
|
/* Register Platform device */ |
|
pdevinfo.parent = &skl->pci->dev; |
|
pdevinfo.id = -1; |
|
pdevinfo.name = "skl-ssp-clk"; |
|
pdevinfo.data = clk_pdata; |
|
pdevinfo.size_data = sizeof(*clk_pdata); |
|
skl->clk_dev = platform_device_register_full(&pdevinfo); |
|
return PTR_ERR_OR_ZERO(skl->clk_dev); |
|
} |
|
|
|
static void skl_clock_device_unregister(struct skl_dev *skl) |
|
{ |
|
if (skl->clk_dev) |
|
platform_device_unregister(skl->clk_dev); |
|
} |
|
|
|
#if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) |
|
|
|
#define IDISP_INTEL_VENDOR_ID 0x80860000 |
|
|
|
/* |
|
* load the legacy codec driver |
|
*/ |
|
static void load_codec_module(struct hda_codec *codec) |
|
{ |
|
#ifdef MODULE |
|
char modalias[MODULE_NAME_LEN]; |
|
const char *mod = NULL; |
|
|
|
snd_hdac_codec_modalias(&codec->core, modalias, sizeof(modalias)); |
|
mod = modalias; |
|
dev_dbg(&codec->core.dev, "loading %s codec module\n", mod); |
|
request_module(mod); |
|
#endif |
|
} |
|
|
|
#endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */ |
|
|
|
/* |
|
* Probe the given codec address |
|
*/ |
|
static int probe_codec(struct hdac_bus *bus, int addr) |
|
{ |
|
unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | |
|
(AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; |
|
unsigned int res = -1; |
|
struct skl_dev *skl = bus_to_skl(bus); |
|
#if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) |
|
struct hdac_hda_priv *hda_codec; |
|
int err; |
|
#endif |
|
struct hdac_device *hdev; |
|
|
|
mutex_lock(&bus->cmd_mutex); |
|
snd_hdac_bus_send_cmd(bus, cmd); |
|
snd_hdac_bus_get_response(bus, addr, &res); |
|
mutex_unlock(&bus->cmd_mutex); |
|
if (res == -1) |
|
return -EIO; |
|
dev_dbg(bus->dev, "codec #%d probed OK: %x\n", addr, res); |
|
|
|
#if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) |
|
hda_codec = devm_kzalloc(&skl->pci->dev, sizeof(*hda_codec), |
|
GFP_KERNEL); |
|
if (!hda_codec) |
|
return -ENOMEM; |
|
|
|
hda_codec->codec.bus = skl_to_hbus(skl); |
|
hdev = &hda_codec->codec.core; |
|
|
|
err = snd_hdac_ext_bus_device_init(bus, addr, hdev, HDA_DEV_ASOC); |
|
if (err < 0) |
|
return err; |
|
|
|
/* use legacy bus only for HDA codecs, idisp uses ext bus */ |
|
if ((res & 0xFFFF0000) != IDISP_INTEL_VENDOR_ID) { |
|
hdev->type = HDA_DEV_LEGACY; |
|
load_codec_module(&hda_codec->codec); |
|
} |
|
return 0; |
|
#else |
|
hdev = devm_kzalloc(&skl->pci->dev, sizeof(*hdev), GFP_KERNEL); |
|
if (!hdev) |
|
return -ENOMEM; |
|
|
|
return snd_hdac_ext_bus_device_init(bus, addr, hdev, HDA_DEV_ASOC); |
|
#endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */ |
|
} |
|
|
|
/* Codec initialization */ |
|
static void skl_codec_create(struct hdac_bus *bus) |
|
{ |
|
int c, max_slots; |
|
|
|
max_slots = HDA_MAX_CODECS; |
|
|
|
/* First try to probe all given codec slots */ |
|
for (c = 0; c < max_slots; c++) { |
|
if ((bus->codec_mask & (1 << c))) { |
|
if (probe_codec(bus, c) < 0) { |
|
/* |
|
* Some BIOSen give you wrong codec addresses |
|
* that don't exist |
|
*/ |
|
dev_warn(bus->dev, |
|
"Codec #%d probe error; disabling it...\n", c); |
|
bus->codec_mask &= ~(1 << c); |
|
/* |
|
* More badly, accessing to a non-existing |
|
* codec often screws up the controller bus, |
|
* and disturbs the further communications. |
|
* Thus if an error occurs during probing, |
|
* better to reset the controller bus to get |
|
* back to the sanity state. |
|
*/ |
|
snd_hdac_bus_stop_chip(bus); |
|
skl_init_chip(bus, true); |
|
} |
|
} |
|
} |
|
} |
|
|
|
static int skl_i915_init(struct hdac_bus *bus) |
|
{ |
|
int err; |
|
|
|
/* |
|
* The HDMI codec is in GPU so we need to ensure that it is powered |
|
* up and ready for probe |
|
*/ |
|
err = snd_hdac_i915_init(bus); |
|
if (err < 0) |
|
return err; |
|
|
|
snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true); |
|
|
|
return 0; |
|
} |
|
|
|
static void skl_probe_work(struct work_struct *work) |
|
{ |
|
struct skl_dev *skl = container_of(work, struct skl_dev, probe_work); |
|
struct hdac_bus *bus = skl_to_bus(skl); |
|
struct hdac_ext_link *hlink; |
|
int err; |
|
|
|
if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { |
|
err = skl_i915_init(bus); |
|
if (err < 0) |
|
return; |
|
} |
|
|
|
skl_init_pci(skl); |
|
skl_dum_set(bus); |
|
|
|
err = skl_init_chip(bus, true); |
|
if (err < 0) { |
|
dev_err(bus->dev, "Init chip failed with err: %d\n", err); |
|
goto out_err; |
|
} |
|
|
|
/* codec detection */ |
|
if (!bus->codec_mask) |
|
dev_info(bus->dev, "no hda codecs found!\n"); |
|
|
|
/* create codec instances */ |
|
skl_codec_create(bus); |
|
|
|
/* register platform dai and controls */ |
|
err = skl_platform_register(bus->dev); |
|
if (err < 0) { |
|
dev_err(bus->dev, "platform register failed: %d\n", err); |
|
goto out_err; |
|
} |
|
|
|
err = skl_machine_device_register(skl); |
|
if (err < 0) { |
|
dev_err(bus->dev, "machine register failed: %d\n", err); |
|
goto out_err; |
|
} |
|
|
|
/* |
|
* we are done probing so decrement link counts |
|
*/ |
|
list_for_each_entry(hlink, &bus->hlink_list, list) |
|
snd_hdac_ext_bus_link_put(bus, hlink); |
|
|
|
if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) |
|
snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); |
|
|
|
/* configure PM */ |
|
pm_runtime_put_noidle(bus->dev); |
|
pm_runtime_allow(bus->dev); |
|
skl->init_done = 1; |
|
|
|
return; |
|
|
|
out_err: |
|
if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) |
|
snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); |
|
} |
|
|
|
/* |
|
* constructor |
|
*/ |
|
static int skl_create(struct pci_dev *pci, |
|
struct skl_dev **rskl) |
|
{ |
|
struct hdac_ext_bus_ops *ext_ops = NULL; |
|
struct skl_dev *skl; |
|
struct hdac_bus *bus; |
|
struct hda_bus *hbus; |
|
int err; |
|
|
|
*rskl = NULL; |
|
|
|
err = pci_enable_device(pci); |
|
if (err < 0) |
|
return err; |
|
|
|
skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL); |
|
if (!skl) { |
|
pci_disable_device(pci); |
|
return -ENOMEM; |
|
} |
|
|
|
hbus = skl_to_hbus(skl); |
|
bus = skl_to_bus(skl); |
|
|
|
INIT_LIST_HEAD(&skl->ppl_list); |
|
INIT_LIST_HEAD(&skl->bind_list); |
|
|
|
#if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) |
|
ext_ops = snd_soc_hdac_hda_get_ops(); |
|
#endif |
|
snd_hdac_ext_bus_init(bus, &pci->dev, NULL, ext_ops); |
|
bus->use_posbuf = 1; |
|
skl->pci = pci; |
|
INIT_WORK(&skl->probe_work, skl_probe_work); |
|
bus->bdl_pos_adj = 0; |
|
|
|
mutex_init(&hbus->prepare_mutex); |
|
hbus->pci = pci; |
|
hbus->mixer_assigned = -1; |
|
hbus->modelname = "sklbus"; |
|
|
|
*rskl = skl; |
|
|
|
return 0; |
|
} |
|
|
|
static int skl_first_init(struct hdac_bus *bus) |
|
{ |
|
struct skl_dev *skl = bus_to_skl(bus); |
|
struct pci_dev *pci = skl->pci; |
|
int err; |
|
unsigned short gcap; |
|
int cp_streams, pb_streams, start_idx; |
|
|
|
err = pci_request_regions(pci, "Skylake HD audio"); |
|
if (err < 0) |
|
return err; |
|
|
|
bus->addr = pci_resource_start(pci, 0); |
|
bus->remap_addr = pci_ioremap_bar(pci, 0); |
|
if (bus->remap_addr == NULL) { |
|
dev_err(bus->dev, "ioremap error\n"); |
|
return -ENXIO; |
|
} |
|
|
|
snd_hdac_bus_parse_capabilities(bus); |
|
|
|
/* check if PPCAP exists */ |
|
if (!bus->ppcap) { |
|
dev_err(bus->dev, "bus ppcap not set, HDAudio or DSP not present?\n"); |
|
return -ENODEV; |
|
} |
|
|
|
if (skl_acquire_irq(bus, 0) < 0) |
|
return -EBUSY; |
|
|
|
pci_set_master(pci); |
|
synchronize_irq(bus->irq); |
|
|
|
gcap = snd_hdac_chip_readw(bus, GCAP); |
|
dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap); |
|
|
|
/* read number of streams from GCAP register */ |
|
cp_streams = (gcap >> 8) & 0x0f; |
|
pb_streams = (gcap >> 12) & 0x0f; |
|
|
|
if (!pb_streams && !cp_streams) { |
|
dev_err(bus->dev, "no streams found in GCAP definitions?\n"); |
|
return -EIO; |
|
} |
|
|
|
bus->num_streams = cp_streams + pb_streams; |
|
|
|
/* allow 64bit DMA address if supported by H/W */ |
|
if (dma_set_mask_and_coherent(bus->dev, DMA_BIT_MASK(64))) |
|
dma_set_mask_and_coherent(bus->dev, DMA_BIT_MASK(32)); |
|
|
|
/* initialize streams */ |
|
snd_hdac_ext_stream_init_all |
|
(bus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE); |
|
start_idx = cp_streams; |
|
snd_hdac_ext_stream_init_all |
|
(bus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK); |
|
|
|
err = snd_hdac_bus_alloc_stream_pages(bus); |
|
if (err < 0) |
|
return err; |
|
|
|
return 0; |
|
} |
|
|
|
static int skl_probe(struct pci_dev *pci, |
|
const struct pci_device_id *pci_id) |
|
{ |
|
struct skl_dev *skl; |
|
struct hdac_bus *bus = NULL; |
|
int err; |
|
|
|
switch (skl_pci_binding) { |
|
case SND_SKL_PCI_BIND_AUTO: |
|
err = snd_intel_dsp_driver_probe(pci); |
|
if (err != SND_INTEL_DSP_DRIVER_ANY && |
|
err != SND_INTEL_DSP_DRIVER_SST) |
|
return -ENODEV; |
|
break; |
|
case SND_SKL_PCI_BIND_LEGACY: |
|
dev_info(&pci->dev, "Module parameter forced binding with HDAudio legacy, aborting probe\n"); |
|
return -ENODEV; |
|
case SND_SKL_PCI_BIND_ASOC: |
|
dev_info(&pci->dev, "Module parameter forced binding with SKL driver, bypassed detection logic\n"); |
|
break; |
|
default: |
|
dev_err(&pci->dev, "invalid value for skl_pci_binding module parameter, ignored\n"); |
|
break; |
|
} |
|
|
|
/* we use ext core ops, so provide NULL for ops here */ |
|
err = skl_create(pci, &skl); |
|
if (err < 0) |
|
return err; |
|
|
|
bus = skl_to_bus(skl); |
|
|
|
err = skl_first_init(bus); |
|
if (err < 0) { |
|
dev_err(bus->dev, "skl_first_init failed with err: %d\n", err); |
|
goto out_free; |
|
} |
|
|
|
skl->pci_id = pci->device; |
|
|
|
device_disable_async_suspend(bus->dev); |
|
|
|
skl->nhlt = intel_nhlt_init(bus->dev); |
|
|
|
if (skl->nhlt == NULL) { |
|
#if !IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) |
|
dev_err(bus->dev, "no nhlt info found\n"); |
|
err = -ENODEV; |
|
goto out_free; |
|
#else |
|
dev_warn(bus->dev, "no nhlt info found, continuing to try to enable HDAudio codec\n"); |
|
#endif |
|
} else { |
|
|
|
err = skl_nhlt_create_sysfs(skl); |
|
if (err < 0) { |
|
dev_err(bus->dev, "skl_nhlt_create_sysfs failed with err: %d\n", err); |
|
goto out_nhlt_free; |
|
} |
|
|
|
skl_nhlt_update_topology_bin(skl); |
|
|
|
/* create device for dsp clk */ |
|
err = skl_clock_device_register(skl); |
|
if (err < 0) { |
|
dev_err(bus->dev, "skl_clock_device_register failed with err: %d\n", err); |
|
goto out_clk_free; |
|
} |
|
} |
|
|
|
pci_set_drvdata(skl->pci, bus); |
|
|
|
|
|
err = skl_find_machine(skl, (void *)pci_id->driver_data); |
|
if (err < 0) { |
|
dev_err(bus->dev, "skl_find_machine failed with err: %d\n", err); |
|
goto out_nhlt_free; |
|
} |
|
|
|
err = skl_init_dsp(skl); |
|
if (err < 0) { |
|
dev_dbg(bus->dev, "error failed to register dsp\n"); |
|
goto out_nhlt_free; |
|
} |
|
skl->enable_miscbdcge = skl_enable_miscbdcge; |
|
skl->clock_power_gating = skl_clock_power_gating; |
|
|
|
if (bus->mlcap) |
|
snd_hdac_ext_bus_get_ml_capabilities(bus); |
|
|
|
/* create device for soc dmic */ |
|
err = skl_dmic_device_register(skl); |
|
if (err < 0) { |
|
dev_err(bus->dev, "skl_dmic_device_register failed with err: %d\n", err); |
|
goto out_dsp_free; |
|
} |
|
|
|
schedule_work(&skl->probe_work); |
|
|
|
return 0; |
|
|
|
out_dsp_free: |
|
skl_free_dsp(skl); |
|
out_clk_free: |
|
skl_clock_device_unregister(skl); |
|
out_nhlt_free: |
|
if (skl->nhlt) |
|
intel_nhlt_free(skl->nhlt); |
|
out_free: |
|
skl_free(bus); |
|
|
|
return err; |
|
} |
|
|
|
static void skl_shutdown(struct pci_dev *pci) |
|
{ |
|
struct hdac_bus *bus = pci_get_drvdata(pci); |
|
struct hdac_stream *s; |
|
struct hdac_ext_stream *stream; |
|
struct skl_dev *skl; |
|
|
|
if (!bus) |
|
return; |
|
|
|
skl = bus_to_skl(bus); |
|
|
|
if (!skl->init_done) |
|
return; |
|
|
|
snd_hdac_ext_stop_streams(bus); |
|
list_for_each_entry(s, &bus->stream_list, list) { |
|
stream = stream_to_hdac_ext_stream(s); |
|
snd_hdac_ext_stream_decouple(bus, stream, false); |
|
} |
|
|
|
snd_hdac_bus_stop_chip(bus); |
|
} |
|
|
|
static void skl_remove(struct pci_dev *pci) |
|
{ |
|
struct hdac_bus *bus = pci_get_drvdata(pci); |
|
struct skl_dev *skl = bus_to_skl(bus); |
|
|
|
cancel_work_sync(&skl->probe_work); |
|
|
|
pm_runtime_get_noresume(&pci->dev); |
|
|
|
/* codec removal, invoke bus_device_remove */ |
|
snd_hdac_ext_bus_device_remove(bus); |
|
|
|
skl_platform_unregister(&pci->dev); |
|
skl_free_dsp(skl); |
|
skl_machine_device_unregister(skl); |
|
skl_dmic_device_unregister(skl); |
|
skl_clock_device_unregister(skl); |
|
skl_nhlt_remove_sysfs(skl); |
|
if (skl->nhlt) |
|
intel_nhlt_free(skl->nhlt); |
|
skl_free(bus); |
|
dev_set_drvdata(&pci->dev, NULL); |
|
} |
|
|
|
/* PCI IDs */ |
|
static const struct pci_device_id skl_ids[] = { |
|
#if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKL) |
|
/* Sunrise Point-LP */ |
|
{ PCI_DEVICE(0x8086, 0x9d70), |
|
.driver_data = (unsigned long)&snd_soc_acpi_intel_skl_machines}, |
|
#endif |
|
#if IS_ENABLED(CONFIG_SND_SOC_INTEL_APL) |
|
/* BXT-P */ |
|
{ PCI_DEVICE(0x8086, 0x5a98), |
|
.driver_data = (unsigned long)&snd_soc_acpi_intel_bxt_machines}, |
|
#endif |
|
#if IS_ENABLED(CONFIG_SND_SOC_INTEL_KBL) |
|
/* KBL */ |
|
{ PCI_DEVICE(0x8086, 0x9D71), |
|
.driver_data = (unsigned long)&snd_soc_acpi_intel_kbl_machines}, |
|
#endif |
|
#if IS_ENABLED(CONFIG_SND_SOC_INTEL_GLK) |
|
/* GLK */ |
|
{ PCI_DEVICE(0x8086, 0x3198), |
|
.driver_data = (unsigned long)&snd_soc_acpi_intel_glk_machines}, |
|
#endif |
|
#if IS_ENABLED(CONFIG_SND_SOC_INTEL_CNL) |
|
/* CNL */ |
|
{ PCI_DEVICE(0x8086, 0x9dc8), |
|
.driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, |
|
#endif |
|
#if IS_ENABLED(CONFIG_SND_SOC_INTEL_CFL) |
|
/* CFL */ |
|
{ PCI_DEVICE(0x8086, 0xa348), |
|
.driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, |
|
#endif |
|
#if IS_ENABLED(CONFIG_SND_SOC_INTEL_CML_LP) |
|
/* CML-LP */ |
|
{ PCI_DEVICE(0x8086, 0x02c8), |
|
.driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, |
|
#endif |
|
#if IS_ENABLED(CONFIG_SND_SOC_INTEL_CML_H) |
|
/* CML-H */ |
|
{ PCI_DEVICE(0x8086, 0x06c8), |
|
.driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, |
|
#endif |
|
{ 0, } |
|
}; |
|
MODULE_DEVICE_TABLE(pci, skl_ids); |
|
|
|
/* pci_driver definition */ |
|
static struct pci_driver skl_driver = { |
|
.name = KBUILD_MODNAME, |
|
.id_table = skl_ids, |
|
.probe = skl_probe, |
|
.remove = skl_remove, |
|
.shutdown = skl_shutdown, |
|
.driver = { |
|
.pm = &skl_pm, |
|
}, |
|
}; |
|
module_pci_driver(skl_driver); |
|
|
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver");
|
|
|