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291 lines
12 KiB
291 lines
12 KiB
.. SPDX-License-Identifier: GPL-2.0 |
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============================================================== |
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ARM Virtual Generic Interrupt Controller v3 and later (VGICv3) |
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============================================================== |
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Device types supported: |
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- KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0 |
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Only one VGIC instance may be instantiated through this API. The created VGIC |
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will act as the VM interrupt controller, requiring emulated user-space devices |
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to inject interrupts to the VGIC instead of directly to CPUs. It is not |
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possible to create both a GICv3 and GICv2 on the same VM. |
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Creating a guest GICv3 device requires a host GICv3 as well. |
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Groups: |
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KVM_DEV_ARM_VGIC_GRP_ADDR |
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Attributes: |
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KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit) |
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Base address in the guest physical address space of the GICv3 distributor |
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register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V3. |
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This address needs to be 64K aligned and the region covers 64 KByte. |
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KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit) |
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Base address in the guest physical address space of the GICv3 |
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redistributor register mappings. There are two 64K pages for each |
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VCPU and all of the redistributor pages are contiguous. |
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Only valid for KVM_DEV_TYPE_ARM_VGIC_V3. |
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This address needs to be 64K aligned. |
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KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit) |
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The attribute data pointed to by kvm_device_attr.addr is a __u64 value:: |
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bits: | 63 .... 52 | 51 .... 16 | 15 - 12 |11 - 0 |
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values: | count | base | flags | index |
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- index encodes the unique redistributor region index |
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- flags: reserved for future use, currently 0 |
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- base field encodes bits [51:16] of the guest physical base address |
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of the first redistributor in the region. |
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- count encodes the number of redistributors in the region. Must be |
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greater than 0. |
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There are two 64K pages for each redistributor in the region and |
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redistributors are laid out contiguously within the region. Regions |
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are filled with redistributors in the index order. The sum of all |
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region count fields must be greater than or equal to the number of |
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VCPUs. Redistributor regions must be registered in the incremental |
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index order, starting from index 0. |
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The characteristics of a specific redistributor region can be read |
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by presetting the index field in the attr data. |
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Only valid for KVM_DEV_TYPE_ARM_VGIC_V3. |
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It is invalid to mix calls with KVM_VGIC_V3_ADDR_TYPE_REDIST and |
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KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION attributes. |
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Errors: |
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======= ============================================================= |
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-E2BIG Address outside of addressable IPA range |
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-EINVAL Incorrectly aligned address, bad redistributor region |
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count/index, mixed redistributor region attribute usage |
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-EEXIST Address already configured |
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-ENOENT Attempt to read the characteristics of a non existing |
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redistributor region |
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-ENXIO The group or attribute is unknown/unsupported for this device |
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or hardware support is missing. |
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-EFAULT Invalid user pointer for attr->addr. |
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======= ============================================================= |
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KVM_DEV_ARM_VGIC_GRP_DIST_REGS, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS |
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Attributes: |
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The attr field of kvm_device_attr encodes two values:: |
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bits: | 63 .... 32 | 31 .... 0 | |
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values: | mpidr | offset | |
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All distributor regs are (rw, 32-bit) and kvm_device_attr.addr points to a |
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__u32 value. 64-bit registers must be accessed by separately accessing the |
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lower and higher word. |
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Writes to read-only registers are ignored by the kernel. |
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KVM_DEV_ARM_VGIC_GRP_DIST_REGS accesses the main distributor registers. |
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KVM_DEV_ARM_VGIC_GRP_REDIST_REGS accesses the redistributor of the CPU |
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specified by the mpidr. |
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The offset is relative to the "[Re]Distributor base address" as defined |
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in the GICv3/4 specs. Getting or setting such a register has the same |
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effect as reading or writing the register on real hardware, except for the |
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following registers: GICD_STATUSR, GICR_STATUSR, GICD_ISPENDR, |
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GICR_ISPENDR0, GICD_ICPENDR, and GICR_ICPENDR0. These registers behave |
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differently when accessed via this interface compared to their |
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architecturally defined behavior to allow software a full view of the |
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VGIC's internal state. |
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The mpidr field is used to specify which |
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redistributor is accessed. The mpidr is ignored for the distributor. |
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The mpidr encoding is based on the affinity information in the |
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architecture defined MPIDR, and the field is encoded as follows:: |
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| 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 | |
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| Aff3 | Aff2 | Aff1 | Aff0 | |
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Note that distributor fields are not banked, but return the same value |
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regardless of the mpidr used to access the register. |
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GICD_IIDR.Revision is updated when the KVM implementation is changed in a |
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way directly observable by the guest or userspace. Userspace should read |
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GICD_IIDR from KVM and write back the read value to confirm its expected |
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behavior is aligned with the KVM implementation. Userspace should set |
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GICD_IIDR before setting any other registers to ensure the expected |
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behavior. |
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The GICD_STATUSR and GICR_STATUSR registers are architecturally defined such |
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that a write of a clear bit has no effect, whereas a write with a set bit |
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clears that value. To allow userspace to freely set the values of these two |
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registers, setting the attributes with the register offsets for these two |
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registers simply sets the non-reserved bits to the value written. |
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Accesses (reads and writes) to the GICD_ISPENDR register region and |
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GICR_ISPENDR0 registers get/set the value of the latched pending state for |
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the interrupts. |
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This is identical to the value returned by a guest read from ISPENDR for an |
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edge triggered interrupt, but may differ for level triggered interrupts. |
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For edge triggered interrupts, once an interrupt becomes pending (whether |
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because of an edge detected on the input line or because of a guest write |
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to ISPENDR) this state is "latched", and only cleared when either the |
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interrupt is activated or when the guest writes to ICPENDR. A level |
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triggered interrupt may be pending either because the level input is held |
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high by a device, or because of a guest write to the ISPENDR register. Only |
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ISPENDR writes are latched; if the device lowers the line level then the |
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interrupt is no longer pending unless the guest also wrote to ISPENDR, and |
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conversely writes to ICPENDR or activations of the interrupt do not clear |
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the pending status if the line level is still being held high. (These |
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rules are documented in the GICv3 specification descriptions of the ICPENDR |
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and ISPENDR registers.) For a level triggered interrupt the value accessed |
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here is that of the latch which is set by ISPENDR and cleared by ICPENDR or |
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interrupt activation, whereas the value returned by a guest read from |
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ISPENDR is the logical OR of the latch value and the input line level. |
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Raw access to the latch state is provided to userspace so that it can save |
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and restore the entire GIC internal state (which is defined by the |
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combination of the current input line level and the latch state, and cannot |
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be deduced from purely the line level and the value of the ISPENDR |
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registers). |
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Accesses to GICD_ICPENDR register region and GICR_ICPENDR0 registers have |
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RAZ/WI semantics, meaning that reads always return 0 and writes are always |
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ignored. |
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Errors: |
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====== ===================================================== |
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-ENXIO Getting or setting this register is not yet supported |
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-EBUSY One or more VCPUs are running |
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====== ===================================================== |
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KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS |
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Attributes: |
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The attr field of kvm_device_attr encodes two values:: |
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bits: | 63 .... 32 | 31 .... 16 | 15 .... 0 | |
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values: | mpidr | RES | instr | |
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The mpidr field encodes the CPU ID based on the affinity information in the |
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architecture defined MPIDR, and the field is encoded as follows:: |
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| 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 | |
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| Aff3 | Aff2 | Aff1 | Aff0 | |
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The instr field encodes the system register to access based on the fields |
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defined in the A64 instruction set encoding for system register access |
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(RES means the bits are reserved for future use and should be zero):: |
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| 15 ... 14 | 13 ... 11 | 10 ... 7 | 6 ... 3 | 2 ... 0 | |
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| Op 0 | Op1 | CRn | CRm | Op2 | |
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All system regs accessed through this API are (rw, 64-bit) and |
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kvm_device_attr.addr points to a __u64 value. |
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KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS accesses the CPU interface registers for the |
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CPU specified by the mpidr field. |
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CPU interface registers access is not implemented for AArch32 mode. |
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Error -ENXIO is returned when accessed in AArch32 mode. |
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Errors: |
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======= ===================================================== |
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-ENXIO Getting or setting this register is not yet supported |
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-EBUSY VCPU is running |
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-EINVAL Invalid mpidr or register value supplied |
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======= ===================================================== |
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KVM_DEV_ARM_VGIC_GRP_NR_IRQS |
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Attributes: |
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A value describing the number of interrupts (SGI, PPI and SPI) for |
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this GIC instance, ranging from 64 to 1024, in increments of 32. |
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kvm_device_attr.addr points to a __u32 value. |
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Errors: |
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======= ====================================== |
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-EINVAL Value set is out of the expected range |
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-EBUSY Value has already be set. |
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======= ====================================== |
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KVM_DEV_ARM_VGIC_GRP_CTRL |
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Attributes: |
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KVM_DEV_ARM_VGIC_CTRL_INIT |
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request the initialization of the VGIC, no additional parameter in |
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kvm_device_attr.addr. Must be called after all VCPUs have been created. |
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KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES |
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save all LPI pending bits into guest RAM pending tables. |
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The first kB of the pending table is not altered by this operation. |
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Errors: |
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======= ======================================================== |
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-ENXIO VGIC not properly configured as required prior to calling |
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this attribute |
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-ENODEV no online VCPU |
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-ENOMEM memory shortage when allocating vgic internal data |
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-EFAULT Invalid guest ram access |
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-EBUSY One or more VCPUS are running |
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======= ======================================================== |
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KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO |
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Attributes: |
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The attr field of kvm_device_attr encodes the following values:: |
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bits: | 63 .... 32 | 31 .... 10 | 9 .... 0 | |
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values: | mpidr | info | vINTID | |
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The vINTID specifies which set of IRQs is reported on. |
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The info field specifies which information userspace wants to get or set |
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using this interface. Currently we support the following info values: |
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VGIC_LEVEL_INFO_LINE_LEVEL: |
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Get/Set the input level of the IRQ line for a set of 32 contiguously |
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numbered interrupts. |
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vINTID must be a multiple of 32. |
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kvm_device_attr.addr points to a __u32 value which will contain a |
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bitmap where a set bit means the interrupt level is asserted. |
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Bit[n] indicates the status for interrupt vINTID + n. |
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SGIs and any interrupt with a higher ID than the number of interrupts |
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supported, will be RAZ/WI. LPIs are always edge-triggered and are |
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therefore not supported by this interface. |
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PPIs are reported per VCPU as specified in the mpidr field, and SPIs are |
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reported with the same value regardless of the mpidr specified. |
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The mpidr field encodes the CPU ID based on the affinity information in the |
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architecture defined MPIDR, and the field is encoded as follows:: |
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| 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 | |
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| Aff3 | Aff2 | Aff1 | Aff0 | |
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Errors: |
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======= ============================================= |
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-EINVAL vINTID is not multiple of 32 or info field is |
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not VGIC_LEVEL_INFO_LINE_LEVEL |
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======= =============================================
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