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573 lines
15 KiB
573 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* tegra30_i2s.c - Tegra30 I2S driver |
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* |
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* Author: Stephen Warren <[email protected]> |
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* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. |
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* |
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* Based on code copyright/by: |
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* |
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* Copyright (c) 2009-2010, NVIDIA Corporation. |
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* Scott Peterson <[email protected]> |
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* |
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* Copyright (C) 2010 Google, Inc. |
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* Iliyan Malchev <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/device.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/regmap.h> |
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#include <linux/reset.h> |
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#include <linux/slab.h> |
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#include <sound/core.h> |
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#include <sound/pcm.h> |
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#include <sound/pcm_params.h> |
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#include <sound/soc.h> |
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#include <sound/dmaengine_pcm.h> |
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#include "tegra30_ahub.h" |
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#include "tegra30_i2s.h" |
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#define DRV_NAME "tegra30-i2s" |
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static __maybe_unused int tegra30_i2s_runtime_suspend(struct device *dev) |
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{ |
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struct tegra30_i2s *i2s = dev_get_drvdata(dev); |
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regcache_cache_only(i2s->regmap, true); |
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clk_disable_unprepare(i2s->clk_i2s); |
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return 0; |
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} |
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static __maybe_unused int tegra30_i2s_runtime_resume(struct device *dev) |
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{ |
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struct tegra30_i2s *i2s = dev_get_drvdata(dev); |
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int ret; |
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ret = clk_prepare_enable(i2s->clk_i2s); |
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if (ret) { |
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dev_err(dev, "clk_enable failed: %d\n", ret); |
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return ret; |
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} |
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regcache_cache_only(i2s->regmap, false); |
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regcache_mark_dirty(i2s->regmap); |
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ret = regcache_sync(i2s->regmap); |
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if (ret) |
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goto disable_clocks; |
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return 0; |
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disable_clocks: |
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clk_disable_unprepare(i2s->clk_i2s); |
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return ret; |
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} |
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static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai, |
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unsigned int fmt) |
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{ |
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struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
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unsigned int mask = 0, val = 0; |
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
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case SND_SOC_DAIFMT_NB_NF: |
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break; |
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default: |
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return -EINVAL; |
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} |
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mask |= TEGRA30_I2S_CTRL_MASTER_ENABLE; |
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
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case SND_SOC_DAIFMT_CBS_CFS: |
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val |= TEGRA30_I2S_CTRL_MASTER_ENABLE; |
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break; |
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case SND_SOC_DAIFMT_CBM_CFM: |
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break; |
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default: |
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return -EINVAL; |
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} |
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mask |= TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK | |
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TEGRA30_I2S_CTRL_LRCK_MASK; |
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
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case SND_SOC_DAIFMT_DSP_A: |
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val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC; |
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val |= TEGRA30_I2S_CTRL_LRCK_L_LOW; |
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break; |
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case SND_SOC_DAIFMT_DSP_B: |
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val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC; |
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val |= TEGRA30_I2S_CTRL_LRCK_R_LOW; |
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break; |
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case SND_SOC_DAIFMT_I2S: |
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val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK; |
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val |= TEGRA30_I2S_CTRL_LRCK_L_LOW; |
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break; |
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case SND_SOC_DAIFMT_RIGHT_J: |
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val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK; |
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val |= TEGRA30_I2S_CTRL_LRCK_L_LOW; |
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break; |
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case SND_SOC_DAIFMT_LEFT_J: |
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val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK; |
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val |= TEGRA30_I2S_CTRL_LRCK_L_LOW; |
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break; |
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default: |
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return -EINVAL; |
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} |
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pm_runtime_get_sync(dai->dev); |
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regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val); |
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pm_runtime_put(dai->dev); |
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return 0; |
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} |
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static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *dai) |
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{ |
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struct device *dev = dai->dev; |
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struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
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unsigned int mask, val, reg; |
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int ret, sample_size, srate, i2sclock, bitcnt; |
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struct tegra30_ahub_cif_conf cif_conf; |
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if (params_channels(params) != 2) |
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return -EINVAL; |
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mask = TEGRA30_I2S_CTRL_BIT_SIZE_MASK; |
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switch (params_format(params)) { |
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case SNDRV_PCM_FORMAT_S16_LE: |
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val = TEGRA30_I2S_CTRL_BIT_SIZE_16; |
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sample_size = 16; |
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break; |
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default: |
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return -EINVAL; |
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} |
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regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val); |
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srate = params_rate(params); |
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/* Final "* 2" required by Tegra hardware */ |
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i2sclock = srate * params_channels(params) * sample_size * 2; |
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bitcnt = (i2sclock / (2 * srate)) - 1; |
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if (bitcnt < 0 || bitcnt > TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US) |
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return -EINVAL; |
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ret = clk_set_rate(i2s->clk_i2s, i2sclock); |
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if (ret) { |
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dev_err(dev, "Can't set I2S clock rate: %d\n", ret); |
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return ret; |
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} |
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val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT; |
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if (i2sclock % (2 * srate)) |
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val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE; |
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regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val); |
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cif_conf.threshold = 0; |
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cif_conf.audio_channels = 2; |
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cif_conf.client_channels = 2; |
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cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16; |
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cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16; |
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cif_conf.expand = 0; |
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cif_conf.stereo_conv = 0; |
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cif_conf.replicate = 0; |
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cif_conf.truncate = 0; |
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cif_conf.mono_conv = 0; |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
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cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_RX; |
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reg = TEGRA30_I2S_CIF_RX_CTRL; |
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} else { |
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cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_TX; |
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reg = TEGRA30_I2S_CIF_TX_CTRL; |
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} |
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i2s->soc_data->set_audio_cif(i2s->regmap, reg, &cif_conf); |
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val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) | |
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(1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT); |
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regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val); |
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return 0; |
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} |
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static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s) |
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{ |
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tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif); |
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regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, |
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TEGRA30_I2S_CTRL_XFER_EN_TX, |
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TEGRA30_I2S_CTRL_XFER_EN_TX); |
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} |
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static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s) |
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{ |
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tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif); |
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regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, |
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TEGRA30_I2S_CTRL_XFER_EN_TX, 0); |
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} |
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static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s) |
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{ |
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tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif); |
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regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, |
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TEGRA30_I2S_CTRL_XFER_EN_RX, |
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TEGRA30_I2S_CTRL_XFER_EN_RX); |
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} |
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static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s) |
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{ |
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regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, |
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TEGRA30_I2S_CTRL_XFER_EN_RX, 0); |
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tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif); |
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} |
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static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd, |
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struct snd_soc_dai *dai) |
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{ |
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struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
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switch (cmd) { |
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case SNDRV_PCM_TRIGGER_START: |
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
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case SNDRV_PCM_TRIGGER_RESUME: |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
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tegra30_i2s_start_playback(i2s); |
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else |
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tegra30_i2s_start_capture(i2s); |
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break; |
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case SNDRV_PCM_TRIGGER_STOP: |
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
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case SNDRV_PCM_TRIGGER_SUSPEND: |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
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tegra30_i2s_stop_playback(i2s); |
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else |
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tegra30_i2s_stop_capture(i2s); |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int tegra30_i2s_set_tdm(struct snd_soc_dai *dai, |
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unsigned int tx_mask, unsigned int rx_mask, |
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int slots, int slot_width) |
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{ |
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struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
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unsigned int mask, val; |
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dev_dbg(dai->dev, "%s: txmask=0x%08x rxmask=0x%08x slots=%d width=%d\n", |
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__func__, tx_mask, rx_mask, slots, slot_width); |
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mask = TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK | |
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TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK | |
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TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK; |
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val = (tx_mask << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT) | |
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(rx_mask << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT) | |
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((slots - 1) << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT); |
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pm_runtime_get_sync(dai->dev); |
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regmap_update_bits(i2s->regmap, TEGRA30_I2S_SLOT_CTRL, mask, val); |
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/* set the fsync width to minimum of 1 clock width */ |
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regmap_update_bits(i2s->regmap, TEGRA30_I2S_CH_CTRL, |
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TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK, 0x0); |
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pm_runtime_put(dai->dev); |
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return 0; |
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} |
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static int tegra30_i2s_probe(struct snd_soc_dai *dai) |
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{ |
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struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
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dai->capture_dma_data = &i2s->capture_dma_data; |
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dai->playback_dma_data = &i2s->playback_dma_data; |
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return 0; |
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} |
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static const struct snd_soc_dai_ops tegra30_i2s_dai_ops = { |
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.set_fmt = tegra30_i2s_set_fmt, |
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.hw_params = tegra30_i2s_hw_params, |
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.trigger = tegra30_i2s_trigger, |
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.set_tdm_slot = tegra30_i2s_set_tdm, |
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}; |
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static const struct snd_soc_dai_driver tegra30_i2s_dai_template = { |
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.probe = tegra30_i2s_probe, |
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.playback = { |
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.stream_name = "Playback", |
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.channels_min = 2, |
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.channels_max = 2, |
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.rates = SNDRV_PCM_RATE_8000_96000, |
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.formats = SNDRV_PCM_FMTBIT_S16_LE, |
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}, |
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.capture = { |
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.stream_name = "Capture", |
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.channels_min = 2, |
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.channels_max = 2, |
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.rates = SNDRV_PCM_RATE_8000_96000, |
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.formats = SNDRV_PCM_FMTBIT_S16_LE, |
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}, |
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.ops = &tegra30_i2s_dai_ops, |
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.symmetric_rate = 1, |
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}; |
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static const struct snd_soc_component_driver tegra30_i2s_component = { |
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.name = DRV_NAME, |
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}; |
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static bool tegra30_i2s_wr_rd_reg(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case TEGRA30_I2S_CTRL: |
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case TEGRA30_I2S_TIMING: |
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case TEGRA30_I2S_OFFSET: |
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case TEGRA30_I2S_CH_CTRL: |
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case TEGRA30_I2S_SLOT_CTRL: |
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case TEGRA30_I2S_CIF_RX_CTRL: |
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case TEGRA30_I2S_CIF_TX_CTRL: |
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case TEGRA30_I2S_FLOWCTL: |
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case TEGRA30_I2S_TX_STEP: |
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case TEGRA30_I2S_FLOW_STATUS: |
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case TEGRA30_I2S_FLOW_TOTAL: |
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case TEGRA30_I2S_FLOW_OVER: |
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case TEGRA30_I2S_FLOW_UNDER: |
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case TEGRA30_I2S_LCOEF_1_4_0: |
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case TEGRA30_I2S_LCOEF_1_4_1: |
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case TEGRA30_I2S_LCOEF_1_4_2: |
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case TEGRA30_I2S_LCOEF_1_4_3: |
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case TEGRA30_I2S_LCOEF_1_4_4: |
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case TEGRA30_I2S_LCOEF_1_4_5: |
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case TEGRA30_I2S_LCOEF_2_4_0: |
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case TEGRA30_I2S_LCOEF_2_4_1: |
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case TEGRA30_I2S_LCOEF_2_4_2: |
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return true; |
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default: |
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return false; |
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} |
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} |
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static bool tegra30_i2s_volatile_reg(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case TEGRA30_I2S_FLOW_STATUS: |
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case TEGRA30_I2S_FLOW_TOTAL: |
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case TEGRA30_I2S_FLOW_OVER: |
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case TEGRA30_I2S_FLOW_UNDER: |
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return true; |
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default: |
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return false; |
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} |
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} |
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static const struct regmap_config tegra30_i2s_regmap_config = { |
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.reg_bits = 32, |
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.reg_stride = 4, |
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.val_bits = 32, |
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.max_register = TEGRA30_I2S_LCOEF_2_4_2, |
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.writeable_reg = tegra30_i2s_wr_rd_reg, |
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.readable_reg = tegra30_i2s_wr_rd_reg, |
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.volatile_reg = tegra30_i2s_volatile_reg, |
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.cache_type = REGCACHE_FLAT, |
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}; |
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static const struct tegra30_i2s_soc_data tegra30_i2s_config = { |
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.set_audio_cif = tegra30_ahub_set_cif, |
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}; |
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static const struct tegra30_i2s_soc_data tegra124_i2s_config = { |
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.set_audio_cif = tegra124_ahub_set_cif, |
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}; |
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static const struct of_device_id tegra30_i2s_of_match[] = { |
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{ .compatible = "nvidia,tegra124-i2s", .data = &tegra124_i2s_config }, |
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{ .compatible = "nvidia,tegra30-i2s", .data = &tegra30_i2s_config }, |
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{}, |
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}; |
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static int tegra30_i2s_platform_probe(struct platform_device *pdev) |
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{ |
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struct tegra30_i2s *i2s; |
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const struct tegra30_i2s_soc_data *soc_data; |
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u32 cif_ids[2]; |
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void __iomem *regs; |
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int ret; |
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i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL); |
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if (!i2s) { |
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ret = -ENOMEM; |
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goto err; |
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} |
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dev_set_drvdata(&pdev->dev, i2s); |
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soc_data = of_device_get_match_data(&pdev->dev); |
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if (!soc_data) { |
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dev_err(&pdev->dev, "Error: No device match found\n"); |
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ret = -ENODEV; |
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goto err; |
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} |
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i2s->soc_data = soc_data; |
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i2s->dai = tegra30_i2s_dai_template; |
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i2s->dai.name = dev_name(&pdev->dev); |
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ret = of_property_read_u32_array(pdev->dev.of_node, |
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"nvidia,ahub-cif-ids", cif_ids, |
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ARRAY_SIZE(cif_ids)); |
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if (ret < 0) |
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goto err; |
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i2s->playback_i2s_cif = cif_ids[0]; |
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i2s->capture_i2s_cif = cif_ids[1]; |
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i2s->clk_i2s = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(i2s->clk_i2s)) { |
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dev_err(&pdev->dev, "Can't retrieve i2s clock\n"); |
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ret = PTR_ERR(i2s->clk_i2s); |
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goto err; |
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} |
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regs = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(regs)) { |
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ret = PTR_ERR(regs); |
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goto err; |
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} |
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i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, |
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&tegra30_i2s_regmap_config); |
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if (IS_ERR(i2s->regmap)) { |
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dev_err(&pdev->dev, "regmap init failed\n"); |
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ret = PTR_ERR(i2s->regmap); |
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goto err; |
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} |
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regcache_cache_only(i2s->regmap, true); |
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pm_runtime_enable(&pdev->dev); |
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i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
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i2s->playback_dma_data.maxburst = 4; |
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ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif, |
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i2s->playback_dma_chan, |
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sizeof(i2s->playback_dma_chan), |
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&i2s->playback_dma_data.addr); |
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if (ret) { |
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dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret); |
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goto err_pm_disable; |
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} |
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ret = tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif, |
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i2s->playback_fifo_cif); |
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if (ret) { |
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dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret); |
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goto err_free_tx_fifo; |
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} |
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i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
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i2s->capture_dma_data.maxburst = 4; |
|
ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif, |
|
i2s->capture_dma_chan, |
|
sizeof(i2s->capture_dma_chan), |
|
&i2s->capture_dma_data.addr); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret); |
|
goto err_unroute_tx_fifo; |
|
} |
|
ret = tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif, |
|
i2s->capture_i2s_cif); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret); |
|
goto err_free_rx_fifo; |
|
} |
|
|
|
ret = snd_soc_register_component(&pdev->dev, &tegra30_i2s_component, |
|
&i2s->dai, 1); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); |
|
ret = -ENOMEM; |
|
goto err_unroute_rx_fifo; |
|
} |
|
|
|
ret = tegra_pcm_platform_register_with_chan_names(&pdev->dev, |
|
&i2s->dma_config, i2s->playback_dma_chan, |
|
i2s->capture_dma_chan); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Could not register PCM: %d\n", ret); |
|
goto err_unregister_component; |
|
} |
|
|
|
return 0; |
|
|
|
err_unregister_component: |
|
snd_soc_unregister_component(&pdev->dev); |
|
err_unroute_rx_fifo: |
|
tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif); |
|
err_free_rx_fifo: |
|
tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif); |
|
err_unroute_tx_fifo: |
|
tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif); |
|
err_free_tx_fifo: |
|
tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif); |
|
err_pm_disable: |
|
pm_runtime_disable(&pdev->dev); |
|
err: |
|
return ret; |
|
} |
|
|
|
static int tegra30_i2s_platform_remove(struct platform_device *pdev) |
|
{ |
|
struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev); |
|
|
|
tegra_pcm_platform_unregister(&pdev->dev); |
|
snd_soc_unregister_component(&pdev->dev); |
|
|
|
tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif); |
|
tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif); |
|
|
|
tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif); |
|
tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif); |
|
|
|
pm_runtime_disable(&pdev->dev); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct dev_pm_ops tegra30_i2s_pm_ops = { |
|
SET_RUNTIME_PM_OPS(tegra30_i2s_runtime_suspend, |
|
tegra30_i2s_runtime_resume, NULL) |
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
|
pm_runtime_force_resume) |
|
}; |
|
|
|
static struct platform_driver tegra30_i2s_driver = { |
|
.driver = { |
|
.name = DRV_NAME, |
|
.of_match_table = tegra30_i2s_of_match, |
|
.pm = &tegra30_i2s_pm_ops, |
|
}, |
|
.probe = tegra30_i2s_platform_probe, |
|
.remove = tegra30_i2s_platform_remove, |
|
}; |
|
module_platform_driver(tegra30_i2s_driver); |
|
|
|
MODULE_AUTHOR("Stephen Warren <[email protected]>"); |
|
MODULE_DESCRIPTION("Tegra30 I2S ASoC driver"); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_ALIAS("platform:" DRV_NAME); |
|
MODULE_DEVICE_TABLE(of, tegra30_i2s_of_match);
|
|
|