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603 lines
17 KiB
603 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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// |
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// tegra210_amx.c - Tegra210 AMX driver |
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// |
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// Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved. |
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#include <linux/clk.h> |
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#include <linux/device.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/regmap.h> |
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#include <sound/core.h> |
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#include <sound/pcm.h> |
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#include <sound/pcm_params.h> |
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#include <sound/soc.h> |
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#include "tegra210_amx.h" |
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#include "tegra_cif.h" |
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/* |
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* The counter is in terms of AHUB clock cycles. If a frame is not |
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* received within these clock cycles, the AMX input channel gets |
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* automatically disabled. For now the counter is calculated as a |
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* function of sample rate (8 kHz) and AHUB clock (49.152 MHz). |
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* If later an accurate number is needed, the counter needs to be |
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* calculated at runtime. |
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* |
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* count = ahub_clk / sample_rate |
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*/ |
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#define TEGRA194_MAX_FRAME_IDLE_COUNT 0x1800 |
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#define AMX_CH_REG(id, reg) ((reg) + ((id) * TEGRA210_AMX_AUDIOCIF_CH_STRIDE)) |
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static const struct reg_default tegra210_amx_reg_defaults[] = { |
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{ TEGRA210_AMX_RX_INT_MASK, 0x0000000f}, |
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{ TEGRA210_AMX_RX1_CIF_CTRL, 0x00007000}, |
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{ TEGRA210_AMX_RX2_CIF_CTRL, 0x00007000}, |
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{ TEGRA210_AMX_RX3_CIF_CTRL, 0x00007000}, |
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{ TEGRA210_AMX_RX4_CIF_CTRL, 0x00007000}, |
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{ TEGRA210_AMX_TX_INT_MASK, 0x00000001}, |
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{ TEGRA210_AMX_TX_CIF_CTRL, 0x00007000}, |
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{ TEGRA210_AMX_CG, 0x1}, |
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{ TEGRA210_AMX_CFG_RAM_CTRL, 0x00004000}, |
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}; |
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static void tegra210_amx_write_map_ram(struct tegra210_amx *amx) |
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{ |
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int i; |
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regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_CTRL, |
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TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN | |
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TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN | |
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TEGRA210_AMX_CFG_RAM_CTRL_RW_WRITE); |
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for (i = 0; i < TEGRA210_AMX_RAM_DEPTH; i++) |
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regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_DATA, |
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amx->map[i]); |
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regmap_write(amx->regmap, TEGRA210_AMX_OUT_BYTE_EN0, amx->byte_mask[0]); |
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regmap_write(amx->regmap, TEGRA210_AMX_OUT_BYTE_EN1, amx->byte_mask[1]); |
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} |
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static int tegra210_amx_startup(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct tegra210_amx *amx = snd_soc_dai_get_drvdata(dai); |
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unsigned int val; |
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int err; |
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/* Ensure if AMX is disabled */ |
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err = regmap_read_poll_timeout(amx->regmap, TEGRA210_AMX_STATUS, val, |
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!(val & 0x1), 10, 10000); |
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if (err < 0) { |
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dev_err(dai->dev, "failed to stop AMX, err = %d\n", err); |
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return err; |
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} |
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/* |
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* Soft Reset: Below performs module soft reset which clears |
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* all FSM logic, flushes flow control of FIFO and resets the |
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* state register. It also brings module back to disabled |
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* state (without flushing the data in the pipe). |
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*/ |
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regmap_update_bits(amx->regmap, TEGRA210_AMX_SOFT_RESET, |
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TEGRA210_AMX_SOFT_RESET_SOFT_RESET_MASK, |
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TEGRA210_AMX_SOFT_RESET_SOFT_EN); |
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err = regmap_read_poll_timeout(amx->regmap, TEGRA210_AMX_SOFT_RESET, |
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val, !(val & 0x1), 10, 10000); |
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if (err < 0) { |
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dev_err(dai->dev, "failed to reset AMX, err = %d\n", err); |
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return err; |
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} |
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return 0; |
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} |
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static int __maybe_unused tegra210_amx_runtime_suspend(struct device *dev) |
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{ |
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struct tegra210_amx *amx = dev_get_drvdata(dev); |
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regcache_cache_only(amx->regmap, true); |
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regcache_mark_dirty(amx->regmap); |
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return 0; |
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} |
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static int __maybe_unused tegra210_amx_runtime_resume(struct device *dev) |
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{ |
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struct tegra210_amx *amx = dev_get_drvdata(dev); |
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regcache_cache_only(amx->regmap, false); |
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regcache_sync(amx->regmap); |
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regmap_update_bits(amx->regmap, |
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TEGRA210_AMX_CTRL, |
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TEGRA210_AMX_CTRL_RX_DEP_MASK, |
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TEGRA210_AMX_WAIT_ON_ANY << TEGRA210_AMX_CTRL_RX_DEP_SHIFT); |
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tegra210_amx_write_map_ram(amx); |
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return 0; |
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} |
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static int tegra210_amx_set_audio_cif(struct snd_soc_dai *dai, |
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struct snd_pcm_hw_params *params, |
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unsigned int reg) |
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{ |
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struct tegra210_amx *amx = snd_soc_dai_get_drvdata(dai); |
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int channels, audio_bits; |
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struct tegra_cif_conf cif_conf; |
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memset(&cif_conf, 0, sizeof(struct tegra_cif_conf)); |
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channels = params_channels(params); |
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switch (params_format(params)) { |
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case SNDRV_PCM_FORMAT_S8: |
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audio_bits = TEGRA_ACIF_BITS_8; |
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break; |
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case SNDRV_PCM_FORMAT_S16_LE: |
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audio_bits = TEGRA_ACIF_BITS_16; |
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break; |
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case SNDRV_PCM_FORMAT_S32_LE: |
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audio_bits = TEGRA_ACIF_BITS_32; |
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break; |
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default: |
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return -EINVAL; |
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} |
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cif_conf.audio_ch = channels; |
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cif_conf.client_ch = channels; |
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cif_conf.audio_bits = audio_bits; |
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cif_conf.client_bits = audio_bits; |
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tegra_set_cif(amx->regmap, reg, &cif_conf); |
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return 0; |
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} |
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static int tegra210_amx_in_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *dai) |
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{ |
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struct tegra210_amx *amx = snd_soc_dai_get_drvdata(dai); |
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if (amx->soc_data->auto_disable) { |
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regmap_write(amx->regmap, |
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AMX_CH_REG(dai->id, TEGRA194_AMX_RX1_FRAME_PERIOD), |
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TEGRA194_MAX_FRAME_IDLE_COUNT); |
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regmap_write(amx->regmap, TEGRA210_AMX_CYA, 1); |
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} |
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return tegra210_amx_set_audio_cif(dai, params, |
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AMX_CH_REG(dai->id, TEGRA210_AMX_RX1_CIF_CTRL)); |
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} |
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static int tegra210_amx_out_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *dai) |
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{ |
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return tegra210_amx_set_audio_cif(dai, params, |
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TEGRA210_AMX_TX_CIF_CTRL); |
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} |
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static int tegra210_amx_get_byte_map(struct snd_kcontrol *kcontrol, |
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struct snd_ctl_elem_value *ucontrol) |
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{ |
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); |
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struct soc_mixer_control *mc = |
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(struct soc_mixer_control *)kcontrol->private_value; |
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struct tegra210_amx *amx = snd_soc_component_get_drvdata(cmpnt); |
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unsigned char *bytes_map = (unsigned char *)&amx->map; |
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int reg = mc->reg; |
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int enabled; |
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if (reg > 31) |
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enabled = amx->byte_mask[1] & (1 << (reg - 32)); |
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else |
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enabled = amx->byte_mask[0] & (1 << reg); |
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if (enabled) |
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ucontrol->value.integer.value[0] = bytes_map[reg]; |
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else |
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ucontrol->value.integer.value[0] = 0; |
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return 0; |
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} |
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static int tegra210_amx_put_byte_map(struct snd_kcontrol *kcontrol, |
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struct snd_ctl_elem_value *ucontrol) |
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{ |
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struct soc_mixer_control *mc = |
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(struct soc_mixer_control *)kcontrol->private_value; |
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); |
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struct tegra210_amx *amx = snd_soc_component_get_drvdata(cmpnt); |
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unsigned char *bytes_map = (unsigned char *)&amx->map; |
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int reg = mc->reg; |
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int value = ucontrol->value.integer.value[0]; |
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if (value == bytes_map[reg]) |
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return 0; |
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if (value >= 0 && value <= 255) { |
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/* Update byte map and enable slot */ |
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bytes_map[reg] = value; |
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if (reg > 31) |
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amx->byte_mask[1] |= (1 << (reg - 32)); |
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else |
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amx->byte_mask[0] |= (1 << reg); |
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} else { |
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/* Reset byte map and disable slot */ |
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bytes_map[reg] = 0; |
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if (reg > 31) |
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amx->byte_mask[1] &= ~(1 << (reg - 32)); |
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else |
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amx->byte_mask[0] &= ~(1 << reg); |
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} |
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return 1; |
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} |
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static const struct snd_soc_dai_ops tegra210_amx_out_dai_ops = { |
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.hw_params = tegra210_amx_out_hw_params, |
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.startup = tegra210_amx_startup, |
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}; |
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static const struct snd_soc_dai_ops tegra210_amx_in_dai_ops = { |
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.hw_params = tegra210_amx_in_hw_params, |
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}; |
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#define IN_DAI(id) \ |
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{ \ |
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.name = "AMX-RX-CIF" #id, \ |
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.playback = { \ |
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.stream_name = "RX" #id "-CIF-Playback",\ |
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.channels_min = 1, \ |
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.channels_max = 16, \ |
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.rates = SNDRV_PCM_RATE_8000_192000, \ |
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.formats = SNDRV_PCM_FMTBIT_S8 | \ |
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SNDRV_PCM_FMTBIT_S16_LE | \ |
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SNDRV_PCM_FMTBIT_S32_LE, \ |
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}, \ |
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.capture = { \ |
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.stream_name = "RX" #id "-CIF-Capture", \ |
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.channels_min = 1, \ |
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.channels_max = 16, \ |
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.rates = SNDRV_PCM_RATE_8000_192000, \ |
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.formats = SNDRV_PCM_FMTBIT_S8 | \ |
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SNDRV_PCM_FMTBIT_S16_LE | \ |
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SNDRV_PCM_FMTBIT_S32_LE, \ |
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}, \ |
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.ops = &tegra210_amx_in_dai_ops, \ |
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} |
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#define OUT_DAI \ |
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{ \ |
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.name = "AMX-TX-CIF", \ |
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.playback = { \ |
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.stream_name = "TX-CIF-Playback", \ |
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.channels_min = 1, \ |
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.channels_max = 16, \ |
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.rates = SNDRV_PCM_RATE_8000_192000, \ |
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.formats = SNDRV_PCM_FMTBIT_S8 | \ |
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SNDRV_PCM_FMTBIT_S16_LE | \ |
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SNDRV_PCM_FMTBIT_S32_LE, \ |
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}, \ |
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.capture = { \ |
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.stream_name = "TX-CIF-Capture", \ |
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.channels_min = 1, \ |
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.channels_max = 16, \ |
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.rates = SNDRV_PCM_RATE_8000_192000, \ |
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.formats = SNDRV_PCM_FMTBIT_S8 | \ |
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SNDRV_PCM_FMTBIT_S16_LE | \ |
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SNDRV_PCM_FMTBIT_S32_LE, \ |
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}, \ |
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.ops = &tegra210_amx_out_dai_ops, \ |
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} |
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static struct snd_soc_dai_driver tegra210_amx_dais[] = { |
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IN_DAI(1), |
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IN_DAI(2), |
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IN_DAI(3), |
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IN_DAI(4), |
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OUT_DAI, |
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}; |
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static const struct snd_soc_dapm_widget tegra210_amx_widgets[] = { |
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SND_SOC_DAPM_AIF_IN("RX1", NULL, 0, TEGRA210_AMX_CTRL, 0, 0), |
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SND_SOC_DAPM_AIF_IN("RX2", NULL, 0, TEGRA210_AMX_CTRL, 1, 0), |
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SND_SOC_DAPM_AIF_IN("RX3", NULL, 0, TEGRA210_AMX_CTRL, 2, 0), |
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SND_SOC_DAPM_AIF_IN("RX4", NULL, 0, TEGRA210_AMX_CTRL, 3, 0), |
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SND_SOC_DAPM_AIF_OUT("TX", NULL, 0, TEGRA210_AMX_ENABLE, |
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TEGRA210_AMX_ENABLE_SHIFT, 0), |
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}; |
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#define STREAM_ROUTES(id, sname) \ |
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{ "RX" #id " XBAR-" sname, NULL, "RX" #id " XBAR-TX" }, \ |
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{ "RX" #id "-CIF-" sname, NULL, "RX" #id " XBAR-" sname },\ |
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{ "RX" #id, NULL, "RX" #id "-CIF-" sname }, \ |
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{ "TX", NULL, "RX" #id }, \ |
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{ "TX-CIF-" sname, NULL, "TX" }, \ |
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{ "XBAR-" sname, NULL, "TX-CIF-" sname }, \ |
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{ "XBAR-RX", NULL, "XBAR-" sname } |
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#define AMX_ROUTES(id) \ |
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STREAM_ROUTES(id, "Playback"), \ |
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STREAM_ROUTES(id, "Capture") |
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static const struct snd_soc_dapm_route tegra210_amx_routes[] = { |
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AMX_ROUTES(1), |
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AMX_ROUTES(2), |
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AMX_ROUTES(3), |
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AMX_ROUTES(4), |
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}; |
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#define TEGRA210_AMX_BYTE_MAP_CTRL(reg) \ |
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SOC_SINGLE_EXT("Byte Map " #reg, reg, 0, 256, 0, \ |
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tegra210_amx_get_byte_map, \ |
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tegra210_amx_put_byte_map) |
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static struct snd_kcontrol_new tegra210_amx_controls[] = { |
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TEGRA210_AMX_BYTE_MAP_CTRL(0), |
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TEGRA210_AMX_BYTE_MAP_CTRL(1), |
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TEGRA210_AMX_BYTE_MAP_CTRL(2), |
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TEGRA210_AMX_BYTE_MAP_CTRL(3), |
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TEGRA210_AMX_BYTE_MAP_CTRL(4), |
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TEGRA210_AMX_BYTE_MAP_CTRL(5), |
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TEGRA210_AMX_BYTE_MAP_CTRL(6), |
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TEGRA210_AMX_BYTE_MAP_CTRL(7), |
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TEGRA210_AMX_BYTE_MAP_CTRL(8), |
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TEGRA210_AMX_BYTE_MAP_CTRL(9), |
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TEGRA210_AMX_BYTE_MAP_CTRL(10), |
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TEGRA210_AMX_BYTE_MAP_CTRL(11), |
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TEGRA210_AMX_BYTE_MAP_CTRL(12), |
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TEGRA210_AMX_BYTE_MAP_CTRL(13), |
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TEGRA210_AMX_BYTE_MAP_CTRL(14), |
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TEGRA210_AMX_BYTE_MAP_CTRL(15), |
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TEGRA210_AMX_BYTE_MAP_CTRL(16), |
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TEGRA210_AMX_BYTE_MAP_CTRL(17), |
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TEGRA210_AMX_BYTE_MAP_CTRL(18), |
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TEGRA210_AMX_BYTE_MAP_CTRL(19), |
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TEGRA210_AMX_BYTE_MAP_CTRL(20), |
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TEGRA210_AMX_BYTE_MAP_CTRL(21), |
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TEGRA210_AMX_BYTE_MAP_CTRL(22), |
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TEGRA210_AMX_BYTE_MAP_CTRL(23), |
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TEGRA210_AMX_BYTE_MAP_CTRL(24), |
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TEGRA210_AMX_BYTE_MAP_CTRL(25), |
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TEGRA210_AMX_BYTE_MAP_CTRL(26), |
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TEGRA210_AMX_BYTE_MAP_CTRL(27), |
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TEGRA210_AMX_BYTE_MAP_CTRL(28), |
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TEGRA210_AMX_BYTE_MAP_CTRL(29), |
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TEGRA210_AMX_BYTE_MAP_CTRL(30), |
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TEGRA210_AMX_BYTE_MAP_CTRL(31), |
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TEGRA210_AMX_BYTE_MAP_CTRL(32), |
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TEGRA210_AMX_BYTE_MAP_CTRL(33), |
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TEGRA210_AMX_BYTE_MAP_CTRL(34), |
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TEGRA210_AMX_BYTE_MAP_CTRL(35), |
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TEGRA210_AMX_BYTE_MAP_CTRL(36), |
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TEGRA210_AMX_BYTE_MAP_CTRL(37), |
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TEGRA210_AMX_BYTE_MAP_CTRL(38), |
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TEGRA210_AMX_BYTE_MAP_CTRL(39), |
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TEGRA210_AMX_BYTE_MAP_CTRL(40), |
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TEGRA210_AMX_BYTE_MAP_CTRL(41), |
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TEGRA210_AMX_BYTE_MAP_CTRL(42), |
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TEGRA210_AMX_BYTE_MAP_CTRL(43), |
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TEGRA210_AMX_BYTE_MAP_CTRL(44), |
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TEGRA210_AMX_BYTE_MAP_CTRL(45), |
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TEGRA210_AMX_BYTE_MAP_CTRL(46), |
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TEGRA210_AMX_BYTE_MAP_CTRL(47), |
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TEGRA210_AMX_BYTE_MAP_CTRL(48), |
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TEGRA210_AMX_BYTE_MAP_CTRL(49), |
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TEGRA210_AMX_BYTE_MAP_CTRL(50), |
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TEGRA210_AMX_BYTE_MAP_CTRL(51), |
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TEGRA210_AMX_BYTE_MAP_CTRL(52), |
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TEGRA210_AMX_BYTE_MAP_CTRL(53), |
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TEGRA210_AMX_BYTE_MAP_CTRL(54), |
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TEGRA210_AMX_BYTE_MAP_CTRL(55), |
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TEGRA210_AMX_BYTE_MAP_CTRL(56), |
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TEGRA210_AMX_BYTE_MAP_CTRL(57), |
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TEGRA210_AMX_BYTE_MAP_CTRL(58), |
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TEGRA210_AMX_BYTE_MAP_CTRL(59), |
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TEGRA210_AMX_BYTE_MAP_CTRL(60), |
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TEGRA210_AMX_BYTE_MAP_CTRL(61), |
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TEGRA210_AMX_BYTE_MAP_CTRL(62), |
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TEGRA210_AMX_BYTE_MAP_CTRL(63), |
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}; |
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static const struct snd_soc_component_driver tegra210_amx_cmpnt = { |
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.dapm_widgets = tegra210_amx_widgets, |
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.num_dapm_widgets = ARRAY_SIZE(tegra210_amx_widgets), |
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.dapm_routes = tegra210_amx_routes, |
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.num_dapm_routes = ARRAY_SIZE(tegra210_amx_routes), |
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.controls = tegra210_amx_controls, |
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.num_controls = ARRAY_SIZE(tegra210_amx_controls), |
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}; |
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static bool tegra210_amx_wr_reg(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case TEGRA210_AMX_RX_INT_MASK ... TEGRA210_AMX_RX4_CIF_CTRL: |
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case TEGRA210_AMX_TX_INT_MASK ... TEGRA210_AMX_CG: |
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case TEGRA210_AMX_CTRL ... TEGRA210_AMX_CYA: |
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case TEGRA210_AMX_CFG_RAM_CTRL ... TEGRA210_AMX_CFG_RAM_DATA: |
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return true; |
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default: |
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return false; |
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} |
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} |
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static bool tegra194_amx_wr_reg(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case TEGRA194_AMX_RX1_FRAME_PERIOD ... TEGRA194_AMX_RX4_FRAME_PERIOD: |
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return true; |
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default: |
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return tegra210_amx_wr_reg(dev, reg); |
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} |
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} |
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static bool tegra210_amx_rd_reg(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case TEGRA210_AMX_RX_STATUS ... TEGRA210_AMX_CFG_RAM_DATA: |
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return true; |
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default: |
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return false; |
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} |
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} |
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static bool tegra194_amx_rd_reg(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case TEGRA194_AMX_RX1_FRAME_PERIOD ... TEGRA194_AMX_RX4_FRAME_PERIOD: |
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return true; |
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default: |
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return tegra210_amx_rd_reg(dev, reg); |
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} |
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} |
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|
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static bool tegra210_amx_volatile_reg(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case TEGRA210_AMX_RX_STATUS: |
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case TEGRA210_AMX_RX_INT_STATUS: |
|
case TEGRA210_AMX_RX_INT_SET: |
|
case TEGRA210_AMX_TX_STATUS: |
|
case TEGRA210_AMX_TX_INT_STATUS: |
|
case TEGRA210_AMX_TX_INT_SET: |
|
case TEGRA210_AMX_SOFT_RESET: |
|
case TEGRA210_AMX_STATUS: |
|
case TEGRA210_AMX_INT_STATUS: |
|
case TEGRA210_AMX_CFG_RAM_CTRL: |
|
case TEGRA210_AMX_CFG_RAM_DATA: |
|
return true; |
|
default: |
|
break; |
|
} |
|
|
|
return false; |
|
} |
|
|
|
static const struct regmap_config tegra210_amx_regmap_config = { |
|
.reg_bits = 32, |
|
.reg_stride = 4, |
|
.val_bits = 32, |
|
.max_register = TEGRA210_AMX_CFG_RAM_DATA, |
|
.writeable_reg = tegra210_amx_wr_reg, |
|
.readable_reg = tegra210_amx_rd_reg, |
|
.volatile_reg = tegra210_amx_volatile_reg, |
|
.reg_defaults = tegra210_amx_reg_defaults, |
|
.num_reg_defaults = ARRAY_SIZE(tegra210_amx_reg_defaults), |
|
.cache_type = REGCACHE_FLAT, |
|
}; |
|
|
|
static const struct regmap_config tegra194_amx_regmap_config = { |
|
.reg_bits = 32, |
|
.reg_stride = 4, |
|
.val_bits = 32, |
|
.max_register = TEGRA194_AMX_RX4_LAST_FRAME_PERIOD, |
|
.writeable_reg = tegra194_amx_wr_reg, |
|
.readable_reg = tegra194_amx_rd_reg, |
|
.volatile_reg = tegra210_amx_volatile_reg, |
|
.reg_defaults = tegra210_amx_reg_defaults, |
|
.num_reg_defaults = ARRAY_SIZE(tegra210_amx_reg_defaults), |
|
.cache_type = REGCACHE_FLAT, |
|
}; |
|
|
|
static const struct tegra210_amx_soc_data soc_data_tegra210 = { |
|
.regmap_conf = &tegra210_amx_regmap_config, |
|
}; |
|
|
|
static const struct tegra210_amx_soc_data soc_data_tegra194 = { |
|
.regmap_conf = &tegra194_amx_regmap_config, |
|
.auto_disable = true, |
|
}; |
|
|
|
static const struct of_device_id tegra210_amx_of_match[] = { |
|
{ .compatible = "nvidia,tegra210-amx", .data = &soc_data_tegra210 }, |
|
{ .compatible = "nvidia,tegra194-amx", .data = &soc_data_tegra194 }, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, tegra210_amx_of_match); |
|
|
|
static int tegra210_amx_platform_probe(struct platform_device *pdev) |
|
{ |
|
struct device *dev = &pdev->dev; |
|
struct tegra210_amx *amx; |
|
void __iomem *regs; |
|
int err; |
|
const struct of_device_id *match; |
|
struct tegra210_amx_soc_data *soc_data; |
|
|
|
match = of_match_device(tegra210_amx_of_match, dev); |
|
|
|
soc_data = (struct tegra210_amx_soc_data *)match->data; |
|
|
|
amx = devm_kzalloc(dev, sizeof(*amx), GFP_KERNEL); |
|
if (!amx) |
|
return -ENOMEM; |
|
|
|
amx->soc_data = soc_data; |
|
|
|
dev_set_drvdata(dev, amx); |
|
|
|
regs = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(regs)) |
|
return PTR_ERR(regs); |
|
|
|
amx->regmap = devm_regmap_init_mmio(dev, regs, |
|
soc_data->regmap_conf); |
|
if (IS_ERR(amx->regmap)) { |
|
dev_err(dev, "regmap init failed\n"); |
|
return PTR_ERR(amx->regmap); |
|
} |
|
|
|
regcache_cache_only(amx->regmap, true); |
|
|
|
err = devm_snd_soc_register_component(dev, &tegra210_amx_cmpnt, |
|
tegra210_amx_dais, |
|
ARRAY_SIZE(tegra210_amx_dais)); |
|
if (err) { |
|
dev_err(dev, "can't register AMX component, err: %d\n", err); |
|
return err; |
|
} |
|
|
|
pm_runtime_enable(dev); |
|
|
|
return 0; |
|
} |
|
|
|
static int tegra210_amx_platform_remove(struct platform_device *pdev) |
|
{ |
|
pm_runtime_disable(&pdev->dev); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct dev_pm_ops tegra210_amx_pm_ops = { |
|
SET_RUNTIME_PM_OPS(tegra210_amx_runtime_suspend, |
|
tegra210_amx_runtime_resume, NULL) |
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
|
pm_runtime_force_resume) |
|
}; |
|
|
|
static struct platform_driver tegra210_amx_driver = { |
|
.driver = { |
|
.name = "tegra210-amx", |
|
.of_match_table = tegra210_amx_of_match, |
|
.pm = &tegra210_amx_pm_ops, |
|
}, |
|
.probe = tegra210_amx_platform_probe, |
|
.remove = tegra210_amx_platform_remove, |
|
}; |
|
module_platform_driver(tegra210_amx_driver); |
|
|
|
MODULE_AUTHOR("Songhee Baek <[email protected]>"); |
|
MODULE_DESCRIPTION("Tegra210 AMX ASoC driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|