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112 lines
4.5 KiB
112 lines
4.5 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* tegra186_asrc.h - Definitions for Tegra186 ASRC driver |
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* |
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* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. |
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* |
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*/ |
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#ifndef __TEGRA186_ASRC_H__ |
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#define __TEGRA186_ASRC_H__ |
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/* ASRC stream related offset */ |
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#define TEGRA186_ASRC_CFG 0x0 |
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#define TEGRA186_ASRC_RATIO_INT_PART 0x4 |
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#define TEGRA186_ASRC_RATIO_FRAC_PART 0x8 |
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#define TEGRA186_ASRC_RATIO_LOCK_STATUS 0xc |
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#define TEGRA186_ASRC_MUTE_UNMUTE_DURATION 0x10 |
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#define TEGRA186_ASRC_TX_THRESHOLD 0x14 |
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#define TEGRA186_ASRC_RX_THRESHOLD 0x18 |
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#define TEGRA186_ASRC_RATIO_COMP 0x1c |
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#define TEGRA186_ASRC_RX_STATUS 0x20 |
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#define TEGRA186_ASRC_RX_CIF_CTRL 0x24 |
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#define TEGRA186_ASRC_TX_STATUS 0x2c |
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#define TEGRA186_ASRC_TX_CIF_CTRL 0x30 |
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#define TEGRA186_ASRC_ENABLE 0x38 |
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#define TEGRA186_ASRC_SOFT_RESET 0x3c |
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#define TEGRA186_ASRC_STATUS 0x4c |
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#define TEGRA186_ASRC_STATEBUF_ADDR 0x5c |
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#define TEGRA186_ASRC_STATEBUF_CFG 0x60 |
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#define TEGRA186_ASRC_INSAMPLEBUF_ADDR 0x64 |
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#define TEGRA186_ASRC_INSAMPLEBUF_CFG 0x68 |
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#define TEGRA186_ASRC_OUTSAMPLEBUF_ADDR 0x6c |
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#define TEGRA186_ASRC_OUTSAMPLEBUF_CFG 0x70 |
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/* ASRC Global registers offset */ |
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#define TEGRA186_ASRC_GLOBAL_ENB 0x2f4 |
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#define TEGRA186_ASRC_GLOBAL_SOFT_RESET 0x2f8 |
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#define TEGRA186_ASRC_GLOBAL_CG 0x2fc |
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#define TEGRA186_ASRC_GLOBAL_CFG 0x300 |
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#define TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR 0x304 |
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#define TEGRA186_ASRC_GLOBAL_SCRATCH_CFG 0x308 |
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#define TEGRA186_ASRC_RATIO_UPD_RX_CIF_CTRL 0x30c |
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#define TEGRA186_ASRC_RATIO_UPD_RX_STATUS 0x310 |
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#define TEGRA186_ASRC_GLOBAL_STATUS 0x314 |
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#define TEGRA186_ASRC_GLOBAL_STREAM_ENABLE_STATUS 0x318 |
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#define TEGRA186_ASRC_GLOBAL_INT_STATUS 0x324 |
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#define TEGRA186_ASRC_GLOBAL_INT_MASK 0x328 |
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#define TEGRA186_ASRC_GLOBAL_INT_SET 0x32c |
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#define TEGRA186_ASRC_GLOBAL_INT_CLEAR 0x330 |
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#define TEGRA186_ASRC_GLOBAL_TRANSFER_ERROR_LOG 0x334 |
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#define TEGRA186_ASRC_GLOBAL_APR_CTRL 0x1000 |
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#define TEGRA186_ASRC_GLOBAL_APR_CTRL_ACCESS_CTRL 0x1004 |
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#define TEGRA186_ASRC_GLOBAL_DISARM_APR 0x1008 |
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#define TEGRA186_ASRC_GLOBAL_DISARM_APR_ACCESS_CTRL 0x100c |
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#define TEGRA186_ASRC_GLOBAL_RATIO_WR_ACCESS 0x1010 |
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#define TEGRA186_ASRC_GLOBAL_RATIO_WR_ACCESS_CTRL 0x1014 |
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#define TEGRA186_ASRC_CYA 0x1018 |
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#define TEGRA186_ASRC_STREAM_DEFAULT_HW_COMP_BIAS_VALUE 0xaaaa |
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#define TEGRA186_ASRC_STREAM_DEFAULT_INPUT_HW_COMP_THRESH_CFG 0x00201002 |
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#define TEGRA186_ASRC_STREAM_DEFAULT_OUTPUT_HW_COMP_THRESH_CFG 0x00201002 |
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#define TEGRA186_ASRC_GLOBAL_CFG_FRAC_28BIT_PRECISION 0 |
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#define TEGRA186_ASRC_GLOBAL_CFG_FRAC_32BIT_PRECISION 1 |
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#define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT 31 |
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#define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_MASK (1 << TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT) |
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#define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_ENABLE (1 << TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT) |
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#define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_DISABLE (0 << TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT) |
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#define TEGRA186_ASRC_STREAM_RATIO_TYPE_SHIFT 0 |
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#define TEGRA186_ASRC_STREAM_RATIO_TYPE_MASK (1 << TEGRA186_ASRC_STREAM_RATIO_TYPE_SHIFT) |
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#define TEGRA186_ASRC_STREAM_EN_SHIFT 0 |
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#define TEGRA186_ASRC_STREAM_EN (1 << TEGRA186_ASRC_STREAM_EN_SHIFT) |
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#define TEGRA186_ASRC_GLOBAL_EN_SHIFT 0 |
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#define TEGRA186_ASRC_GLOBAL_EN (1 << TEGRA186_ASRC_GLOBAL_EN_SHIFT) |
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#define TEGRA186_ASRC_STREAM_STATEBUF_CFG_SIZE_SHIFT 0 |
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#define TEGRA186_ASRC_STREAM_STATEBUF_CFG_SIZE_MASK (0xffff << TEGRA186_ASRC_STREAM_STATEBUF_CFG_SIZE_SHIFT) |
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#define TEGRA186_ASRC_STREAM_INSAMPLEBUF_CFG_SIZE_SHIFT 0 |
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#define TEGRA186_ASRC_STREAM_INSAMPLEBUF_CFG_SIZE_MASK (0xffff << TEGRA186_ASRC_STREAM_INSAMPLEBUF_CFG_SIZE_SHIFT) |
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#define TEGRA186_ASRC_STREAM_OUTSAMPLEBUF_CFG_SIZE_SHIFT 0 |
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#define TEGRA186_ASRC_STREAM_OUTSAMPLEBUF_CFG_SIZE_MASK (0xffff << TEGRA186_ASRC_STREAM_OUTSAMPLEBUF_CFG_SIZE_SHIFT) |
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#define TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK 0x1f |
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#define TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK 0xffffffff |
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#define TEGRA186_ASRC_STREAM_STRIDE 0x80 |
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#define TEGRA186_ASRC_STREAM_MAX 0x6 |
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#define TEGRA186_ASRC_STREAM_LIMIT 0x2f0 |
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#define TEGRA186_ASRC_RATIO_SOURCE_ARAD 0x0 |
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#define TEGRA186_ASRC_RATIO_SOURCE_SW 0x1 |
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#define TEGRA186_ASRC_ARAM_START_ADDR 0x3f800000 |
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struct tegra186_asrc_lane { |
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unsigned int int_part; |
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unsigned int frac_part; |
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unsigned int ratio_source; |
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unsigned int hwcomp_disable; |
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unsigned int input_thresh; |
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unsigned int output_thresh; |
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}; |
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struct tegra186_asrc { |
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struct tegra186_asrc_lane lane[TEGRA186_ASRC_STREAM_MAX]; |
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struct regmap *regmap; |
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}; |
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#endif
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