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435 lines
11 KiB
435 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* SiRF USP in I2S/DSP mode |
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* |
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. |
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*/ |
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#include <linux/module.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/clk.h> |
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#include <linux/pm_runtime.h> |
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#include <sound/soc.h> |
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#include <sound/pcm_params.h> |
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#include <sound/dmaengine_pcm.h> |
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#include "sirf-usp.h" |
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struct sirf_usp { |
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struct regmap *regmap; |
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struct clk *clk; |
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u32 mode1_reg; |
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u32 mode2_reg; |
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int daifmt_format; |
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struct snd_dmaengine_dai_dma_data playback_dma_data; |
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struct snd_dmaengine_dai_dma_data capture_dma_data; |
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}; |
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static void sirf_usp_tx_enable(struct sirf_usp *usp) |
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{ |
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regmap_update_bits(usp->regmap, USP_TX_FIFO_OP, |
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USP_TX_FIFO_RESET, USP_TX_FIFO_RESET); |
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regmap_write(usp->regmap, USP_TX_FIFO_OP, 0); |
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regmap_update_bits(usp->regmap, USP_TX_FIFO_OP, |
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USP_TX_FIFO_START, USP_TX_FIFO_START); |
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regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE, |
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USP_TX_ENA, USP_TX_ENA); |
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} |
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static void sirf_usp_tx_disable(struct sirf_usp *usp) |
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{ |
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regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE, |
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USP_TX_ENA, ~USP_TX_ENA); |
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/* FIFO stop */ |
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regmap_write(usp->regmap, USP_TX_FIFO_OP, 0); |
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} |
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static void sirf_usp_rx_enable(struct sirf_usp *usp) |
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{ |
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regmap_update_bits(usp->regmap, USP_RX_FIFO_OP, |
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USP_RX_FIFO_RESET, USP_RX_FIFO_RESET); |
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regmap_write(usp->regmap, USP_RX_FIFO_OP, 0); |
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regmap_update_bits(usp->regmap, USP_RX_FIFO_OP, |
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USP_RX_FIFO_START, USP_RX_FIFO_START); |
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regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE, |
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USP_RX_ENA, USP_RX_ENA); |
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} |
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static void sirf_usp_rx_disable(struct sirf_usp *usp) |
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{ |
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regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE, |
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USP_RX_ENA, ~USP_RX_ENA); |
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/* FIFO stop */ |
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regmap_write(usp->regmap, USP_RX_FIFO_OP, 0); |
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} |
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static int sirf_usp_pcm_dai_probe(struct snd_soc_dai *dai) |
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{ |
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struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai); |
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snd_soc_dai_init_dma_data(dai, &usp->playback_dma_data, |
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&usp->capture_dma_data); |
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return 0; |
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} |
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static int sirf_usp_pcm_set_dai_fmt(struct snd_soc_dai *dai, |
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unsigned int fmt) |
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{ |
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struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai); |
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/* set master/slave audio interface */ |
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
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case SND_SOC_DAIFMT_CBM_CFM: |
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break; |
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default: |
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dev_err(dai->dev, "Only CBM and CFM supported\n"); |
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return -EINVAL; |
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} |
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
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case SND_SOC_DAIFMT_I2S: |
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case SND_SOC_DAIFMT_DSP_A: |
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usp->daifmt_format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK); |
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break; |
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default: |
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dev_err(dai->dev, "Only I2S and DSP_A format supported\n"); |
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return -EINVAL; |
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} |
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
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case SND_SOC_DAIFMT_NB_NF: |
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break; |
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case SND_SOC_DAIFMT_IB_NF: |
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usp->daifmt_format |= (fmt & SND_SOC_DAIFMT_INV_MASK); |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static void sirf_usp_i2s_init(struct sirf_usp *usp) |
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{ |
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/* Configure RISC mode */ |
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regmap_update_bits(usp->regmap, USP_RISC_DSP_MODE, |
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USP_RISC_DSP_SEL, ~USP_RISC_DSP_SEL); |
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/* |
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* Configure DMA IO Length register |
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* Set no limit, USP can receive data continuously until it is diabled |
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*/ |
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regmap_write(usp->regmap, USP_TX_DMA_IO_LEN, 0); |
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regmap_write(usp->regmap, USP_RX_DMA_IO_LEN, 0); |
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/* Configure Mode2 register */ |
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regmap_write(usp->regmap, USP_MODE2, (1 << USP_RXD_DELAY_LEN_OFFSET) | |
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(0 << USP_TXD_DELAY_LEN_OFFSET) | |
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USP_TFS_CLK_SLAVE_MODE | USP_RFS_CLK_SLAVE_MODE); |
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/* Configure Mode1 register */ |
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regmap_write(usp->regmap, USP_MODE1, |
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USP_SYNC_MODE | USP_EN | USP_TXD_ACT_EDGE_FALLING | |
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USP_RFS_ACT_LEVEL_LOGIC1 | USP_TFS_ACT_LEVEL_LOGIC1 | |
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USP_TX_UFLOW_REPEAT_ZERO | USP_CLOCK_MODE_SLAVE); |
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/* Configure RX DMA IO Control register */ |
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regmap_write(usp->regmap, USP_RX_DMA_IO_CTRL, 0); |
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/* Congiure RX FIFO Control register */ |
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regmap_write(usp->regmap, USP_RX_FIFO_CTRL, |
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(USP_RX_FIFO_THRESHOLD << USP_RX_FIFO_THD_OFFSET) | |
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(USP_TX_RX_FIFO_WIDTH_DWORD << USP_RX_FIFO_WIDTH_OFFSET)); |
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/* Congiure RX FIFO Level Check register */ |
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regmap_write(usp->regmap, USP_RX_FIFO_LEVEL_CHK, |
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RX_FIFO_SC(0x04) | RX_FIFO_LC(0x0E) | RX_FIFO_HC(0x1B)); |
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/* Configure TX DMA IO Control register*/ |
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regmap_write(usp->regmap, USP_TX_DMA_IO_CTRL, 0); |
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/* Configure TX FIFO Control register */ |
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regmap_write(usp->regmap, USP_TX_FIFO_CTRL, |
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(USP_TX_FIFO_THRESHOLD << USP_TX_FIFO_THD_OFFSET) | |
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(USP_TX_RX_FIFO_WIDTH_DWORD << USP_TX_FIFO_WIDTH_OFFSET)); |
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/* Congiure TX FIFO Level Check register */ |
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regmap_write(usp->regmap, USP_TX_FIFO_LEVEL_CHK, |
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TX_FIFO_SC(0x1B) | TX_FIFO_LC(0x0E) | TX_FIFO_HC(0x04)); |
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} |
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static int sirf_usp_pcm_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) |
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{ |
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struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai); |
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u32 data_len, frame_len, shifter_len; |
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switch (params_format(params)) { |
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case SNDRV_PCM_FORMAT_S16_LE: |
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data_len = 16; |
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frame_len = 16; |
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break; |
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case SNDRV_PCM_FORMAT_S24_LE: |
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data_len = 24; |
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frame_len = 32; |
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break; |
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case SNDRV_PCM_FORMAT_S24_3LE: |
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data_len = 24; |
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frame_len = 24; |
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break; |
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default: |
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dev_err(dai->dev, "Format unsupported\n"); |
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return -EINVAL; |
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} |
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shifter_len = data_len; |
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switch (usp->daifmt_format & SND_SOC_DAIFMT_FORMAT_MASK) { |
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case SND_SOC_DAIFMT_I2S: |
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regmap_update_bits(usp->regmap, USP_RX_FRAME_CTRL, |
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USP_I2S_SYNC_CHG, USP_I2S_SYNC_CHG); |
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break; |
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case SND_SOC_DAIFMT_DSP_A: |
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regmap_update_bits(usp->regmap, USP_RX_FRAME_CTRL, |
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USP_I2S_SYNC_CHG, 0); |
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frame_len = data_len * params_channels(params); |
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data_len = frame_len; |
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break; |
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default: |
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dev_err(dai->dev, "Only support I2S and DSP_A mode\n"); |
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return -EINVAL; |
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} |
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switch (usp->daifmt_format & SND_SOC_DAIFMT_INV_MASK) { |
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case SND_SOC_DAIFMT_NB_NF: |
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break; |
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case SND_SOC_DAIFMT_IB_NF: |
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regmap_update_bits(usp->regmap, USP_MODE1, |
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USP_RXD_ACT_EDGE_FALLING | USP_TXD_ACT_EDGE_FALLING, |
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USP_RXD_ACT_EDGE_FALLING); |
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break; |
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default: |
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return -EINVAL; |
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} |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
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regmap_update_bits(usp->regmap, USP_TX_FRAME_CTRL, |
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USP_TXC_DATA_LEN_MASK | USP_TXC_FRAME_LEN_MASK |
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| USP_TXC_SHIFTER_LEN_MASK | USP_TXC_SLAVE_CLK_SAMPLE, |
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((data_len - 1) << USP_TXC_DATA_LEN_OFFSET) |
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| ((frame_len - 1) << USP_TXC_FRAME_LEN_OFFSET) |
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| ((shifter_len - 1) << USP_TXC_SHIFTER_LEN_OFFSET) |
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| USP_TXC_SLAVE_CLK_SAMPLE); |
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else |
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regmap_update_bits(usp->regmap, USP_RX_FRAME_CTRL, |
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USP_RXC_DATA_LEN_MASK | USP_RXC_FRAME_LEN_MASK |
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| USP_RXC_SHIFTER_LEN_MASK | USP_SINGLE_SYNC_MODE, |
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((data_len - 1) << USP_RXC_DATA_LEN_OFFSET) |
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| ((frame_len - 1) << USP_RXC_FRAME_LEN_OFFSET) |
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| ((shifter_len - 1) << USP_RXC_SHIFTER_LEN_OFFSET) |
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| USP_SINGLE_SYNC_MODE); |
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return 0; |
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} |
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static int sirf_usp_pcm_trigger(struct snd_pcm_substream *substream, int cmd, |
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struct snd_soc_dai *dai) |
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{ |
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struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai); |
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switch (cmd) { |
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case SNDRV_PCM_TRIGGER_START: |
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case SNDRV_PCM_TRIGGER_RESUME: |
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
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sirf_usp_tx_enable(usp); |
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else |
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sirf_usp_rx_enable(usp); |
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break; |
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case SNDRV_PCM_TRIGGER_STOP: |
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case SNDRV_PCM_TRIGGER_SUSPEND: |
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
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sirf_usp_tx_disable(usp); |
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else |
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sirf_usp_rx_disable(usp); |
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break; |
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} |
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return 0; |
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} |
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static const struct snd_soc_dai_ops sirf_usp_pcm_dai_ops = { |
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.trigger = sirf_usp_pcm_trigger, |
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.set_fmt = sirf_usp_pcm_set_dai_fmt, |
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.hw_params = sirf_usp_pcm_hw_params, |
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}; |
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static struct snd_soc_dai_driver sirf_usp_pcm_dai = { |
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.probe = sirf_usp_pcm_dai_probe, |
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.name = "sirf-usp-pcm", |
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.id = 0, |
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.playback = { |
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.stream_name = "SiRF USP PCM Playback", |
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.channels_min = 1, |
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.channels_max = 2, |
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.rates = SNDRV_PCM_RATE_8000_192000, |
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.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | |
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SNDRV_PCM_FMTBIT_S24_3LE, |
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}, |
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.capture = { |
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.stream_name = "SiRF USP PCM Capture", |
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.channels_min = 1, |
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.channels_max = 2, |
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.rates = SNDRV_PCM_RATE_8000_192000, |
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.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | |
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SNDRV_PCM_FMTBIT_S24_3LE, |
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}, |
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.ops = &sirf_usp_pcm_dai_ops, |
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}; |
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static int sirf_usp_pcm_runtime_suspend(struct device *dev) |
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{ |
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struct sirf_usp *usp = dev_get_drvdata(dev); |
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clk_disable_unprepare(usp->clk); |
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return 0; |
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} |
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static int sirf_usp_pcm_runtime_resume(struct device *dev) |
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{ |
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struct sirf_usp *usp = dev_get_drvdata(dev); |
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int ret; |
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ret = clk_prepare_enable(usp->clk); |
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if (ret) { |
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dev_err(dev, "clk_enable failed: %d\n", ret); |
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return ret; |
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} |
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sirf_usp_i2s_init(usp); |
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return 0; |
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} |
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#ifdef CONFIG_PM_SLEEP |
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static int sirf_usp_pcm_suspend(struct device *dev) |
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{ |
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struct sirf_usp *usp = dev_get_drvdata(dev); |
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if (!pm_runtime_status_suspended(dev)) { |
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regmap_read(usp->regmap, USP_MODE1, &usp->mode1_reg); |
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regmap_read(usp->regmap, USP_MODE2, &usp->mode2_reg); |
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sirf_usp_pcm_runtime_suspend(dev); |
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} |
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return 0; |
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} |
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static int sirf_usp_pcm_resume(struct device *dev) |
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{ |
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struct sirf_usp *usp = dev_get_drvdata(dev); |
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int ret; |
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if (!pm_runtime_status_suspended(dev)) { |
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ret = sirf_usp_pcm_runtime_resume(dev); |
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if (ret) |
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return ret; |
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regmap_write(usp->regmap, USP_MODE1, usp->mode1_reg); |
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regmap_write(usp->regmap, USP_MODE2, usp->mode2_reg); |
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} |
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return 0; |
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} |
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#endif |
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static const struct snd_soc_component_driver sirf_usp_component = { |
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.name = "sirf-usp", |
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}; |
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static const struct regmap_config sirf_usp_regmap_config = { |
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.reg_bits = 32, |
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.reg_stride = 4, |
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.val_bits = 32, |
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.max_register = USP_RX_FIFO_DATA, |
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.cache_type = REGCACHE_NONE, |
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}; |
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static int sirf_usp_pcm_probe(struct platform_device *pdev) |
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{ |
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int ret; |
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struct sirf_usp *usp; |
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void __iomem *base; |
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usp = devm_kzalloc(&pdev->dev, sizeof(struct sirf_usp), |
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GFP_KERNEL); |
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if (!usp) |
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return -ENOMEM; |
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platform_set_drvdata(pdev, usp); |
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base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(base)) |
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return PTR_ERR(base); |
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usp->regmap = devm_regmap_init_mmio(&pdev->dev, base, |
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&sirf_usp_regmap_config); |
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if (IS_ERR(usp->regmap)) |
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return PTR_ERR(usp->regmap); |
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usp->clk = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(usp->clk)) { |
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dev_err(&pdev->dev, "Get clock failed.\n"); |
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return PTR_ERR(usp->clk); |
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} |
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pm_runtime_enable(&pdev->dev); |
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if (!pm_runtime_enabled(&pdev->dev)) { |
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ret = sirf_usp_pcm_runtime_resume(&pdev->dev); |
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if (ret) |
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return ret; |
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} |
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ret = devm_snd_soc_register_component(&pdev->dev, &sirf_usp_component, |
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&sirf_usp_pcm_dai, 1); |
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if (ret) { |
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dev_err(&pdev->dev, "Register Audio SoC dai failed.\n"); |
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return ret; |
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} |
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return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); |
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} |
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static int sirf_usp_pcm_remove(struct platform_device *pdev) |
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{ |
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if (!pm_runtime_enabled(&pdev->dev)) |
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sirf_usp_pcm_runtime_suspend(&pdev->dev); |
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else |
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pm_runtime_disable(&pdev->dev); |
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return 0; |
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} |
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static const struct of_device_id sirf_usp_pcm_of_match[] = { |
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{ .compatible = "sirf,prima2-usp-pcm", }, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(of, sirf_usp_pcm_of_match); |
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static const struct dev_pm_ops sirf_usp_pcm_pm_ops = { |
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SET_RUNTIME_PM_OPS(sirf_usp_pcm_runtime_suspend, |
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sirf_usp_pcm_runtime_resume, NULL) |
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SET_SYSTEM_SLEEP_PM_OPS(sirf_usp_pcm_suspend, sirf_usp_pcm_resume) |
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}; |
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static struct platform_driver sirf_usp_pcm_driver = { |
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.driver = { |
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.name = "sirf-usp-pcm", |
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.of_match_table = sirf_usp_pcm_of_match, |
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.pm = &sirf_usp_pcm_pm_ops, |
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}, |
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.probe = sirf_usp_pcm_probe, |
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.remove = sirf_usp_pcm_remove, |
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}; |
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module_platform_driver(sirf_usp_pcm_driver); |
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MODULE_DESCRIPTION("SiRF SoC USP PCM bus driver"); |
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MODULE_AUTHOR("RongJun Ying <[email protected]>"); |
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MODULE_LICENSE("GPL v2");
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