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396 lines
9.2 KiB
396 lines
9.2 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* sound/soc/rockchip/rk_spdif.c |
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* |
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* ALSA SoC Audio Layer - Rockchip I2S Controller driver |
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* |
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* Copyright (c) 2014 Rockchip Electronics Co. Ltd. |
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* Author: Jianqun <[email protected]> |
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* Copyright (c) 2015 Collabora Ltd. |
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* Author: Sjoerd Simons <[email protected]> |
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*/ |
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#include <linux/module.h> |
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#include <linux/delay.h> |
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#include <linux/of_gpio.h> |
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#include <linux/clk.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/regmap.h> |
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#include <sound/pcm_params.h> |
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#include <sound/dmaengine_pcm.h> |
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#include "rockchip_spdif.h" |
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enum rk_spdif_type { |
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RK_SPDIF_RK3066, |
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RK_SPDIF_RK3188, |
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RK_SPDIF_RK3288, |
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RK_SPDIF_RK3366, |
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}; |
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#define RK3288_GRF_SOC_CON2 0x24c |
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struct rk_spdif_dev { |
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struct device *dev; |
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struct clk *mclk; |
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struct clk *hclk; |
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struct snd_dmaengine_dai_dma_data playback_dma_data; |
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struct regmap *regmap; |
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}; |
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static const struct of_device_id rk_spdif_match[] __maybe_unused = { |
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{ .compatible = "rockchip,rk3066-spdif", |
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.data = (void *)RK_SPDIF_RK3066 }, |
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{ .compatible = "rockchip,rk3188-spdif", |
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.data = (void *)RK_SPDIF_RK3188 }, |
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{ .compatible = "rockchip,rk3228-spdif", |
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.data = (void *)RK_SPDIF_RK3366 }, |
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{ .compatible = "rockchip,rk3288-spdif", |
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.data = (void *)RK_SPDIF_RK3288 }, |
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{ .compatible = "rockchip,rk3328-spdif", |
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.data = (void *)RK_SPDIF_RK3366 }, |
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{ .compatible = "rockchip,rk3366-spdif", |
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.data = (void *)RK_SPDIF_RK3366 }, |
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{ .compatible = "rockchip,rk3368-spdif", |
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.data = (void *)RK_SPDIF_RK3366 }, |
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{ .compatible = "rockchip,rk3399-spdif", |
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.data = (void *)RK_SPDIF_RK3366 }, |
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{ .compatible = "rockchip,rk3568-spdif", |
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.data = (void *)RK_SPDIF_RK3366 }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, rk_spdif_match); |
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static int __maybe_unused rk_spdif_runtime_suspend(struct device *dev) |
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{ |
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struct rk_spdif_dev *spdif = dev_get_drvdata(dev); |
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regcache_cache_only(spdif->regmap, true); |
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clk_disable_unprepare(spdif->mclk); |
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clk_disable_unprepare(spdif->hclk); |
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return 0; |
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} |
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static int __maybe_unused rk_spdif_runtime_resume(struct device *dev) |
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{ |
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struct rk_spdif_dev *spdif = dev_get_drvdata(dev); |
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int ret; |
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ret = clk_prepare_enable(spdif->mclk); |
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if (ret) { |
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dev_err(spdif->dev, "mclk clock enable failed %d\n", ret); |
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return ret; |
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} |
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ret = clk_prepare_enable(spdif->hclk); |
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if (ret) { |
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dev_err(spdif->dev, "hclk clock enable failed %d\n", ret); |
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return ret; |
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} |
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regcache_cache_only(spdif->regmap, false); |
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regcache_mark_dirty(spdif->regmap); |
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ret = regcache_sync(spdif->regmap); |
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if (ret) { |
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clk_disable_unprepare(spdif->mclk); |
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clk_disable_unprepare(spdif->hclk); |
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} |
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return ret; |
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} |
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static int rk_spdif_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *dai) |
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{ |
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struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai); |
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unsigned int val = SPDIF_CFGR_HALFWORD_ENABLE; |
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int srate, mclk; |
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int ret; |
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srate = params_rate(params); |
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mclk = srate * 128; |
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switch (params_format(params)) { |
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case SNDRV_PCM_FORMAT_S16_LE: |
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val |= SPDIF_CFGR_VDW_16; |
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break; |
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case SNDRV_PCM_FORMAT_S20_3LE: |
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val |= SPDIF_CFGR_VDW_20; |
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break; |
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case SNDRV_PCM_FORMAT_S24_LE: |
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val |= SPDIF_CFGR_VDW_24; |
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break; |
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default: |
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return -EINVAL; |
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} |
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/* Set clock and calculate divider */ |
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ret = clk_set_rate(spdif->mclk, mclk); |
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if (ret != 0) { |
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dev_err(spdif->dev, "Failed to set module clock rate: %d\n", |
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ret); |
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return ret; |
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} |
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ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR, |
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SPDIF_CFGR_CLK_DIV_MASK | |
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SPDIF_CFGR_HALFWORD_ENABLE | |
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SDPIF_CFGR_VDW_MASK, val); |
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return ret; |
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} |
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static int rk_spdif_trigger(struct snd_pcm_substream *substream, |
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int cmd, struct snd_soc_dai *dai) |
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{ |
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struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai); |
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int ret; |
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switch (cmd) { |
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case SNDRV_PCM_TRIGGER_START: |
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case SNDRV_PCM_TRIGGER_RESUME: |
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
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ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR, |
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SPDIF_DMACR_TDE_ENABLE | |
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SPDIF_DMACR_TDL_MASK, |
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SPDIF_DMACR_TDE_ENABLE | |
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SPDIF_DMACR_TDL(16)); |
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if (ret != 0) |
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return ret; |
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ret = regmap_update_bits(spdif->regmap, SPDIF_XFER, |
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SPDIF_XFER_TXS_START, |
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SPDIF_XFER_TXS_START); |
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break; |
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case SNDRV_PCM_TRIGGER_SUSPEND: |
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case SNDRV_PCM_TRIGGER_STOP: |
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
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ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR, |
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SPDIF_DMACR_TDE_ENABLE, |
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SPDIF_DMACR_TDE_DISABLE); |
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if (ret != 0) |
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return ret; |
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ret = regmap_update_bits(spdif->regmap, SPDIF_XFER, |
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SPDIF_XFER_TXS_START, |
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SPDIF_XFER_TXS_STOP); |
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break; |
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default: |
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ret = -EINVAL; |
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break; |
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} |
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return ret; |
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} |
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static int rk_spdif_dai_probe(struct snd_soc_dai *dai) |
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{ |
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struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai); |
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dai->playback_dma_data = &spdif->playback_dma_data; |
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return 0; |
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} |
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static const struct snd_soc_dai_ops rk_spdif_dai_ops = { |
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.hw_params = rk_spdif_hw_params, |
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.trigger = rk_spdif_trigger, |
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}; |
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static struct snd_soc_dai_driver rk_spdif_dai = { |
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.probe = rk_spdif_dai_probe, |
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.playback = { |
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.stream_name = "Playback", |
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.channels_min = 2, |
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.channels_max = 2, |
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.rates = (SNDRV_PCM_RATE_32000 | |
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SNDRV_PCM_RATE_44100 | |
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SNDRV_PCM_RATE_48000 | |
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SNDRV_PCM_RATE_96000 | |
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SNDRV_PCM_RATE_192000), |
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.formats = (SNDRV_PCM_FMTBIT_S16_LE | |
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SNDRV_PCM_FMTBIT_S20_3LE | |
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SNDRV_PCM_FMTBIT_S24_LE), |
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}, |
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.ops = &rk_spdif_dai_ops, |
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}; |
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static const struct snd_soc_component_driver rk_spdif_component = { |
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.name = "rockchip-spdif", |
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}; |
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static bool rk_spdif_wr_reg(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case SPDIF_CFGR: |
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case SPDIF_DMACR: |
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case SPDIF_INTCR: |
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case SPDIF_XFER: |
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case SPDIF_SMPDR: |
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return true; |
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default: |
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return false; |
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} |
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} |
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static bool rk_spdif_rd_reg(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case SPDIF_CFGR: |
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case SPDIF_SDBLR: |
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case SPDIF_INTCR: |
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case SPDIF_INTSR: |
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case SPDIF_XFER: |
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case SPDIF_SMPDR: |
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return true; |
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default: |
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return false; |
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} |
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} |
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static bool rk_spdif_volatile_reg(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case SPDIF_INTSR: |
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case SPDIF_SDBLR: |
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case SPDIF_SMPDR: |
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return true; |
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default: |
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return false; |
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} |
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} |
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static const struct regmap_config rk_spdif_regmap_config = { |
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.reg_bits = 32, |
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.reg_stride = 4, |
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.val_bits = 32, |
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.max_register = SPDIF_SMPDR, |
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.writeable_reg = rk_spdif_wr_reg, |
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.readable_reg = rk_spdif_rd_reg, |
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.volatile_reg = rk_spdif_volatile_reg, |
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.cache_type = REGCACHE_FLAT, |
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}; |
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static int rk_spdif_probe(struct platform_device *pdev) |
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{ |
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struct device_node *np = pdev->dev.of_node; |
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struct rk_spdif_dev *spdif; |
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const struct of_device_id *match; |
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struct resource *res; |
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void __iomem *regs; |
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int ret; |
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match = of_match_node(rk_spdif_match, np); |
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if (match->data == (void *)RK_SPDIF_RK3288) { |
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struct regmap *grf; |
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grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); |
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if (IS_ERR(grf)) { |
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dev_err(&pdev->dev, |
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"rockchip_spdif missing 'rockchip,grf'\n"); |
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return PTR_ERR(grf); |
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} |
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/* Select the 8 channel SPDIF solution on RK3288 as |
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* the 2 channel one does not appear to work |
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*/ |
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regmap_write(grf, RK3288_GRF_SOC_CON2, BIT(1) << 16); |
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} |
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spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL); |
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if (!spdif) |
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return -ENOMEM; |
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spdif->hclk = devm_clk_get(&pdev->dev, "hclk"); |
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if (IS_ERR(spdif->hclk)) |
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return PTR_ERR(spdif->hclk); |
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spdif->mclk = devm_clk_get(&pdev->dev, "mclk"); |
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if (IS_ERR(spdif->mclk)) |
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return PTR_ERR(spdif->mclk); |
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regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); |
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if (IS_ERR(regs)) |
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return PTR_ERR(regs); |
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spdif->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "hclk", regs, |
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&rk_spdif_regmap_config); |
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if (IS_ERR(spdif->regmap)) |
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return PTR_ERR(spdif->regmap); |
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spdif->playback_dma_data.addr = res->start + SPDIF_SMPDR; |
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spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
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spdif->playback_dma_data.maxburst = 4; |
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spdif->dev = &pdev->dev; |
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dev_set_drvdata(&pdev->dev, spdif); |
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pm_runtime_enable(&pdev->dev); |
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if (!pm_runtime_enabled(&pdev->dev)) { |
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ret = rk_spdif_runtime_resume(&pdev->dev); |
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if (ret) |
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goto err_pm_runtime; |
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} |
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ret = devm_snd_soc_register_component(&pdev->dev, |
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&rk_spdif_component, |
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&rk_spdif_dai, 1); |
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if (ret) { |
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dev_err(&pdev->dev, "Could not register DAI\n"); |
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goto err_pm_suspend; |
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} |
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ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); |
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if (ret) { |
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dev_err(&pdev->dev, "Could not register PCM\n"); |
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goto err_pm_suspend; |
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} |
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return 0; |
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err_pm_suspend: |
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if (!pm_runtime_status_suspended(&pdev->dev)) |
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rk_spdif_runtime_suspend(&pdev->dev); |
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err_pm_runtime: |
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pm_runtime_disable(&pdev->dev); |
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return ret; |
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} |
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static int rk_spdif_remove(struct platform_device *pdev) |
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{ |
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pm_runtime_disable(&pdev->dev); |
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if (!pm_runtime_status_suspended(&pdev->dev)) |
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rk_spdif_runtime_suspend(&pdev->dev); |
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return 0; |
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} |
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static const struct dev_pm_ops rk_spdif_pm_ops = { |
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SET_RUNTIME_PM_OPS(rk_spdif_runtime_suspend, rk_spdif_runtime_resume, |
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NULL) |
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}; |
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static struct platform_driver rk_spdif_driver = { |
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.probe = rk_spdif_probe, |
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.remove = rk_spdif_remove, |
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.driver = { |
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.name = "rockchip-spdif", |
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.of_match_table = of_match_ptr(rk_spdif_match), |
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.pm = &rk_spdif_pm_ops, |
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}, |
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}; |
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module_platform_driver(rk_spdif_driver); |
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MODULE_ALIAS("platform:rockchip-spdif"); |
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MODULE_DESCRIPTION("ROCKCHIP SPDIF transceiver Interface"); |
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MODULE_AUTHOR("Sjoerd Simons <[email protected]>"); |
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MODULE_LICENSE("GPL v2");
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