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46 lines
1.5 KiB
46 lines
1.5 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copied from the kernel sources: |
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* |
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* Copyright (C) 1999 Cort Dougan <[email protected]> |
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*/ |
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#ifndef _TOOLS_LINUX_ASM_POWERPC_BARRIER_H |
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#define _TOOLS_LINUX_ASM_POWERPC_BARRIER_H |
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/* |
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* Memory barrier. |
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* The sync instruction guarantees that all memory accesses initiated |
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* by this processor have been performed (with respect to all other |
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* mechanisms that access memory). The eieio instruction is a barrier |
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* providing an ordering (separately) for (a) cacheable stores and (b) |
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* loads and stores to non-cacheable memory (e.g. I/O devices). |
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* |
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* mb() prevents loads and stores being reordered across this point. |
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* rmb() prevents loads being reordered across this point. |
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* wmb() prevents stores being reordered across this point. |
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* |
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* *mb() variants without smp_ prefix must order all types of memory |
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* operations with one another. sync is the only instruction sufficient |
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* to do this. |
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*/ |
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#define mb() __asm__ __volatile__ ("sync" : : : "memory") |
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#define rmb() __asm__ __volatile__ ("sync" : : : "memory") |
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#define wmb() __asm__ __volatile__ ("sync" : : : "memory") |
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#if defined(__powerpc64__) |
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#define smp_lwsync() __asm__ __volatile__ ("lwsync" : : : "memory") |
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#define smp_store_release(p, v) \ |
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do { \ |
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smp_lwsync(); \ |
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WRITE_ONCE(*p, v); \ |
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} while (0) |
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#define smp_load_acquire(p) \ |
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({ \ |
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typeof(*p) ___p1 = READ_ONCE(*p); \ |
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smp_lwsync(); \ |
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___p1; \ |
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}) |
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#endif /* defined(__powerpc64__) */ |
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#endif /* _TOOLS_LINUX_ASM_POWERPC_BARRIER_H */
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