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1060 lines
21 KiB
1060 lines
21 KiB
/* SPDX-License-Identifier: MIT */ |
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/* Copyright (c) 2012-2020 NVIDIA Corporation */ |
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#ifndef _UAPI_TEGRA_DRM_H_ |
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#define _UAPI_TEGRA_DRM_H_ |
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#include "drm.h" |
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#if defined(__cplusplus) |
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extern "C" { |
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#endif |
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/* Tegra DRM legacy UAPI. Only enabled with STAGING */ |
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#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0) |
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#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1) |
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/** |
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* struct drm_tegra_gem_create - parameters for the GEM object creation IOCTL |
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*/ |
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struct drm_tegra_gem_create { |
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/** |
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* @size: |
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* |
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* The size, in bytes, of the buffer object to be created. |
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*/ |
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__u64 size; |
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/** |
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* @flags: |
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* |
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* A bitmask of flags that influence the creation of GEM objects: |
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* |
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* DRM_TEGRA_GEM_CREATE_TILED |
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* Use the 16x16 tiling format for this buffer. |
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* |
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* DRM_TEGRA_GEM_CREATE_BOTTOM_UP |
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* The buffer has a bottom-up layout. |
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*/ |
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__u32 flags; |
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/** |
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* @handle: |
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* |
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* The handle of the created GEM object. Set by the kernel upon |
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* successful completion of the IOCTL. |
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*/ |
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__u32 handle; |
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}; |
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/** |
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* struct drm_tegra_gem_mmap - parameters for the GEM mmap IOCTL |
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*/ |
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struct drm_tegra_gem_mmap { |
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/** |
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* @handle: |
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* |
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* Handle of the GEM object to obtain an mmap offset for. |
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*/ |
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__u32 handle; |
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/** |
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* @pad: |
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* |
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* Structure padding that may be used in the future. Must be 0. |
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*/ |
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__u32 pad; |
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/** |
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* @offset: |
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* |
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* The mmap offset for the given GEM object. Set by the kernel upon |
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* successful completion of the IOCTL. |
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*/ |
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__u64 offset; |
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}; |
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/** |
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* struct drm_tegra_syncpt_read - parameters for the read syncpoint IOCTL |
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*/ |
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struct drm_tegra_syncpt_read { |
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/** |
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* @id: |
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* |
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* ID of the syncpoint to read the current value from. |
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*/ |
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__u32 id; |
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/** |
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* @value: |
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* |
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* The current syncpoint value. Set by the kernel upon successful |
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* completion of the IOCTL. |
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*/ |
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__u32 value; |
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}; |
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/** |
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* struct drm_tegra_syncpt_incr - parameters for the increment syncpoint IOCTL |
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*/ |
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struct drm_tegra_syncpt_incr { |
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/** |
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* @id: |
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* |
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* ID of the syncpoint to increment. |
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*/ |
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__u32 id; |
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/** |
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* @pad: |
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* |
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* Structure padding that may be used in the future. Must be 0. |
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*/ |
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__u32 pad; |
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}; |
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/** |
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* struct drm_tegra_syncpt_wait - parameters for the wait syncpoint IOCTL |
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*/ |
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struct drm_tegra_syncpt_wait { |
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/** |
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* @id: |
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* |
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* ID of the syncpoint to wait on. |
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*/ |
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__u32 id; |
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/** |
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* @thresh: |
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* |
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* Threshold value for which to wait. |
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*/ |
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__u32 thresh; |
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/** |
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* @timeout: |
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* |
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* Timeout, in milliseconds, to wait. |
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*/ |
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__u32 timeout; |
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/** |
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* @value: |
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* |
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* The new syncpoint value after the wait. Set by the kernel upon |
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* successful completion of the IOCTL. |
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*/ |
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__u32 value; |
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}; |
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#define DRM_TEGRA_NO_TIMEOUT (0xffffffff) |
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/** |
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* struct drm_tegra_open_channel - parameters for the open channel IOCTL |
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*/ |
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struct drm_tegra_open_channel { |
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/** |
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* @client: |
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* |
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* The client ID for this channel. |
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*/ |
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__u32 client; |
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/** |
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* @pad: |
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* |
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* Structure padding that may be used in the future. Must be 0. |
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*/ |
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__u32 pad; |
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/** |
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* @context: |
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* |
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* The application context of this channel. Set by the kernel upon |
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* successful completion of the IOCTL. This context needs to be passed |
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* to the DRM_TEGRA_CHANNEL_CLOSE or the DRM_TEGRA_SUBMIT IOCTLs. |
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*/ |
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__u64 context; |
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}; |
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/** |
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* struct drm_tegra_close_channel - parameters for the close channel IOCTL |
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*/ |
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struct drm_tegra_close_channel { |
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/** |
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* @context: |
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* |
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* The application context of this channel. This is obtained from the |
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* DRM_TEGRA_OPEN_CHANNEL IOCTL. |
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*/ |
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__u64 context; |
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}; |
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/** |
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* struct drm_tegra_get_syncpt - parameters for the get syncpoint IOCTL |
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*/ |
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struct drm_tegra_get_syncpt { |
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/** |
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* @context: |
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* |
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* The application context identifying the channel for which to obtain |
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* the syncpoint ID. |
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*/ |
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__u64 context; |
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/** |
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* @index: |
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* |
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* Index of the client syncpoint for which to obtain the ID. |
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*/ |
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__u32 index; |
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/** |
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* @id: |
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* |
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* The ID of the given syncpoint. Set by the kernel upon successful |
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* completion of the IOCTL. |
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*/ |
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__u32 id; |
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}; |
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/** |
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* struct drm_tegra_get_syncpt_base - parameters for the get wait base IOCTL |
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*/ |
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struct drm_tegra_get_syncpt_base { |
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/** |
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* @context: |
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* |
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* The application context identifying for which channel to obtain the |
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* wait base. |
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*/ |
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__u64 context; |
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/** |
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* @syncpt: |
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* |
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* ID of the syncpoint for which to obtain the wait base. |
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*/ |
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__u32 syncpt; |
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/** |
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* @id: |
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* |
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* The ID of the wait base corresponding to the client syncpoint. Set |
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* by the kernel upon successful completion of the IOCTL. |
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*/ |
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__u32 id; |
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}; |
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/** |
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* struct drm_tegra_syncpt - syncpoint increment operation |
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*/ |
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struct drm_tegra_syncpt { |
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/** |
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* @id: |
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* |
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* ID of the syncpoint to operate on. |
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*/ |
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__u32 id; |
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/** |
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* @incrs: |
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* |
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* Number of increments to perform for the syncpoint. |
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*/ |
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__u32 incrs; |
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}; |
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/** |
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* struct drm_tegra_cmdbuf - structure describing a command buffer |
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*/ |
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struct drm_tegra_cmdbuf { |
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/** |
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* @handle: |
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* |
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* Handle to a GEM object containing the command buffer. |
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*/ |
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__u32 handle; |
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/** |
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* @offset: |
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* |
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* Offset, in bytes, into the GEM object identified by @handle at |
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* which the command buffer starts. |
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*/ |
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__u32 offset; |
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/** |
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* @words: |
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* |
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* Number of 32-bit words in this command buffer. |
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*/ |
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__u32 words; |
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/** |
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* @pad: |
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* |
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* Structure padding that may be used in the future. Must be 0. |
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*/ |
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__u32 pad; |
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}; |
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/** |
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* struct drm_tegra_reloc - GEM object relocation structure |
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*/ |
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struct drm_tegra_reloc { |
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struct { |
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/** |
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* @cmdbuf.handle: |
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* |
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* Handle to the GEM object containing the command buffer for |
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* which to perform this GEM object relocation. |
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*/ |
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__u32 handle; |
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/** |
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* @cmdbuf.offset: |
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* |
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* Offset, in bytes, into the command buffer at which to |
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* insert the relocated address. |
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*/ |
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__u32 offset; |
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} cmdbuf; |
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struct { |
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/** |
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* @target.handle: |
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* |
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* Handle to the GEM object to be relocated. |
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*/ |
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__u32 handle; |
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/** |
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* @target.offset: |
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* |
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* Offset, in bytes, into the target GEM object at which the |
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* relocated data starts. |
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*/ |
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__u32 offset; |
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} target; |
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/** |
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* @shift: |
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* |
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* The number of bits by which to shift relocated addresses. |
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*/ |
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__u32 shift; |
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/** |
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* @pad: |
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* |
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* Structure padding that may be used in the future. Must be 0. |
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*/ |
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__u32 pad; |
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}; |
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/** |
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* struct drm_tegra_waitchk - wait check structure |
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*/ |
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struct drm_tegra_waitchk { |
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/** |
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* @handle: |
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* |
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* Handle to the GEM object containing a command stream on which to |
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* perform the wait check. |
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*/ |
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__u32 handle; |
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/** |
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* @offset: |
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* |
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* Offset, in bytes, of the location in the command stream to perform |
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* the wait check on. |
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*/ |
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__u32 offset; |
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/** |
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* @syncpt: |
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* |
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* ID of the syncpoint to wait check. |
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*/ |
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__u32 syncpt; |
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/** |
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* @thresh: |
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* |
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* Threshold value for which to check. |
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*/ |
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__u32 thresh; |
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}; |
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/** |
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* struct drm_tegra_submit - job submission structure |
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*/ |
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struct drm_tegra_submit { |
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/** |
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* @context: |
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* |
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* The application context identifying the channel to use for the |
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* execution of this job. |
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*/ |
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__u64 context; |
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/** |
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* @num_syncpts: |
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* |
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* The number of syncpoints operated on by this job. This defines the |
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* length of the array pointed to by @syncpts. |
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*/ |
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__u32 num_syncpts; |
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/** |
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* @num_cmdbufs: |
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* |
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* The number of command buffers to execute as part of this job. This |
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* defines the length of the array pointed to by @cmdbufs. |
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*/ |
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__u32 num_cmdbufs; |
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/** |
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* @num_relocs: |
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* |
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* The number of relocations to perform before executing this job. |
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* This defines the length of the array pointed to by @relocs. |
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*/ |
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__u32 num_relocs; |
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/** |
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* @num_waitchks: |
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* |
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* The number of wait checks to perform as part of this job. This |
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* defines the length of the array pointed to by @waitchks. |
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*/ |
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__u32 num_waitchks; |
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/** |
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* @waitchk_mask: |
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* |
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* Bitmask of valid wait checks. |
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*/ |
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__u32 waitchk_mask; |
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/** |
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* @timeout: |
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* |
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* Timeout, in milliseconds, before this job is cancelled. |
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*/ |
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__u32 timeout; |
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/** |
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* @syncpts: |
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* |
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* A pointer to an array of &struct drm_tegra_syncpt structures that |
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* specify the syncpoint operations performed as part of this job. |
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* The number of elements in the array must be equal to the value |
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* given by @num_syncpts. |
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*/ |
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__u64 syncpts; |
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/** |
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* @cmdbufs: |
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* |
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* A pointer to an array of &struct drm_tegra_cmdbuf structures that |
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* define the command buffers to execute as part of this job. The |
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* number of elements in the array must be equal to the value given |
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* by @num_syncpts. |
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*/ |
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__u64 cmdbufs; |
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/** |
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* @relocs: |
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* |
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* A pointer to an array of &struct drm_tegra_reloc structures that |
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* specify the relocations that need to be performed before executing |
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* this job. The number of elements in the array must be equal to the |
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* value given by @num_relocs. |
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*/ |
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__u64 relocs; |
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/** |
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* @waitchks: |
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* |
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* A pointer to an array of &struct drm_tegra_waitchk structures that |
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* specify the wait checks to be performed while executing this job. |
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* The number of elements in the array must be equal to the value |
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* given by @num_waitchks. |
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*/ |
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__u64 waitchks; |
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/** |
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* @fence: |
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* |
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* The threshold of the syncpoint associated with this job after it |
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* has been completed. Set by the kernel upon successful completion of |
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* the IOCTL. This can be used with the DRM_TEGRA_SYNCPT_WAIT IOCTL to |
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* wait for this job to be finished. |
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*/ |
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__u32 fence; |
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/** |
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* @reserved: |
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* |
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* This field is reserved for future use. Must be 0. |
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*/ |
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__u32 reserved[5]; |
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}; |
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#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0 |
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#define DRM_TEGRA_GEM_TILING_MODE_TILED 1 |
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#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2 |
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/** |
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* struct drm_tegra_gem_set_tiling - parameters for the set tiling IOCTL |
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*/ |
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struct drm_tegra_gem_set_tiling { |
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/** |
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* @handle: |
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* |
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* Handle to the GEM object for which to set the tiling parameters. |
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*/ |
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__u32 handle; |
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/** |
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* @mode: |
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* |
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* The tiling mode to set. Must be one of: |
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* |
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* DRM_TEGRA_GEM_TILING_MODE_PITCH |
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* pitch linear format |
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* |
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* DRM_TEGRA_GEM_TILING_MODE_TILED |
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* 16x16 tiling format |
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* |
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* DRM_TEGRA_GEM_TILING_MODE_BLOCK |
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* 16Bx2 tiling format |
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*/ |
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__u32 mode; |
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/** |
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* @value: |
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* |
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* The value to set for the tiling mode parameter. |
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*/ |
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__u32 value; |
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/** |
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* @pad: |
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* |
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* Structure padding that may be used in the future. Must be 0. |
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*/ |
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__u32 pad; |
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}; |
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/** |
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* struct drm_tegra_gem_get_tiling - parameters for the get tiling IOCTL |
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*/ |
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struct drm_tegra_gem_get_tiling { |
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/** |
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* @handle: |
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* |
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* Handle to the GEM object for which to query the tiling parameters. |
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*/ |
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__u32 handle; |
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/** |
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* @mode: |
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* |
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* The tiling mode currently associated with the GEM object. Set by |
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* the kernel upon successful completion of the IOCTL. |
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*/ |
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__u32 mode; |
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/** |
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* @value: |
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* |
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* The tiling mode parameter currently associated with the GEM object. |
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* Set by the kernel upon successful completion of the IOCTL. |
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*/ |
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__u32 value; |
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/** |
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* @pad: |
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* |
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* Structure padding that may be used in the future. Must be 0. |
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*/ |
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__u32 pad; |
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}; |
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#define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0) |
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#define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP) |
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/** |
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* struct drm_tegra_gem_set_flags - parameters for the set flags IOCTL |
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*/ |
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struct drm_tegra_gem_set_flags { |
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/** |
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* @handle: |
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* |
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* Handle to the GEM object for which to set the flags. |
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*/ |
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__u32 handle; |
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/** |
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* @flags: |
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* |
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* The flags to set for the GEM object. |
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*/ |
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__u32 flags; |
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}; |
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/** |
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* struct drm_tegra_gem_get_flags - parameters for the get flags IOCTL |
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*/ |
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struct drm_tegra_gem_get_flags { |
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/** |
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* @handle: |
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* |
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* Handle to the GEM object for which to query the flags. |
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*/ |
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__u32 handle; |
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/** |
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* @flags: |
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* |
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* The flags currently associated with the GEM object. Set by the |
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* kernel upon successful completion of the IOCTL. |
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*/ |
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__u32 flags; |
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}; |
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#define DRM_TEGRA_GEM_CREATE 0x00 |
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#define DRM_TEGRA_GEM_MMAP 0x01 |
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#define DRM_TEGRA_SYNCPT_READ 0x02 |
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#define DRM_TEGRA_SYNCPT_INCR 0x03 |
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#define DRM_TEGRA_SYNCPT_WAIT 0x04 |
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#define DRM_TEGRA_OPEN_CHANNEL 0x05 |
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#define DRM_TEGRA_CLOSE_CHANNEL 0x06 |
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#define DRM_TEGRA_GET_SYNCPT 0x07 |
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#define DRM_TEGRA_SUBMIT 0x08 |
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#define DRM_TEGRA_GET_SYNCPT_BASE 0x09 |
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#define DRM_TEGRA_GEM_SET_TILING 0x0a |
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#define DRM_TEGRA_GEM_GET_TILING 0x0b |
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#define DRM_TEGRA_GEM_SET_FLAGS 0x0c |
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#define DRM_TEGRA_GEM_GET_FLAGS 0x0d |
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#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create) |
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#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap) |
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#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read) |
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#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr) |
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#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait) |
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#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel) |
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#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_close_channel) |
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#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt) |
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#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit) |
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#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base) |
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#define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling) |
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#define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling) |
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#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags) |
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#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags) |
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/* New Tegra DRM UAPI */ |
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/* |
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* Reported by the driver in the `capabilities` field. |
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* |
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* DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT: If set, the engine is cache coherent |
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* with regard to the system memory. |
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*/ |
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#define DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT (1 << 0) |
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struct drm_tegra_channel_open { |
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/** |
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* @host1x_class: [in] |
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* |
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* Host1x class of the engine that will be programmed using this |
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* channel. |
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*/ |
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__u32 host1x_class; |
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/** |
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* @flags: [in] |
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* |
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* Flags. |
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*/ |
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__u32 flags; |
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/** |
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* @context: [out] |
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* |
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* Opaque identifier corresponding to the opened channel. |
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*/ |
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__u32 context; |
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/** |
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* @version: [out] |
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* |
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* Version of the engine hardware. This can be used by userspace |
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* to determine how the engine needs to be programmed. |
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*/ |
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__u32 version; |
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/** |
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* @capabilities: [out] |
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* |
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* Flags describing the hardware capabilities. |
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*/ |
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__u32 capabilities; |
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__u32 padding; |
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}; |
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struct drm_tegra_channel_close { |
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/** |
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* @context: [in] |
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* |
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* Identifier of the channel to close. |
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*/ |
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__u32 context; |
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__u32 padding; |
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}; |
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/* |
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* Mapping flags that can be used to influence how the mapping is created. |
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* |
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* DRM_TEGRA_CHANNEL_MAP_READ: create mapping that allows HW read access |
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* DRM_TEGRA_CHANNEL_MAP_WRITE: create mapping that allows HW write access |
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*/ |
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#define DRM_TEGRA_CHANNEL_MAP_READ (1 << 0) |
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#define DRM_TEGRA_CHANNEL_MAP_WRITE (1 << 1) |
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#define DRM_TEGRA_CHANNEL_MAP_READ_WRITE (DRM_TEGRA_CHANNEL_MAP_READ | \ |
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DRM_TEGRA_CHANNEL_MAP_WRITE) |
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struct drm_tegra_channel_map { |
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/** |
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* @context: [in] |
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* |
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* Identifier of the channel to which make memory available for. |
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*/ |
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__u32 context; |
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/** |
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* @handle: [in] |
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* |
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* GEM handle of the memory to map. |
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*/ |
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__u32 handle; |
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/** |
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* @flags: [in] |
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* |
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* Flags. |
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*/ |
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__u32 flags; |
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/** |
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* @mapping: [out] |
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* |
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* Identifier corresponding to the mapping, to be used for |
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* relocations or unmapping later. |
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*/ |
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__u32 mapping; |
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}; |
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struct drm_tegra_channel_unmap { |
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/** |
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* @context: [in] |
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* |
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* Channel identifier of the channel to unmap memory from. |
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*/ |
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__u32 context; |
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/** |
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* @mapping: [in] |
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* |
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* Mapping identifier of the memory mapping to unmap. |
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*/ |
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__u32 mapping; |
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}; |
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/* Submission */ |
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/** |
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* Specify that bit 39 of the patched-in address should be set to switch |
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* swizzling between Tegra and non-Tegra sector layout on systems that store |
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* surfaces in system memory in non-Tegra sector layout. |
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*/ |
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#define DRM_TEGRA_SUBMIT_RELOC_SECTOR_LAYOUT (1 << 0) |
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struct drm_tegra_submit_buf { |
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/** |
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* @mapping: [in] |
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* |
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* Identifier of the mapping to use in the submission. |
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*/ |
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__u32 mapping; |
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/** |
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* @flags: [in] |
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* |
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* Flags. |
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*/ |
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__u32 flags; |
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/** |
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* Information for relocation patching. |
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*/ |
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struct { |
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/** |
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* @target_offset: [in] |
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* |
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* Offset from the start of the mapping of the data whose |
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* address is to be patched into the gather. |
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*/ |
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__u64 target_offset; |
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/** |
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* @gather_offset_words: [in] |
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* |
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* Offset in words from the start of the gather data to |
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* where the address should be patched into. |
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*/ |
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__u32 gather_offset_words; |
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/** |
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* @shift: [in] |
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* |
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* Number of bits the address should be shifted right before |
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* patching in. |
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*/ |
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__u32 shift; |
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} reloc; |
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}; |
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/** |
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* Execute `words` words of Host1x opcodes specified in the `gather_data_ptr` |
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* buffer. Each GATHER_UPTR command uses successive words from the buffer. |
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*/ |
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#define DRM_TEGRA_SUBMIT_CMD_GATHER_UPTR 0 |
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/** |
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* Wait for a syncpoint to reach a value before continuing with further |
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* commands. |
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*/ |
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#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT 1 |
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/** |
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* Wait for a syncpoint to reach a value before continuing with further |
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* commands. The threshold is calculated relative to the start of the job. |
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*/ |
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#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT_RELATIVE 2 |
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struct drm_tegra_submit_cmd_gather_uptr { |
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__u32 words; |
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__u32 reserved[3]; |
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}; |
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struct drm_tegra_submit_cmd_wait_syncpt { |
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__u32 id; |
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__u32 value; |
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__u32 reserved[2]; |
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}; |
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struct drm_tegra_submit_cmd { |
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/** |
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* @type: [in] |
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* |
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* Command type to execute. One of the DRM_TEGRA_SUBMIT_CMD* |
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* defines. |
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*/ |
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__u32 type; |
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/** |
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* @flags: [in] |
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* |
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* Flags. |
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*/ |
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__u32 flags; |
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union { |
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struct drm_tegra_submit_cmd_gather_uptr gather_uptr; |
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struct drm_tegra_submit_cmd_wait_syncpt wait_syncpt; |
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__u32 reserved[4]; |
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}; |
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}; |
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struct drm_tegra_submit_syncpt { |
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/** |
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* @id: [in] |
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* |
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* ID of the syncpoint that the job will increment. |
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*/ |
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__u32 id; |
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/** |
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* @flags: [in] |
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* |
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* Flags. |
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*/ |
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__u32 flags; |
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/** |
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* @increments: [in] |
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* |
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* Number of times the job will increment this syncpoint. |
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*/ |
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__u32 increments; |
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/** |
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* @value: [out] |
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* |
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* Value the syncpoint will have once the job has completed all |
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* its specified syncpoint increments. |
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* |
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* Note that the kernel may increment the syncpoint before or after |
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* the job. These increments are not reflected in this field. |
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* |
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* If the job hangs or times out, not all of the increments may |
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* get executed. |
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*/ |
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__u32 value; |
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}; |
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struct drm_tegra_channel_submit { |
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/** |
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* @context: [in] |
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* |
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* Identifier of the channel to submit this job to. |
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*/ |
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__u32 context; |
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/** |
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* @num_bufs: [in] |
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* |
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* Number of elements in the `bufs_ptr` array. |
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*/ |
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__u32 num_bufs; |
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/** |
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* @num_cmds: [in] |
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* |
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* Number of elements in the `cmds_ptr` array. |
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*/ |
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__u32 num_cmds; |
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/** |
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* @gather_data_words: [in] |
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* |
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* Number of 32-bit words in the `gather_data_ptr` array. |
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*/ |
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__u32 gather_data_words; |
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/** |
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* @bufs_ptr: [in] |
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* |
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* Pointer to an array of drm_tegra_submit_buf structures. |
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*/ |
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__u64 bufs_ptr; |
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/** |
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* @cmds_ptr: [in] |
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* |
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* Pointer to an array of drm_tegra_submit_cmd structures. |
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*/ |
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__u64 cmds_ptr; |
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/** |
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* @gather_data_ptr: [in] |
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* |
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* Pointer to an array of Host1x opcodes to be used by GATHER_UPTR |
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* commands. |
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*/ |
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__u64 gather_data_ptr; |
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/** |
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* @syncobj_in: [in] |
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* |
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* Handle for DRM syncobj that will be waited before submission. |
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* Ignored if zero. |
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*/ |
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__u32 syncobj_in; |
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/** |
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* @syncobj_out: [in] |
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* |
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* Handle for DRM syncobj that will have its fence replaced with |
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* the job's completion fence. Ignored if zero. |
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*/ |
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__u32 syncobj_out; |
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/** |
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* @syncpt_incr: [in,out] |
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* |
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* Information about the syncpoint the job will increment. |
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*/ |
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struct drm_tegra_submit_syncpt syncpt; |
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}; |
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struct drm_tegra_syncpoint_allocate { |
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/** |
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* @id: [out] |
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* |
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* ID of allocated syncpoint. |
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*/ |
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__u32 id; |
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__u32 padding; |
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}; |
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struct drm_tegra_syncpoint_free { |
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/** |
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* @id: [in] |
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* |
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* ID of syncpoint to free. |
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*/ |
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__u32 id; |
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__u32 padding; |
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}; |
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struct drm_tegra_syncpoint_wait { |
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/** |
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* @timeout: [in] |
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* |
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* Absolute timestamp at which the wait will time out. |
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*/ |
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__s64 timeout_ns; |
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/** |
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* @id: [in] |
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* |
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* ID of syncpoint to wait on. |
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*/ |
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__u32 id; |
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/** |
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* @threshold: [in] |
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* |
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* Threshold to wait for. |
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*/ |
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__u32 threshold; |
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/** |
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* @value: [out] |
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* |
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* Value of the syncpoint upon wait completion. |
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*/ |
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__u32 value; |
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__u32 padding; |
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}; |
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#define DRM_IOCTL_TEGRA_CHANNEL_OPEN DRM_IOWR(DRM_COMMAND_BASE + 0x10, struct drm_tegra_channel_open) |
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#define DRM_IOCTL_TEGRA_CHANNEL_CLOSE DRM_IOWR(DRM_COMMAND_BASE + 0x11, struct drm_tegra_channel_close) |
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#define DRM_IOCTL_TEGRA_CHANNEL_MAP DRM_IOWR(DRM_COMMAND_BASE + 0x12, struct drm_tegra_channel_map) |
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#define DRM_IOCTL_TEGRA_CHANNEL_UNMAP DRM_IOWR(DRM_COMMAND_BASE + 0x13, struct drm_tegra_channel_unmap) |
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#define DRM_IOCTL_TEGRA_CHANNEL_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + 0x14, struct drm_tegra_channel_submit) |
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#define DRM_IOCTL_TEGRA_SYNCPOINT_ALLOCATE DRM_IOWR(DRM_COMMAND_BASE + 0x20, struct drm_tegra_syncpoint_allocate) |
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#define DRM_IOCTL_TEGRA_SYNCPOINT_FREE DRM_IOWR(DRM_COMMAND_BASE + 0x21, struct drm_tegra_syncpoint_free) |
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#define DRM_IOCTL_TEGRA_SYNCPOINT_WAIT DRM_IOWR(DRM_COMMAND_BASE + 0x22, struct drm_tegra_syncpoint_wait) |
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#if defined(__cplusplus) |
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} |
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#endif |
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#endif
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