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680 lines
17 KiB
680 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// |
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// Xilinx ASoC audio formatter support |
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// |
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// Copyright (C) 2018 Xilinx, Inc. |
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// |
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// Author: Maruthi Srinivas Bayyavarapu <[email protected]> |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/sizes.h> |
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#include <sound/asoundef.h> |
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#include <sound/soc.h> |
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#include <sound/pcm_params.h> |
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#define DRV_NAME "xlnx_formatter_pcm" |
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#define XLNX_S2MM_OFFSET 0 |
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#define XLNX_MM2S_OFFSET 0x100 |
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#define XLNX_AUD_CORE_CONFIG 0x4 |
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#define XLNX_AUD_CTRL 0x10 |
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#define XLNX_AUD_STS 0x14 |
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#define AUD_CTRL_RESET_MASK BIT(1) |
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#define AUD_CFG_MM2S_MASK BIT(15) |
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#define AUD_CFG_S2MM_MASK BIT(31) |
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#define XLNX_AUD_FS_MULTIPLIER 0x18 |
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#define XLNX_AUD_PERIOD_CONFIG 0x1C |
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#define XLNX_AUD_BUFF_ADDR_LSB 0x20 |
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#define XLNX_AUD_BUFF_ADDR_MSB 0x24 |
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#define XLNX_AUD_XFER_COUNT 0x28 |
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#define XLNX_AUD_CH_STS_START 0x2C |
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#define XLNX_BYTES_PER_CH 0x44 |
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#define AUD_STS_IOC_IRQ_MASK BIT(31) |
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#define AUD_STS_CH_STS_MASK BIT(29) |
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#define AUD_CTRL_IOC_IRQ_MASK BIT(13) |
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#define AUD_CTRL_TOUT_IRQ_MASK BIT(14) |
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#define AUD_CTRL_DMA_EN_MASK BIT(0) |
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#define CFG_MM2S_CH_MASK GENMASK(11, 8) |
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#define CFG_MM2S_CH_SHIFT 8 |
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#define CFG_MM2S_XFER_MASK GENMASK(14, 13) |
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#define CFG_MM2S_XFER_SHIFT 13 |
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#define CFG_MM2S_PKG_MASK BIT(12) |
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#define CFG_S2MM_CH_MASK GENMASK(27, 24) |
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#define CFG_S2MM_CH_SHIFT 24 |
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#define CFG_S2MM_XFER_MASK GENMASK(30, 29) |
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#define CFG_S2MM_XFER_SHIFT 29 |
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#define CFG_S2MM_PKG_MASK BIT(28) |
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#define AUD_CTRL_DATA_WIDTH_SHIFT 16 |
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#define AUD_CTRL_ACTIVE_CH_SHIFT 19 |
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#define PERIOD_CFG_PERIODS_SHIFT 16 |
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#define PERIODS_MIN 2 |
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#define PERIODS_MAX 6 |
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#define PERIOD_BYTES_MIN 192 |
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#define PERIOD_BYTES_MAX (50 * 1024) |
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#define XLNX_PARAM_UNKNOWN 0 |
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enum bit_depth { |
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BIT_DEPTH_8, |
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BIT_DEPTH_16, |
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BIT_DEPTH_20, |
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BIT_DEPTH_24, |
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BIT_DEPTH_32, |
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}; |
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struct xlnx_pcm_drv_data { |
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void __iomem *mmio; |
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bool s2mm_presence; |
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bool mm2s_presence; |
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int s2mm_irq; |
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int mm2s_irq; |
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struct snd_pcm_substream *play_stream; |
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struct snd_pcm_substream *capture_stream; |
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struct clk *axi_clk; |
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}; |
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/* |
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* struct xlnx_pcm_stream_param - stream configuration |
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* @mmio: base address offset |
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* @interleaved: audio channels arrangement in buffer |
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* @xfer_mode: data formatting mode during transfer |
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* @ch_limit: Maximum channels supported |
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* @buffer_size: stream ring buffer size |
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*/ |
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struct xlnx_pcm_stream_param { |
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void __iomem *mmio; |
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bool interleaved; |
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u32 xfer_mode; |
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u32 ch_limit; |
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u64 buffer_size; |
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}; |
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static const struct snd_pcm_hardware xlnx_pcm_hardware = { |
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.info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | |
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SNDRV_PCM_INFO_BATCH | SNDRV_PCM_INFO_PAUSE | |
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SNDRV_PCM_INFO_RESUME, |
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.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | |
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SNDRV_PCM_FMTBIT_S24_LE, |
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.channels_min = 2, |
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.channels_max = 2, |
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.rates = SNDRV_PCM_RATE_8000_192000, |
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.rate_min = 8000, |
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.rate_max = 192000, |
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.buffer_bytes_max = PERIODS_MAX * PERIOD_BYTES_MAX, |
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.period_bytes_min = PERIOD_BYTES_MIN, |
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.period_bytes_max = PERIOD_BYTES_MAX, |
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.periods_min = PERIODS_MIN, |
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.periods_max = PERIODS_MAX, |
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}; |
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enum { |
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AES_TO_AES, |
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AES_TO_PCM, |
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PCM_TO_PCM, |
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PCM_TO_AES |
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}; |
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static void xlnx_parse_aes_params(u32 chsts_reg1_val, u32 chsts_reg2_val, |
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struct device *dev) |
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{ |
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u32 padded, srate, bit_depth, status[2]; |
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if (chsts_reg1_val & IEC958_AES0_PROFESSIONAL) { |
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status[0] = chsts_reg1_val & 0xff; |
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status[1] = (chsts_reg1_val >> 16) & 0xff; |
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switch (status[0] & IEC958_AES0_PRO_FS) { |
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case IEC958_AES0_PRO_FS_44100: |
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srate = 44100; |
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break; |
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case IEC958_AES0_PRO_FS_48000: |
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srate = 48000; |
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break; |
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case IEC958_AES0_PRO_FS_32000: |
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srate = 32000; |
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break; |
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case IEC958_AES0_PRO_FS_NOTID: |
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default: |
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srate = XLNX_PARAM_UNKNOWN; |
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break; |
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} |
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switch (status[1] & IEC958_AES2_PRO_SBITS) { |
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case IEC958_AES2_PRO_WORDLEN_NOTID: |
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case IEC958_AES2_PRO_SBITS_20: |
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padded = 0; |
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break; |
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case IEC958_AES2_PRO_SBITS_24: |
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padded = 4; |
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break; |
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default: |
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bit_depth = XLNX_PARAM_UNKNOWN; |
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goto log_params; |
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} |
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switch (status[1] & IEC958_AES2_PRO_WORDLEN) { |
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case IEC958_AES2_PRO_WORDLEN_20_16: |
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bit_depth = 16 + padded; |
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break; |
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case IEC958_AES2_PRO_WORDLEN_22_18: |
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bit_depth = 18 + padded; |
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break; |
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case IEC958_AES2_PRO_WORDLEN_23_19: |
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bit_depth = 19 + padded; |
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break; |
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case IEC958_AES2_PRO_WORDLEN_24_20: |
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bit_depth = 20 + padded; |
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break; |
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case IEC958_AES2_PRO_WORDLEN_NOTID: |
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default: |
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bit_depth = XLNX_PARAM_UNKNOWN; |
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break; |
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} |
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} else { |
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status[0] = (chsts_reg1_val >> 24) & 0xff; |
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status[1] = chsts_reg2_val & 0xff; |
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switch (status[0] & IEC958_AES3_CON_FS) { |
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case IEC958_AES3_CON_FS_44100: |
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srate = 44100; |
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break; |
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case IEC958_AES3_CON_FS_48000: |
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srate = 48000; |
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break; |
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case IEC958_AES3_CON_FS_32000: |
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srate = 32000; |
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break; |
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default: |
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srate = XLNX_PARAM_UNKNOWN; |
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break; |
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} |
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if (status[1] & IEC958_AES4_CON_MAX_WORDLEN_24) |
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padded = 4; |
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else |
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padded = 0; |
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switch (status[1] & IEC958_AES4_CON_WORDLEN) { |
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case IEC958_AES4_CON_WORDLEN_20_16: |
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bit_depth = 16 + padded; |
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break; |
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case IEC958_AES4_CON_WORDLEN_22_18: |
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bit_depth = 18 + padded; |
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break; |
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case IEC958_AES4_CON_WORDLEN_23_19: |
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bit_depth = 19 + padded; |
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break; |
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case IEC958_AES4_CON_WORDLEN_24_20: |
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bit_depth = 20 + padded; |
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break; |
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case IEC958_AES4_CON_WORDLEN_21_17: |
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bit_depth = 17 + padded; |
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break; |
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case IEC958_AES4_CON_WORDLEN_NOTID: |
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default: |
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bit_depth = XLNX_PARAM_UNKNOWN; |
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break; |
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} |
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} |
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log_params: |
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if (srate != XLNX_PARAM_UNKNOWN) |
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dev_info(dev, "sample rate = %d\n", srate); |
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else |
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dev_info(dev, "sample rate = unknown\n"); |
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if (bit_depth != XLNX_PARAM_UNKNOWN) |
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dev_info(dev, "bit_depth = %d\n", bit_depth); |
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else |
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dev_info(dev, "bit_depth = unknown\n"); |
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} |
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static int xlnx_formatter_pcm_reset(void __iomem *mmio_base) |
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{ |
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u32 val, retries = 0; |
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val = readl(mmio_base + XLNX_AUD_CTRL); |
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val |= AUD_CTRL_RESET_MASK; |
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writel(val, mmio_base + XLNX_AUD_CTRL); |
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val = readl(mmio_base + XLNX_AUD_CTRL); |
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/* Poll for maximum timeout of approximately 100ms (1 * 100)*/ |
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while ((val & AUD_CTRL_RESET_MASK) && (retries < 100)) { |
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mdelay(1); |
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retries++; |
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val = readl(mmio_base + XLNX_AUD_CTRL); |
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} |
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if (val & AUD_CTRL_RESET_MASK) |
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return -ENODEV; |
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return 0; |
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} |
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static void xlnx_formatter_disable_irqs(void __iomem *mmio_base, int stream) |
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{ |
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u32 val; |
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val = readl(mmio_base + XLNX_AUD_CTRL); |
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val &= ~AUD_CTRL_IOC_IRQ_MASK; |
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if (stream == SNDRV_PCM_STREAM_CAPTURE) |
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val &= ~AUD_CTRL_TOUT_IRQ_MASK; |
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writel(val, mmio_base + XLNX_AUD_CTRL); |
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} |
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static irqreturn_t xlnx_mm2s_irq_handler(int irq, void *arg) |
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{ |
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u32 val; |
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void __iomem *reg; |
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struct device *dev = arg; |
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struct xlnx_pcm_drv_data *adata = dev_get_drvdata(dev); |
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reg = adata->mmio + XLNX_MM2S_OFFSET + XLNX_AUD_STS; |
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val = readl(reg); |
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if (val & AUD_STS_IOC_IRQ_MASK) { |
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writel(val & AUD_STS_IOC_IRQ_MASK, reg); |
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if (adata->play_stream) |
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snd_pcm_period_elapsed(adata->play_stream); |
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return IRQ_HANDLED; |
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} |
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return IRQ_NONE; |
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} |
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static irqreturn_t xlnx_s2mm_irq_handler(int irq, void *arg) |
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{ |
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u32 val; |
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void __iomem *reg; |
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struct device *dev = arg; |
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struct xlnx_pcm_drv_data *adata = dev_get_drvdata(dev); |
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reg = adata->mmio + XLNX_S2MM_OFFSET + XLNX_AUD_STS; |
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val = readl(reg); |
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if (val & AUD_STS_IOC_IRQ_MASK) { |
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writel(val & AUD_STS_IOC_IRQ_MASK, reg); |
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if (adata->capture_stream) |
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snd_pcm_period_elapsed(adata->capture_stream); |
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return IRQ_HANDLED; |
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} |
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return IRQ_NONE; |
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} |
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static int xlnx_formatter_pcm_open(struct snd_soc_component *component, |
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struct snd_pcm_substream *substream) |
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{ |
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int err; |
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u32 val, data_format_mode; |
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u32 ch_count_mask, ch_count_shift, data_xfer_mode, data_xfer_shift; |
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struct xlnx_pcm_stream_param *stream_data; |
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struct snd_pcm_runtime *runtime = substream->runtime; |
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struct xlnx_pcm_drv_data *adata = dev_get_drvdata(component->dev); |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && |
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!adata->mm2s_presence) |
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return -ENODEV; |
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else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && |
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!adata->s2mm_presence) |
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return -ENODEV; |
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stream_data = kzalloc(sizeof(*stream_data), GFP_KERNEL); |
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if (!stream_data) |
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return -ENOMEM; |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
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ch_count_mask = CFG_MM2S_CH_MASK; |
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ch_count_shift = CFG_MM2S_CH_SHIFT; |
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data_xfer_mode = CFG_MM2S_XFER_MASK; |
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data_xfer_shift = CFG_MM2S_XFER_SHIFT; |
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data_format_mode = CFG_MM2S_PKG_MASK; |
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stream_data->mmio = adata->mmio + XLNX_MM2S_OFFSET; |
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adata->play_stream = substream; |
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} else { |
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ch_count_mask = CFG_S2MM_CH_MASK; |
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ch_count_shift = CFG_S2MM_CH_SHIFT; |
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data_xfer_mode = CFG_S2MM_XFER_MASK; |
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data_xfer_shift = CFG_S2MM_XFER_SHIFT; |
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data_format_mode = CFG_S2MM_PKG_MASK; |
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stream_data->mmio = adata->mmio + XLNX_S2MM_OFFSET; |
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adata->capture_stream = substream; |
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} |
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val = readl(adata->mmio + XLNX_AUD_CORE_CONFIG); |
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if (!(val & data_format_mode)) |
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stream_data->interleaved = true; |
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stream_data->xfer_mode = (val & data_xfer_mode) >> data_xfer_shift; |
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stream_data->ch_limit = (val & ch_count_mask) >> ch_count_shift; |
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dev_info(component->dev, |
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"stream %d : format = %d mode = %d ch_limit = %d\n", |
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substream->stream, stream_data->interleaved, |
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stream_data->xfer_mode, stream_data->ch_limit); |
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snd_soc_set_runtime_hwparams(substream, &xlnx_pcm_hardware); |
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runtime->private_data = stream_data; |
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/* Resize the period size divisible by 64 */ |
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err = snd_pcm_hw_constraint_step(runtime, 0, |
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SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64); |
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if (err) { |
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dev_err(component->dev, |
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"unable to set constraint on period bytes\n"); |
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return err; |
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} |
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/* enable DMA IOC irq */ |
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val = readl(stream_data->mmio + XLNX_AUD_CTRL); |
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val |= AUD_CTRL_IOC_IRQ_MASK; |
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writel(val, stream_data->mmio + XLNX_AUD_CTRL); |
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return 0; |
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} |
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static int xlnx_formatter_pcm_close(struct snd_soc_component *component, |
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struct snd_pcm_substream *substream) |
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{ |
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int ret; |
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struct xlnx_pcm_stream_param *stream_data = |
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substream->runtime->private_data; |
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ret = xlnx_formatter_pcm_reset(stream_data->mmio); |
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if (ret) { |
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dev_err(component->dev, "audio formatter reset failed\n"); |
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goto err_reset; |
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} |
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xlnx_formatter_disable_irqs(stream_data->mmio, substream->stream); |
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err_reset: |
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kfree(stream_data); |
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return 0; |
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} |
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static snd_pcm_uframes_t |
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xlnx_formatter_pcm_pointer(struct snd_soc_component *component, |
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struct snd_pcm_substream *substream) |
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{ |
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u32 pos; |
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struct snd_pcm_runtime *runtime = substream->runtime; |
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struct xlnx_pcm_stream_param *stream_data = runtime->private_data; |
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pos = readl(stream_data->mmio + XLNX_AUD_XFER_COUNT); |
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if (pos >= stream_data->buffer_size) |
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pos = 0; |
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return bytes_to_frames(runtime, pos); |
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} |
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static int xlnx_formatter_pcm_hw_params(struct snd_soc_component *component, |
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struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params) |
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{ |
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u32 low, high, active_ch, val, bytes_per_ch, bits_per_sample; |
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u32 aes_reg1_val, aes_reg2_val; |
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u64 size; |
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struct snd_pcm_runtime *runtime = substream->runtime; |
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struct xlnx_pcm_stream_param *stream_data = runtime->private_data; |
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active_ch = params_channels(params); |
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if (active_ch > stream_data->ch_limit) |
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return -EINVAL; |
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && |
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stream_data->xfer_mode == AES_TO_PCM) { |
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val = readl(stream_data->mmio + XLNX_AUD_STS); |
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if (val & AUD_STS_CH_STS_MASK) { |
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aes_reg1_val = readl(stream_data->mmio + |
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XLNX_AUD_CH_STS_START); |
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aes_reg2_val = readl(stream_data->mmio + |
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XLNX_AUD_CH_STS_START + 0x4); |
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xlnx_parse_aes_params(aes_reg1_val, aes_reg2_val, |
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component->dev); |
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} |
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} |
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size = params_buffer_bytes(params); |
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stream_data->buffer_size = size; |
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low = lower_32_bits(runtime->dma_addr); |
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high = upper_32_bits(runtime->dma_addr); |
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writel(low, stream_data->mmio + XLNX_AUD_BUFF_ADDR_LSB); |
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writel(high, stream_data->mmio + XLNX_AUD_BUFF_ADDR_MSB); |
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val = readl(stream_data->mmio + XLNX_AUD_CTRL); |
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bits_per_sample = params_width(params); |
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switch (bits_per_sample) { |
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case 8: |
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val |= (BIT_DEPTH_8 << AUD_CTRL_DATA_WIDTH_SHIFT); |
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break; |
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case 16: |
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val |= (BIT_DEPTH_16 << AUD_CTRL_DATA_WIDTH_SHIFT); |
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break; |
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case 20: |
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val |= (BIT_DEPTH_20 << AUD_CTRL_DATA_WIDTH_SHIFT); |
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break; |
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case 24: |
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val |= (BIT_DEPTH_24 << AUD_CTRL_DATA_WIDTH_SHIFT); |
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break; |
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case 32: |
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val |= (BIT_DEPTH_32 << AUD_CTRL_DATA_WIDTH_SHIFT); |
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break; |
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default: |
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return -EINVAL; |
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} |
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val |= active_ch << AUD_CTRL_ACTIVE_CH_SHIFT; |
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writel(val, stream_data->mmio + XLNX_AUD_CTRL); |
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val = (params_periods(params) << PERIOD_CFG_PERIODS_SHIFT) |
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| params_period_bytes(params); |
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writel(val, stream_data->mmio + XLNX_AUD_PERIOD_CONFIG); |
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bytes_per_ch = DIV_ROUND_UP(params_period_bytes(params), active_ch); |
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writel(bytes_per_ch, stream_data->mmio + XLNX_BYTES_PER_CH); |
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return 0; |
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} |
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static int xlnx_formatter_pcm_trigger(struct snd_soc_component *component, |
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struct snd_pcm_substream *substream, |
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int cmd) |
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{ |
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u32 val; |
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struct xlnx_pcm_stream_param *stream_data = |
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substream->runtime->private_data; |
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switch (cmd) { |
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case SNDRV_PCM_TRIGGER_START: |
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
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case SNDRV_PCM_TRIGGER_RESUME: |
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val = readl(stream_data->mmio + XLNX_AUD_CTRL); |
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val |= AUD_CTRL_DMA_EN_MASK; |
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writel(val, stream_data->mmio + XLNX_AUD_CTRL); |
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break; |
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case SNDRV_PCM_TRIGGER_STOP: |
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
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case SNDRV_PCM_TRIGGER_SUSPEND: |
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val = readl(stream_data->mmio + XLNX_AUD_CTRL); |
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val &= ~AUD_CTRL_DMA_EN_MASK; |
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writel(val, stream_data->mmio + XLNX_AUD_CTRL); |
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break; |
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} |
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return 0; |
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} |
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|
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static int xlnx_formatter_pcm_new(struct snd_soc_component *component, |
|
struct snd_soc_pcm_runtime *rtd) |
|
{ |
|
snd_pcm_set_managed_buffer_all(rtd->pcm, |
|
SNDRV_DMA_TYPE_DEV, component->dev, |
|
xlnx_pcm_hardware.buffer_bytes_max, |
|
xlnx_pcm_hardware.buffer_bytes_max); |
|
return 0; |
|
} |
|
|
|
static const struct snd_soc_component_driver xlnx_asoc_component = { |
|
.name = DRV_NAME, |
|
.open = xlnx_formatter_pcm_open, |
|
.close = xlnx_formatter_pcm_close, |
|
.hw_params = xlnx_formatter_pcm_hw_params, |
|
.trigger = xlnx_formatter_pcm_trigger, |
|
.pointer = xlnx_formatter_pcm_pointer, |
|
.pcm_construct = xlnx_formatter_pcm_new, |
|
}; |
|
|
|
static int xlnx_formatter_pcm_probe(struct platform_device *pdev) |
|
{ |
|
int ret; |
|
u32 val; |
|
struct xlnx_pcm_drv_data *aud_drv_data; |
|
struct device *dev = &pdev->dev; |
|
|
|
aud_drv_data = devm_kzalloc(dev, sizeof(*aud_drv_data), GFP_KERNEL); |
|
if (!aud_drv_data) |
|
return -ENOMEM; |
|
|
|
aud_drv_data->axi_clk = devm_clk_get(dev, "s_axi_lite_aclk"); |
|
if (IS_ERR(aud_drv_data->axi_clk)) { |
|
ret = PTR_ERR(aud_drv_data->axi_clk); |
|
dev_err(dev, "failed to get s_axi_lite_aclk(%d)\n", ret); |
|
return ret; |
|
} |
|
ret = clk_prepare_enable(aud_drv_data->axi_clk); |
|
if (ret) { |
|
dev_err(dev, |
|
"failed to enable s_axi_lite_aclk(%d)\n", ret); |
|
return ret; |
|
} |
|
|
|
aud_drv_data->mmio = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(aud_drv_data->mmio)) { |
|
dev_err(dev, "audio formatter ioremap failed\n"); |
|
ret = PTR_ERR(aud_drv_data->mmio); |
|
goto clk_err; |
|
} |
|
|
|
val = readl(aud_drv_data->mmio + XLNX_AUD_CORE_CONFIG); |
|
if (val & AUD_CFG_MM2S_MASK) { |
|
aud_drv_data->mm2s_presence = true; |
|
ret = xlnx_formatter_pcm_reset(aud_drv_data->mmio + |
|
XLNX_MM2S_OFFSET); |
|
if (ret) { |
|
dev_err(dev, "audio formatter reset failed\n"); |
|
goto clk_err; |
|
} |
|
xlnx_formatter_disable_irqs(aud_drv_data->mmio + |
|
XLNX_MM2S_OFFSET, |
|
SNDRV_PCM_STREAM_PLAYBACK); |
|
|
|
aud_drv_data->mm2s_irq = platform_get_irq_byname(pdev, |
|
"irq_mm2s"); |
|
if (aud_drv_data->mm2s_irq < 0) { |
|
ret = aud_drv_data->mm2s_irq; |
|
goto clk_err; |
|
} |
|
ret = devm_request_irq(dev, aud_drv_data->mm2s_irq, |
|
xlnx_mm2s_irq_handler, 0, |
|
"xlnx_formatter_pcm_mm2s_irq", dev); |
|
if (ret) { |
|
dev_err(dev, "xlnx audio mm2s irq request failed\n"); |
|
goto clk_err; |
|
} |
|
} |
|
if (val & AUD_CFG_S2MM_MASK) { |
|
aud_drv_data->s2mm_presence = true; |
|
ret = xlnx_formatter_pcm_reset(aud_drv_data->mmio + |
|
XLNX_S2MM_OFFSET); |
|
if (ret) { |
|
dev_err(dev, "audio formatter reset failed\n"); |
|
goto clk_err; |
|
} |
|
xlnx_formatter_disable_irqs(aud_drv_data->mmio + |
|
XLNX_S2MM_OFFSET, |
|
SNDRV_PCM_STREAM_CAPTURE); |
|
|
|
aud_drv_data->s2mm_irq = platform_get_irq_byname(pdev, |
|
"irq_s2mm"); |
|
if (aud_drv_data->s2mm_irq < 0) { |
|
ret = aud_drv_data->s2mm_irq; |
|
goto clk_err; |
|
} |
|
ret = devm_request_irq(dev, aud_drv_data->s2mm_irq, |
|
xlnx_s2mm_irq_handler, 0, |
|
"xlnx_formatter_pcm_s2mm_irq", |
|
dev); |
|
if (ret) { |
|
dev_err(dev, "xlnx audio s2mm irq request failed\n"); |
|
goto clk_err; |
|
} |
|
} |
|
|
|
dev_set_drvdata(dev, aud_drv_data); |
|
|
|
ret = devm_snd_soc_register_component(dev, &xlnx_asoc_component, |
|
NULL, 0); |
|
if (ret) { |
|
dev_err(dev, "pcm platform device register failed\n"); |
|
goto clk_err; |
|
} |
|
|
|
return 0; |
|
|
|
clk_err: |
|
clk_disable_unprepare(aud_drv_data->axi_clk); |
|
return ret; |
|
} |
|
|
|
static int xlnx_formatter_pcm_remove(struct platform_device *pdev) |
|
{ |
|
int ret = 0; |
|
struct xlnx_pcm_drv_data *adata = dev_get_drvdata(&pdev->dev); |
|
|
|
if (adata->s2mm_presence) |
|
ret = xlnx_formatter_pcm_reset(adata->mmio + XLNX_S2MM_OFFSET); |
|
|
|
/* Try MM2S reset, even if S2MM reset fails */ |
|
if (adata->mm2s_presence) |
|
ret = xlnx_formatter_pcm_reset(adata->mmio + XLNX_MM2S_OFFSET); |
|
|
|
if (ret) |
|
dev_err(&pdev->dev, "audio formatter reset failed\n"); |
|
|
|
clk_disable_unprepare(adata->axi_clk); |
|
return ret; |
|
} |
|
|
|
static const struct of_device_id xlnx_formatter_pcm_of_match[] = { |
|
{ .compatible = "xlnx,audio-formatter-1.0"}, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, xlnx_formatter_pcm_of_match); |
|
|
|
static struct platform_driver xlnx_formatter_pcm_driver = { |
|
.probe = xlnx_formatter_pcm_probe, |
|
.remove = xlnx_formatter_pcm_remove, |
|
.driver = { |
|
.name = DRV_NAME, |
|
.of_match_table = xlnx_formatter_pcm_of_match, |
|
}, |
|
}; |
|
|
|
module_platform_driver(xlnx_formatter_pcm_driver); |
|
MODULE_AUTHOR("Maruthi Srinivas Bayyavarapu <[email protected]>"); |
|
MODULE_LICENSE("GPL v2");
|
|
|