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778 lines
24 KiB
778 lines
24 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* This driver supports the digital controls for the internal codec |
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* found in Allwinner's A33 SoCs. |
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* |
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* (C) Copyright 2010-2016 |
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* Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com> |
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* huangxin <[email protected]> |
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* Mylène Josserand <[email protected]> |
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*/ |
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#include <linux/module.h> |
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#include <linux/delay.h> |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/of_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/regmap.h> |
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#include <linux/log2.h> |
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#include <sound/pcm_params.h> |
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#include <sound/soc.h> |
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#include <sound/soc-dapm.h> |
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#define SUN8I_SYSCLK_CTL 0x00c |
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#define SUN8I_SYSCLK_CTL_AIF1CLK_ENA 11 |
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#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL (0x2 << 8) |
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#define SUN8I_SYSCLK_CTL_AIF2CLK_ENA 7 |
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#define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_PLL (0x2 << 4) |
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#define SUN8I_SYSCLK_CTL_SYSCLK_ENA 3 |
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#define SUN8I_SYSCLK_CTL_SYSCLK_SRC 0 |
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#define SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF1CLK (0x0 << 0) |
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#define SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF2CLK (0x1 << 0) |
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#define SUN8I_MOD_CLK_ENA 0x010 |
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#define SUN8I_MOD_CLK_ENA_AIF1 15 |
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#define SUN8I_MOD_CLK_ENA_ADC 3 |
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#define SUN8I_MOD_CLK_ENA_DAC 2 |
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#define SUN8I_MOD_RST_CTL 0x014 |
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#define SUN8I_MOD_RST_CTL_AIF1 15 |
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#define SUN8I_MOD_RST_CTL_ADC 3 |
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#define SUN8I_MOD_RST_CTL_DAC 2 |
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#define SUN8I_SYS_SR_CTRL 0x018 |
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#define SUN8I_SYS_SR_CTRL_AIF1_FS 12 |
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#define SUN8I_SYS_SR_CTRL_AIF2_FS 8 |
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#define SUN8I_AIF1CLK_CTRL 0x040 |
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#define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD 15 |
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#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV 14 |
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#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV 13 |
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#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9 |
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#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6 |
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#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4 |
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#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16 (1 << 4) |
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#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2 |
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#define SUN8I_AIF1_ADCDAT_CTRL 0x044 |
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#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15 |
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#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14 |
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#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC 10 |
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#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC 8 |
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#define SUN8I_AIF1_DACDAT_CTRL 0x048 |
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#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15 |
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#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14 |
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#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_SRC 10 |
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#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_SRC 8 |
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#define SUN8I_AIF1_MXR_SRC 0x04c |
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#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L 15 |
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#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL 14 |
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#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL 13 |
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#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR 12 |
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#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R 11 |
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#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR 10 |
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#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR 9 |
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#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL 8 |
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#define SUN8I_ADC_DIG_CTRL 0x100 |
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#define SUN8I_ADC_DIG_CTRL_ENAD 15 |
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#define SUN8I_ADC_DIG_CTRL_ADOUT_DTS 2 |
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#define SUN8I_ADC_DIG_CTRL_ADOUT_DLY 1 |
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#define SUN8I_DAC_DIG_CTRL 0x120 |
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#define SUN8I_DAC_DIG_CTRL_ENDA 15 |
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#define SUN8I_DAC_MXR_SRC 0x130 |
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#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L 15 |
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#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L 14 |
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#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL 13 |
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#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL 12 |
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#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R 11 |
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#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R 10 |
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#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR 9 |
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#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8 |
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#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK GENMASK(9, 8) |
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#define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK GENMASK(5, 4) |
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#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12) |
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#define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8) |
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#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9) |
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#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6) |
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#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) |
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#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2) |
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struct sun8i_codec_quirks { |
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bool legacy_widgets : 1; |
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bool lrck_inversion : 1; |
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}; |
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struct sun8i_codec { |
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struct regmap *regmap; |
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struct clk *clk_module; |
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const struct sun8i_codec_quirks *quirks; |
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}; |
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static int sun8i_codec_runtime_resume(struct device *dev) |
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{ |
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struct sun8i_codec *scodec = dev_get_drvdata(dev); |
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int ret; |
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regcache_cache_only(scodec->regmap, false); |
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ret = regcache_sync(scodec->regmap); |
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if (ret) { |
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dev_err(dev, "Failed to sync regmap cache\n"); |
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return ret; |
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} |
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return 0; |
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} |
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static int sun8i_codec_runtime_suspend(struct device *dev) |
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{ |
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struct sun8i_codec *scodec = dev_get_drvdata(dev); |
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regcache_cache_only(scodec->regmap, true); |
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regcache_mark_dirty(scodec->regmap); |
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return 0; |
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} |
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static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params) |
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{ |
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unsigned int rate = params_rate(params); |
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switch (rate) { |
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case 8000: |
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case 7350: |
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return 0x0; |
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case 11025: |
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return 0x1; |
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case 12000: |
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return 0x2; |
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case 16000: |
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return 0x3; |
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case 22050: |
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return 0x4; |
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case 24000: |
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return 0x5; |
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case 32000: |
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return 0x6; |
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case 44100: |
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return 0x7; |
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case 48000: |
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return 0x8; |
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case 96000: |
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return 0x9; |
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case 192000: |
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return 0xa; |
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default: |
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return -EINVAL; |
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} |
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} |
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static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
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{ |
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struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); |
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u32 value; |
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/* clock masters */ |
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
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case SND_SOC_DAIFMT_CBS_CFS: /* Codec slave, DAI master */ |
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value = 0x1; |
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break; |
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case SND_SOC_DAIFMT_CBM_CFM: /* Codec Master, DAI slave */ |
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value = 0x0; |
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break; |
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default: |
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return -EINVAL; |
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} |
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regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, |
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BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD), |
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value << SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD); |
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/* clock inversion */ |
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
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case SND_SOC_DAIFMT_NB_NF: /* Normal */ |
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value = 0x0; |
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break; |
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case SND_SOC_DAIFMT_IB_IF: /* Inversion */ |
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value = 0x1; |
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break; |
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default: |
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return -EINVAL; |
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} |
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regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, |
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BIT(SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV), |
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value << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV); |
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/* |
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* It appears that the DAI and the codec in the A33 SoC don't |
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* share the same polarity for the LRCK signal when they mean |
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* 'normal' and 'inverted' in the datasheet. |
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* |
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* Since the DAI here is our regular i2s driver that have been |
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* tested with way more codecs than just this one, it means |
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* that the codec probably gets it backward, and we have to |
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* invert the value here. |
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*/ |
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value ^= scodec->quirks->lrck_inversion; |
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regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, |
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BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV), |
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value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV); |
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/* DAI format */ |
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
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case SND_SOC_DAIFMT_I2S: |
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value = 0x0; |
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break; |
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case SND_SOC_DAIFMT_LEFT_J: |
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value = 0x1; |
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break; |
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case SND_SOC_DAIFMT_RIGHT_J: |
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value = 0x2; |
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break; |
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case SND_SOC_DAIFMT_DSP_A: |
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case SND_SOC_DAIFMT_DSP_B: |
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value = 0x3; |
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break; |
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default: |
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return -EINVAL; |
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} |
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regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, |
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SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK, |
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value << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT); |
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return 0; |
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} |
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struct sun8i_codec_clk_div { |
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u8 div; |
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u8 val; |
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}; |
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static const struct sun8i_codec_clk_div sun8i_codec_bclk_div[] = { |
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{ .div = 1, .val = 0 }, |
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{ .div = 2, .val = 1 }, |
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{ .div = 4, .val = 2 }, |
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{ .div = 6, .val = 3 }, |
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{ .div = 8, .val = 4 }, |
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{ .div = 12, .val = 5 }, |
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{ .div = 16, .val = 6 }, |
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{ .div = 24, .val = 7 }, |
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{ .div = 32, .val = 8 }, |
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{ .div = 48, .val = 9 }, |
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{ .div = 64, .val = 10 }, |
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{ .div = 96, .val = 11 }, |
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{ .div = 128, .val = 12 }, |
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{ .div = 192, .val = 13 }, |
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}; |
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static u8 sun8i_codec_get_bclk_div(struct sun8i_codec *scodec, |
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unsigned int rate, |
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unsigned int word_size) |
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{ |
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unsigned long clk_rate = clk_get_rate(scodec->clk_module); |
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unsigned int div = clk_rate / rate / word_size / 2; |
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unsigned int best_val = 0, best_diff = ~0; |
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int i; |
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for (i = 0; i < ARRAY_SIZE(sun8i_codec_bclk_div); i++) { |
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const struct sun8i_codec_clk_div *bdiv = &sun8i_codec_bclk_div[i]; |
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unsigned int diff = abs(bdiv->div - div); |
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if (diff < best_diff) { |
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best_diff = diff; |
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best_val = bdiv->val; |
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} |
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} |
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return best_val; |
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} |
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static int sun8i_codec_get_lrck_div(unsigned int channels, |
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unsigned int word_size) |
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{ |
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unsigned int div = word_size * channels; |
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if (div < 16 || div > 256) |
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return -EINVAL; |
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return ilog2(div) - 4; |
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} |
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static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *dai) |
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{ |
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struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); |
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int sample_rate, lrck_div; |
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u8 bclk_div; |
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/* |
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* The CPU DAI handles only a sample of 16 bits. Configure the |
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* codec to handle this type of sample resolution. |
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*/ |
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regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, |
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SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK, |
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SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16); |
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bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), 16); |
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regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, |
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SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK, |
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bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV); |
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lrck_div = sun8i_codec_get_lrck_div(params_channels(params), |
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params_physical_width(params)); |
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if (lrck_div < 0) |
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return lrck_div; |
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regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, |
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SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK, |
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lrck_div << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV); |
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sample_rate = sun8i_codec_get_hw_rate(params); |
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if (sample_rate < 0) |
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return sample_rate; |
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regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, |
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SUN8I_SYS_SR_CTRL_AIF1_FS_MASK, |
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sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS); |
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return 0; |
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} |
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static const char *const sun8i_aif_stereo_mux_enum_values[] = { |
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"Stereo", "Reverse Stereo", "Sum Mono", "Mix Mono" |
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}; |
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static SOC_ENUM_DOUBLE_DECL(sun8i_aif1_ad0_stereo_mux_enum, |
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SUN8I_AIF1_ADCDAT_CTRL, |
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SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC, |
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SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC, |
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sun8i_aif_stereo_mux_enum_values); |
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static const struct snd_kcontrol_new sun8i_aif1_ad0_stereo_mux_control = |
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SOC_DAPM_ENUM("AIF1 AD0 Stereo Capture Route", |
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sun8i_aif1_ad0_stereo_mux_enum); |
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static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = { |
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SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital ADC Capture Switch", |
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SUN8I_AIF1_MXR_SRC, |
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SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L, |
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SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R, 1, 0), |
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SOC_DAPM_DOUBLE("AIF2 Digital ADC Capture Switch", |
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SUN8I_AIF1_MXR_SRC, |
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SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL, |
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SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR, 1, 0), |
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SOC_DAPM_DOUBLE("AIF1 Data Digital ADC Capture Switch", |
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SUN8I_AIF1_MXR_SRC, |
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SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL, |
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SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR, 1, 0), |
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SOC_DAPM_DOUBLE("AIF2 Inv Digital ADC Capture Switch", |
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SUN8I_AIF1_MXR_SRC, |
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SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR, |
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SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0), |
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}; |
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static SOC_ENUM_DOUBLE_DECL(sun8i_aif1_da0_stereo_mux_enum, |
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SUN8I_AIF1_DACDAT_CTRL, |
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SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_SRC, |
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SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_SRC, |
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sun8i_aif_stereo_mux_enum_values); |
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static const struct snd_kcontrol_new sun8i_aif1_da0_stereo_mux_control = |
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SOC_DAPM_ENUM("AIF1 DA0 Stereo Playback Route", |
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sun8i_aif1_da0_stereo_mux_enum); |
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static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { |
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SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch", |
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SUN8I_DAC_MXR_SRC, |
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SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L, |
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SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0), |
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SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Playback Switch", |
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SUN8I_DAC_MXR_SRC, |
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SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L, |
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SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R, 1, 0), |
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SOC_DAPM_DOUBLE("AIF2 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, |
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SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL, |
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SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0), |
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SOC_DAPM_DOUBLE("ADC Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, |
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SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL, |
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SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0), |
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}; |
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static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { |
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/* System Clocks */ |
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SND_SOC_DAPM_CLOCK_SUPPLY("mod"), |
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SND_SOC_DAPM_SUPPLY("AIF1CLK", |
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SUN8I_SYSCLK_CTL, |
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SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("SYSCLK", |
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SUN8I_SYSCLK_CTL, |
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SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0), |
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|
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/* Module Clocks */ |
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SND_SOC_DAPM_SUPPLY("CLK AIF1", |
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SUN8I_MOD_CLK_ENA, |
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SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("CLK ADC", |
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SUN8I_MOD_CLK_ENA, |
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SUN8I_MOD_CLK_ENA_ADC, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("CLK DAC", |
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SUN8I_MOD_CLK_ENA, |
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SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0), |
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|
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/* Module Resets */ |
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SND_SOC_DAPM_SUPPLY("RST AIF1", |
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SUN8I_MOD_RST_CTL, |
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SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("RST ADC", |
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SUN8I_MOD_RST_CTL, |
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SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("RST DAC", |
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SUN8I_MOD_RST_CTL, |
|
SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0), |
|
|
|
/* Module Supplies */ |
|
SND_SOC_DAPM_SUPPLY("ADC", |
|
SUN8I_ADC_DIG_CTRL, |
|
SUN8I_ADC_DIG_CTRL_ENAD, 0, NULL, 0), |
|
SND_SOC_DAPM_SUPPLY("DAC", |
|
SUN8I_DAC_DIG_CTRL, |
|
SUN8I_DAC_DIG_CTRL_ENDA, 0, NULL, 0), |
|
|
|
/* AIF "ADC" Outputs */ |
|
SND_SOC_DAPM_AIF_OUT("AIF1 AD0L", "Capture", 0, |
|
SUN8I_AIF1_ADCDAT_CTRL, |
|
SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0), |
|
SND_SOC_DAPM_AIF_OUT("AIF1 AD0R", "Capture", 1, |
|
SUN8I_AIF1_ADCDAT_CTRL, |
|
SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0), |
|
|
|
/* AIF "ADC" Mono/Stereo Muxes */ |
|
SND_SOC_DAPM_MUX("AIF1 AD0L Stereo Mux", SND_SOC_NOPM, 0, 0, |
|
&sun8i_aif1_ad0_stereo_mux_control), |
|
SND_SOC_DAPM_MUX("AIF1 AD0R Stereo Mux", SND_SOC_NOPM, 0, 0, |
|
&sun8i_aif1_ad0_stereo_mux_control), |
|
|
|
/* AIF "ADC" Mixers */ |
|
SOC_MIXER_ARRAY("AIF1 AD0L Mixer", SND_SOC_NOPM, 0, 0, |
|
sun8i_aif1_ad0_mixer_controls), |
|
SOC_MIXER_ARRAY("AIF1 AD0R Mixer", SND_SOC_NOPM, 0, 0, |
|
sun8i_aif1_ad0_mixer_controls), |
|
|
|
/* AIF "DAC" Mono/Stereo Muxes */ |
|
SND_SOC_DAPM_MUX("AIF1 DA0L Stereo Mux", SND_SOC_NOPM, 0, 0, |
|
&sun8i_aif1_da0_stereo_mux_control), |
|
SND_SOC_DAPM_MUX("AIF1 DA0R Stereo Mux", SND_SOC_NOPM, 0, 0, |
|
&sun8i_aif1_da0_stereo_mux_control), |
|
|
|
/* AIF "DAC" Inputs */ |
|
SND_SOC_DAPM_AIF_IN("AIF1 DA0L", "Playback", 0, |
|
SUN8I_AIF1_DACDAT_CTRL, |
|
SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0), |
|
SND_SOC_DAPM_AIF_IN("AIF1 DA0R", "Playback", 1, |
|
SUN8I_AIF1_DACDAT_CTRL, |
|
SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0), |
|
|
|
/* ADC Inputs (connected to analog codec DAPM context) */ |
|
SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 0, 0), |
|
SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0), |
|
|
|
/* DAC Outputs (connected to analog codec DAPM context) */ |
|
SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), |
|
SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0), |
|
|
|
/* DAC Mixers */ |
|
SOC_MIXER_ARRAY("DACL Mixer", SND_SOC_NOPM, 0, 0, |
|
sun8i_dac_mixer_controls), |
|
SOC_MIXER_ARRAY("DACR Mixer", SND_SOC_NOPM, 0, 0, |
|
sun8i_dac_mixer_controls), |
|
}; |
|
|
|
static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { |
|
/* Clock Routes */ |
|
{ "AIF1CLK", NULL, "mod" }, |
|
|
|
{ "SYSCLK", NULL, "AIF1CLK" }, |
|
|
|
{ "CLK AIF1", NULL, "AIF1CLK" }, |
|
{ "CLK AIF1", NULL, "SYSCLK" }, |
|
{ "RST AIF1", NULL, "CLK AIF1" }, |
|
{ "AIF1 AD0L", NULL, "RST AIF1" }, |
|
{ "AIF1 AD0R", NULL, "RST AIF1" }, |
|
{ "AIF1 DA0L", NULL, "RST AIF1" }, |
|
{ "AIF1 DA0R", NULL, "RST AIF1" }, |
|
|
|
{ "CLK ADC", NULL, "SYSCLK" }, |
|
{ "RST ADC", NULL, "CLK ADC" }, |
|
{ "ADC", NULL, "RST ADC" }, |
|
{ "ADCL", NULL, "ADC" }, |
|
{ "ADCR", NULL, "ADC" }, |
|
|
|
{ "CLK DAC", NULL, "SYSCLK" }, |
|
{ "RST DAC", NULL, "CLK DAC" }, |
|
{ "DAC", NULL, "RST DAC" }, |
|
{ "DACL", NULL, "DAC" }, |
|
{ "DACR", NULL, "DAC" }, |
|
|
|
/* AIF "ADC" Output Routes */ |
|
{ "AIF1 AD0L", NULL, "AIF1 AD0L Stereo Mux" }, |
|
{ "AIF1 AD0R", NULL, "AIF1 AD0R Stereo Mux" }, |
|
|
|
/* AIF "ADC" Mono/Stereo Mux Routes */ |
|
{ "AIF1 AD0L Stereo Mux", "Stereo", "AIF1 AD0L Mixer" }, |
|
{ "AIF1 AD0L Stereo Mux", "Reverse Stereo", "AIF1 AD0R Mixer" }, |
|
{ "AIF1 AD0L Stereo Mux", "Sum Mono", "AIF1 AD0L Mixer" }, |
|
{ "AIF1 AD0L Stereo Mux", "Sum Mono", "AIF1 AD0R Mixer" }, |
|
{ "AIF1 AD0L Stereo Mux", "Mix Mono", "AIF1 AD0L Mixer" }, |
|
{ "AIF1 AD0L Stereo Mux", "Mix Mono", "AIF1 AD0R Mixer" }, |
|
|
|
{ "AIF1 AD0R Stereo Mux", "Stereo", "AIF1 AD0R Mixer" }, |
|
{ "AIF1 AD0R Stereo Mux", "Reverse Stereo", "AIF1 AD0L Mixer" }, |
|
{ "AIF1 AD0R Stereo Mux", "Sum Mono", "AIF1 AD0L Mixer" }, |
|
{ "AIF1 AD0R Stereo Mux", "Sum Mono", "AIF1 AD0R Mixer" }, |
|
{ "AIF1 AD0R Stereo Mux", "Mix Mono", "AIF1 AD0L Mixer" }, |
|
{ "AIF1 AD0R Stereo Mux", "Mix Mono", "AIF1 AD0R Mixer" }, |
|
|
|
/* AIF "ADC" Mixer Routes */ |
|
{ "AIF1 AD0L Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0L Stereo Mux" }, |
|
{ "AIF1 AD0L Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCL" }, |
|
|
|
{ "AIF1 AD0R Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0R Stereo Mux" }, |
|
{ "AIF1 AD0R Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCR" }, |
|
|
|
/* AIF "DAC" Mono/Stereo Mux Routes */ |
|
{ "AIF1 DA0L Stereo Mux", "Stereo", "AIF1 DA0L" }, |
|
{ "AIF1 DA0L Stereo Mux", "Reverse Stereo", "AIF1 DA0R" }, |
|
{ "AIF1 DA0L Stereo Mux", "Sum Mono", "AIF1 DA0L" }, |
|
{ "AIF1 DA0L Stereo Mux", "Sum Mono", "AIF1 DA0R" }, |
|
{ "AIF1 DA0L Stereo Mux", "Mix Mono", "AIF1 DA0L" }, |
|
{ "AIF1 DA0L Stereo Mux", "Mix Mono", "AIF1 DA0R" }, |
|
|
|
{ "AIF1 DA0R Stereo Mux", "Stereo", "AIF1 DA0R" }, |
|
{ "AIF1 DA0R Stereo Mux", "Reverse Stereo", "AIF1 DA0L" }, |
|
{ "AIF1 DA0R Stereo Mux", "Sum Mono", "AIF1 DA0L" }, |
|
{ "AIF1 DA0R Stereo Mux", "Sum Mono", "AIF1 DA0R" }, |
|
{ "AIF1 DA0R Stereo Mux", "Mix Mono", "AIF1 DA0L" }, |
|
{ "AIF1 DA0R Stereo Mux", "Mix Mono", "AIF1 DA0R" }, |
|
|
|
/* DAC Output Routes */ |
|
{ "DACL", NULL, "DACL Mixer" }, |
|
{ "DACR", NULL, "DACR Mixer" }, |
|
|
|
/* DAC Mixer Routes */ |
|
{ "DACL Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0L Stereo Mux" }, |
|
{ "DACL Mixer", "ADC Digital DAC Playback Switch", "ADCL" }, |
|
|
|
{ "DACR Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0R Stereo Mux" }, |
|
{ "DACR Mixer", "ADC Digital DAC Playback Switch", "ADCR" }, |
|
}; |
|
|
|
static const struct snd_soc_dapm_widget sun8i_codec_legacy_widgets[] = { |
|
/* Legacy ADC Inputs (connected to analog codec DAPM context) */ |
|
SND_SOC_DAPM_ADC("AIF1 Slot 0 Left ADC", NULL, SND_SOC_NOPM, 0, 0), |
|
SND_SOC_DAPM_ADC("AIF1 Slot 0 Right ADC", NULL, SND_SOC_NOPM, 0, 0), |
|
|
|
/* Legacy DAC Outputs (connected to analog codec DAPM context) */ |
|
SND_SOC_DAPM_DAC("AIF1 Slot 0 Left", NULL, SND_SOC_NOPM, 0, 0), |
|
SND_SOC_DAPM_DAC("AIF1 Slot 0 Right", NULL, SND_SOC_NOPM, 0, 0), |
|
}; |
|
|
|
static const struct snd_soc_dapm_route sun8i_codec_legacy_routes[] = { |
|
/* Legacy ADC Routes */ |
|
{ "ADCL", NULL, "AIF1 Slot 0 Left ADC" }, |
|
{ "ADCR", NULL, "AIF1 Slot 0 Right ADC" }, |
|
|
|
/* Legacy DAC Routes */ |
|
{ "AIF1 Slot 0 Left", NULL, "DACL" }, |
|
{ "AIF1 Slot 0 Right", NULL, "DACR" }, |
|
}; |
|
|
|
static int sun8i_codec_component_probe(struct snd_soc_component *component) |
|
{ |
|
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); |
|
struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component); |
|
int ret; |
|
|
|
/* Add widgets for backward compatibility with old device trees. */ |
|
if (scodec->quirks->legacy_widgets) { |
|
ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_legacy_widgets, |
|
ARRAY_SIZE(sun8i_codec_legacy_widgets)); |
|
if (ret) |
|
return ret; |
|
|
|
ret = snd_soc_dapm_add_routes(dapm, sun8i_codec_legacy_routes, |
|
ARRAY_SIZE(sun8i_codec_legacy_routes)); |
|
if (ret) |
|
return ret; |
|
} |
|
|
|
/* |
|
* AIF1CLK and AIF2CLK share a pair of clock parents: PLL_AUDIO ("mod") |
|
* and MCLK (from the CPU DAI connected to AIF1). MCLK's parent is also |
|
* PLL_AUDIO, so using it adds no additional flexibility. Use PLL_AUDIO |
|
* directly to simplify the clock tree. |
|
*/ |
|
regmap_update_bits(scodec->regmap, SUN8I_SYSCLK_CTL, |
|
SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK | |
|
SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK, |
|
SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL | |
|
SUN8I_SYSCLK_CTL_AIF2CLK_SRC_PLL); |
|
|
|
/* Use AIF1CLK as the SYSCLK parent since AIF1 is used most often. */ |
|
regmap_update_bits(scodec->regmap, SUN8I_SYSCLK_CTL, |
|
BIT(SUN8I_SYSCLK_CTL_SYSCLK_SRC), |
|
SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF1CLK); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct snd_soc_dai_ops sun8i_codec_dai_ops = { |
|
.hw_params = sun8i_codec_hw_params, |
|
.set_fmt = sun8i_set_fmt, |
|
}; |
|
|
|
static struct snd_soc_dai_driver sun8i_codec_dai = { |
|
.name = "sun8i", |
|
/* playback capabilities */ |
|
.playback = { |
|
.stream_name = "Playback", |
|
.channels_min = 1, |
|
.channels_max = 2, |
|
.rates = SNDRV_PCM_RATE_8000_192000, |
|
.formats = SNDRV_PCM_FMTBIT_S16_LE, |
|
}, |
|
/* capture capabilities */ |
|
.capture = { |
|
.stream_name = "Capture", |
|
.channels_min = 1, |
|
.channels_max = 2, |
|
.rates = SNDRV_PCM_RATE_8000_192000, |
|
.formats = SNDRV_PCM_FMTBIT_S16_LE, |
|
.sig_bits = 24, |
|
}, |
|
/* pcm operations */ |
|
.ops = &sun8i_codec_dai_ops, |
|
}; |
|
|
|
static const struct snd_soc_component_driver sun8i_soc_component = { |
|
.dapm_widgets = sun8i_codec_dapm_widgets, |
|
.num_dapm_widgets = ARRAY_SIZE(sun8i_codec_dapm_widgets), |
|
.dapm_routes = sun8i_codec_dapm_routes, |
|
.num_dapm_routes = ARRAY_SIZE(sun8i_codec_dapm_routes), |
|
.probe = sun8i_codec_component_probe, |
|
.idle_bias_on = 1, |
|
.use_pmdown_time = 1, |
|
.endianness = 1, |
|
.non_legacy_dai_naming = 1, |
|
}; |
|
|
|
static const struct regmap_config sun8i_codec_regmap_config = { |
|
.reg_bits = 32, |
|
.reg_stride = 4, |
|
.val_bits = 32, |
|
.max_register = SUN8I_DAC_MXR_SRC, |
|
|
|
.cache_type = REGCACHE_FLAT, |
|
}; |
|
|
|
static int sun8i_codec_probe(struct platform_device *pdev) |
|
{ |
|
struct sun8i_codec *scodec; |
|
void __iomem *base; |
|
int ret; |
|
|
|
scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL); |
|
if (!scodec) |
|
return -ENOMEM; |
|
|
|
scodec->clk_module = devm_clk_get(&pdev->dev, "mod"); |
|
if (IS_ERR(scodec->clk_module)) { |
|
dev_err(&pdev->dev, "Failed to get the module clock\n"); |
|
return PTR_ERR(scodec->clk_module); |
|
} |
|
|
|
base = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(base)) { |
|
dev_err(&pdev->dev, "Failed to map the registers\n"); |
|
return PTR_ERR(base); |
|
} |
|
|
|
scodec->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "bus", base, |
|
&sun8i_codec_regmap_config); |
|
if (IS_ERR(scodec->regmap)) { |
|
dev_err(&pdev->dev, "Failed to create our regmap\n"); |
|
return PTR_ERR(scodec->regmap); |
|
} |
|
|
|
scodec->quirks = of_device_get_match_data(&pdev->dev); |
|
|
|
platform_set_drvdata(pdev, scodec); |
|
|
|
pm_runtime_enable(&pdev->dev); |
|
if (!pm_runtime_enabled(&pdev->dev)) { |
|
ret = sun8i_codec_runtime_resume(&pdev->dev); |
|
if (ret) |
|
goto err_pm_disable; |
|
} |
|
|
|
ret = devm_snd_soc_register_component(&pdev->dev, &sun8i_soc_component, |
|
&sun8i_codec_dai, 1); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Failed to register codec\n"); |
|
goto err_suspend; |
|
} |
|
|
|
return ret; |
|
|
|
err_suspend: |
|
if (!pm_runtime_status_suspended(&pdev->dev)) |
|
sun8i_codec_runtime_suspend(&pdev->dev); |
|
|
|
err_pm_disable: |
|
pm_runtime_disable(&pdev->dev); |
|
|
|
return ret; |
|
} |
|
|
|
static int sun8i_codec_remove(struct platform_device *pdev) |
|
{ |
|
pm_runtime_disable(&pdev->dev); |
|
if (!pm_runtime_status_suspended(&pdev->dev)) |
|
sun8i_codec_runtime_suspend(&pdev->dev); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct sun8i_codec_quirks sun8i_a33_quirks = { |
|
.legacy_widgets = true, |
|
.lrck_inversion = true, |
|
}; |
|
|
|
static const struct sun8i_codec_quirks sun50i_a64_quirks = { |
|
}; |
|
|
|
static const struct of_device_id sun8i_codec_of_match[] = { |
|
{ .compatible = "allwinner,sun8i-a33-codec", .data = &sun8i_a33_quirks }, |
|
{ .compatible = "allwinner,sun50i-a64-codec", .data = &sun50i_a64_quirks }, |
|
{} |
|
}; |
|
MODULE_DEVICE_TABLE(of, sun8i_codec_of_match); |
|
|
|
static const struct dev_pm_ops sun8i_codec_pm_ops = { |
|
SET_RUNTIME_PM_OPS(sun8i_codec_runtime_suspend, |
|
sun8i_codec_runtime_resume, NULL) |
|
}; |
|
|
|
static struct platform_driver sun8i_codec_driver = { |
|
.driver = { |
|
.name = "sun8i-codec", |
|
.of_match_table = sun8i_codec_of_match, |
|
.pm = &sun8i_codec_pm_ops, |
|
}, |
|
.probe = sun8i_codec_probe, |
|
.remove = sun8i_codec_remove, |
|
}; |
|
module_platform_driver(sun8i_codec_driver); |
|
|
|
MODULE_DESCRIPTION("Allwinner A33 (sun8i) codec driver"); |
|
MODULE_AUTHOR("Mylène Josserand <[email protected]>"); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_ALIAS("platform:sun8i-codec");
|
|
|