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650 lines
19 KiB
650 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* ATI Mach64 CT/VT/GT/LT Support |
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*/ |
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#include <linux/fb.h> |
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#include <linux/delay.h> |
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#include <asm/io.h> |
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#include <video/mach64.h> |
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#include "atyfb.h" |
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#ifdef CONFIG_PPC |
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#include <asm/machdep.h> |
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#endif |
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#undef DEBUG |
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static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll); |
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static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll); |
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static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll); |
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static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll); |
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u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par) |
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{ |
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u8 res; |
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/* write addr byte */ |
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aty_st_8(CLOCK_CNTL_ADDR, (offset << 2) & PLL_ADDR, par); |
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/* read the register value */ |
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res = aty_ld_8(CLOCK_CNTL_DATA, par); |
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return res; |
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} |
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static void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par) |
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{ |
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/* write addr byte */ |
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aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) | PLL_WR_EN, par); |
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/* write the register value */ |
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aty_st_8(CLOCK_CNTL_DATA, val & PLL_DATA, par); |
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aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) & ~PLL_WR_EN, par); |
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} |
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/* |
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* by Daniel Mantione |
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* <[email protected]> |
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* |
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* |
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* ATI Mach64 CT clock synthesis description. |
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* |
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* All clocks on the Mach64 can be calculated using the same principle: |
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* |
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* XTALIN * x * FB_DIV |
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* CLK = ---------------------- |
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* PLL_REF_DIV * POST_DIV |
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* |
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* XTALIN is a fixed speed clock. Common speeds are 14.31 MHz and 29.50 MHz. |
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* PLL_REF_DIV can be set by the user, but is the same for all clocks. |
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* FB_DIV can be set by the user for each clock individually, it should be set |
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* between 128 and 255, the chip will generate a bad clock signal for too low |
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* values. |
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* x depends on the type of clock; usually it is 2, but for the MCLK it can also |
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* be set to 4. |
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* POST_DIV can be set by the user for each clock individually, Possible values |
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* are 1,2,4,8 and for some clocks other values are available too. |
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* CLK is of course the clock speed that is generated. |
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* |
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* The Mach64 has these clocks: |
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* |
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* MCLK The clock rate of the chip |
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* XCLK The clock rate of the on-chip memory |
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* VCLK0 First pixel clock of first CRT controller |
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* VCLK1 Second pixel clock of first CRT controller |
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* VCLK2 Third pixel clock of first CRT controller |
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* VCLK3 Fourth pixel clock of first CRT controller |
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* VCLK Selected pixel clock, one of VCLK0, VCLK1, VCLK2, VCLK3 |
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* V2CLK Pixel clock of the second CRT controller. |
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* SCLK Multi-purpose clock |
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* |
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* - MCLK and XCLK use the same FB_DIV |
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* - VCLK0 .. VCLK3 use the same FB_DIV |
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* - V2CLK is needed when the second CRTC is used (can be used for dualhead); |
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* i.e. CRT monitor connected to laptop has different resolution than built |
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* in LCD monitor. |
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* - SCLK is not available on all cards; it is know to exist on the Rage LT-PRO, |
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* Rage XL and Rage Mobility. It is know not to exist on the Mach64 VT. |
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* - V2CLK is not available on all cards, most likely only the Rage LT-PRO, |
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* the Rage XL and the Rage Mobility |
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* |
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* SCLK can be used to: |
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* - Clock the chip instead of MCLK |
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* - Replace XTALIN with a user defined frequency |
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* - Generate the pixel clock for the LCD monitor (instead of VCLK) |
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*/ |
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/* |
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* It can be quite hard to calculate XCLK and MCLK if they don't run at the |
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* same frequency. Luckily, until now all cards that need asynchrone clock |
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* speeds seem to have SCLK. |
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* So this driver uses SCLK to clock the chip and XCLK to clock the memory. |
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*/ |
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/* ------------------------------------------------------------------------- */ |
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/* |
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* PLL programming (Mach64 CT family) |
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* |
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* |
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* This procedure sets the display fifo. The display fifo is a buffer that |
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* contains data read from the video memory that waits to be processed by |
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* the CRT controller. |
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* |
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* On the more modern Mach64 variants, the chip doesn't calculate the |
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* interval after which the display fifo has to be reloaded from memory |
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* automatically, the driver has to do it instead. |
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*/ |
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#define Maximum_DSP_PRECISION 7 |
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const u8 aty_postdividers[8] = {1,2,4,8,3,5,6,12}; |
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static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll) |
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{ |
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u32 dsp_off, dsp_on, dsp_xclks; |
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u32 multiplier, divider, ras_multiplier, ras_divider, tmp; |
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u8 vshift, xshift; |
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s8 dsp_precision; |
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multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real; |
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divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div; |
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ras_multiplier = pll->xclkmaxrasdelay; |
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ras_divider = 1; |
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if (bpp>=8) |
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divider = divider * (bpp >> 2); |
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vshift = (6 - 2) - pll->xclk_post_div; /* FIFO is 64 bits wide in accelerator mode ... */ |
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if (bpp == 0) |
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vshift--; /* ... but only 32 bits in VGA mode. */ |
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#ifdef CONFIG_FB_ATY_GENERIC_LCD |
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if (pll->xres != 0) { |
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struct atyfb_par *par = (struct atyfb_par *) info->par; |
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multiplier = multiplier * par->lcd_width; |
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divider = divider * pll->xres & ~7; |
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ras_multiplier = ras_multiplier * par->lcd_width; |
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ras_divider = ras_divider * pll->xres & ~7; |
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} |
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#endif |
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/* If we don't do this, 32 bits for multiplier & divider won't be |
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enough in certain situations! */ |
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while (((multiplier | divider) & 1) == 0) { |
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multiplier = multiplier >> 1; |
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divider = divider >> 1; |
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} |
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/* Determine DSP precision first */ |
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tmp = ((multiplier * pll->fifo_size) << vshift) / divider; |
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for (dsp_precision = -5; tmp; dsp_precision++) |
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tmp >>= 1; |
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if (dsp_precision < 0) |
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dsp_precision = 0; |
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else if (dsp_precision > Maximum_DSP_PRECISION) |
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dsp_precision = Maximum_DSP_PRECISION; |
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xshift = 6 - dsp_precision; |
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vshift += xshift; |
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/* Move on to dsp_off */ |
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dsp_off = ((multiplier * (pll->fifo_size - 1)) << vshift) / divider - |
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(1 << (vshift - xshift)); |
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/* if (bpp == 0) |
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dsp_on = ((multiplier * 20 << vshift) + divider) / divider; |
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else */ |
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{ |
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dsp_on = ((multiplier << vshift) + divider) / divider; |
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tmp = ((ras_multiplier << xshift) + ras_divider) / ras_divider; |
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if (dsp_on < tmp) |
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dsp_on = tmp; |
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dsp_on = dsp_on + (tmp * 2) + (pll->xclkpagefaultdelay << xshift); |
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} |
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/* Calculate rounding factor and apply it to dsp_on */ |
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tmp = ((1 << (Maximum_DSP_PRECISION - dsp_precision)) - 1) >> 1; |
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dsp_on = ((dsp_on + tmp) / (tmp + 1)) * (tmp + 1); |
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if (dsp_on >= ((dsp_off / (tmp + 1)) * (tmp + 1))) { |
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dsp_on = dsp_off - (multiplier << vshift) / divider; |
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dsp_on = (dsp_on / (tmp + 1)) * (tmp + 1); |
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} |
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/* Last but not least: dsp_xclks */ |
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dsp_xclks = ((multiplier << (vshift + 5)) + divider) / divider; |
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/* Get register values. */ |
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pll->dsp_on_off = (dsp_on << 16) + dsp_off; |
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pll->dsp_config = (dsp_precision << 20) | (pll->dsp_loop_latency << 16) | dsp_xclks; |
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#ifdef DEBUG |
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printk("atyfb(%s): dsp_config 0x%08x, dsp_on_off 0x%08x\n", |
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__func__, pll->dsp_config, pll->dsp_on_off); |
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#endif |
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return 0; |
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} |
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static int aty_valid_pll_ct(const struct fb_info *info, u32 vclk_per, struct pll_ct *pll) |
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{ |
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u32 q; |
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struct atyfb_par *par = (struct atyfb_par *) info->par; |
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int pllvclk; |
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/* FIXME: use the VTB/GTB /{3,6,12} post dividers if they're better suited */ |
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q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per; |
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if (q < 16*8 || q > 255*8) { |
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printk(KERN_CRIT "atyfb: vclk out of range\n"); |
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return -EINVAL; |
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} else { |
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pll->vclk_post_div = (q < 128*8); |
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pll->vclk_post_div += (q < 64*8); |
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pll->vclk_post_div += (q < 32*8); |
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} |
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pll->vclk_post_div_real = aty_postdividers[pll->vclk_post_div]; |
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// pll->vclk_post_div <<= 6; |
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pll->vclk_fb_div = q * pll->vclk_post_div_real / 8; |
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pllvclk = (1000000 * 2 * pll->vclk_fb_div) / |
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(par->ref_clk_per * pll->pll_ref_div); |
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#ifdef DEBUG |
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printk("atyfb(%s): pllvclk=%d MHz, vclk=%d MHz\n", |
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__func__, pllvclk, pllvclk / pll->vclk_post_div_real); |
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#endif |
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pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */ |
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/* Set ECP (scaler/overlay clock) divider */ |
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if (par->pll_limits.ecp_max) { |
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int ecp = pllvclk / pll->vclk_post_div_real; |
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int ecp_div = 0; |
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while (ecp > par->pll_limits.ecp_max && ecp_div < 2) { |
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ecp >>= 1; |
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ecp_div++; |
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} |
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pll->pll_vclk_cntl |= ecp_div << 4; |
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} |
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return 0; |
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} |
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static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) |
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{ |
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struct atyfb_par *par = (struct atyfb_par *) info->par; |
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int err; |
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if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct))) |
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return err; |
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if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, &pll->ct))) |
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return err; |
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/*aty_calc_pll_ct(info, &pll->ct);*/ |
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return 0; |
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} |
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static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll) |
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{ |
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struct atyfb_par *par = (struct atyfb_par *) info->par; |
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u32 ret; |
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ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / 2; |
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#ifdef CONFIG_FB_ATY_GENERIC_LCD |
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if(pll->ct.xres > 0) { |
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ret *= par->lcd_width; |
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ret /= pll->ct.xres; |
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} |
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#endif |
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#ifdef DEBUG |
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printk("atyfb(%s): calculated 0x%08X(%i)\n", __func__, ret, ret); |
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#endif |
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return ret; |
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} |
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void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll) |
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{ |
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struct atyfb_par *par = (struct atyfb_par *) info->par; |
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u32 crtc_gen_cntl, lcd_gen_cntrl; |
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u8 tmp, tmp2; |
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lcd_gen_cntrl = 0; |
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#ifdef DEBUG |
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printk("atyfb(%s): about to program:\n" |
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"pll_ext_cntl=0x%02x pll_gen_cntl=0x%02x pll_vclk_cntl=0x%02x\n", |
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__func__, |
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pll->ct.pll_ext_cntl, pll->ct.pll_gen_cntl, pll->ct.pll_vclk_cntl); |
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printk("atyfb(%s): setting clock %lu for FeedBackDivider %i, ReferenceDivider %i, PostDivider %i(%i)\n", |
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__func__, |
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par->clk_wr_offset, pll->ct.vclk_fb_div, |
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pll->ct.pll_ref_div, pll->ct.vclk_post_div, pll->ct.vclk_post_div_real); |
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#endif |
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#ifdef CONFIG_FB_ATY_GENERIC_LCD |
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if (par->lcd_table != 0) { |
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/* turn off LCD */ |
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lcd_gen_cntrl = aty_ld_lcd(LCD_GEN_CNTL, par); |
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aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl & ~LCD_ON, par); |
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} |
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#endif |
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aty_st_8(CLOCK_CNTL, par->clk_wr_offset | CLOCK_STROBE, par); |
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/* Temporarily switch to accelerator mode */ |
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crtc_gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par); |
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if (!(crtc_gen_cntl & CRTC_EXT_DISP_EN)) |
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aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl | CRTC_EXT_DISP_EN, par); |
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/* Reset VCLK generator */ |
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aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par); |
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/* Set post-divider */ |
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tmp2 = par->clk_wr_offset << 1; |
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tmp = aty_ld_pll_ct(VCLK_POST_DIV, par); |
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tmp &= ~(0x03U << tmp2); |
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tmp |= ((pll->ct.vclk_post_div & 0x03U) << tmp2); |
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aty_st_pll_ct(VCLK_POST_DIV, tmp, par); |
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/* Set extended post-divider */ |
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tmp = aty_ld_pll_ct(PLL_EXT_CNTL, par); |
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tmp &= ~(0x10U << par->clk_wr_offset); |
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tmp &= 0xF0U; |
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tmp |= pll->ct.pll_ext_cntl; |
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aty_st_pll_ct(PLL_EXT_CNTL, tmp, par); |
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/* Set feedback divider */ |
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tmp = VCLK0_FB_DIV + par->clk_wr_offset; |
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aty_st_pll_ct(tmp, (pll->ct.vclk_fb_div & 0xFFU), par); |
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aty_st_pll_ct(PLL_GEN_CNTL, (pll->ct.pll_gen_cntl & (~(PLL_OVERRIDE | PLL_MCLK_RST))) | OSC_EN, par); |
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/* End VCLK generator reset */ |
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aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl & ~(PLL_VCLK_RST), par); |
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mdelay(5); |
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aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par); |
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aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par); |
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mdelay(1); |
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/* Restore mode register */ |
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if (!(crtc_gen_cntl & CRTC_EXT_DISP_EN)) |
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aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl, par); |
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if (M64_HAS(GTB_DSP)) { |
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u8 dll_cntl; |
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if (M64_HAS(XL_DLL)) |
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dll_cntl = 0x80; |
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else if (par->ram_type >= SDRAM) |
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dll_cntl = 0xa6; |
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else |
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dll_cntl = 0xa0; |
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aty_st_pll_ct(DLL_CNTL, dll_cntl, par); |
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aty_st_pll_ct(VFC_CNTL, 0x1b, par); |
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aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, par); |
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aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, par); |
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mdelay(10); |
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aty_st_pll_ct(DLL_CNTL, dll_cntl, par); |
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mdelay(10); |
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aty_st_pll_ct(DLL_CNTL, dll_cntl | 0x40, par); |
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mdelay(10); |
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aty_st_pll_ct(DLL_CNTL, dll_cntl & ~0x40, par); |
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} |
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#ifdef CONFIG_FB_ATY_GENERIC_LCD |
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if (par->lcd_table != 0) { |
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/* restore LCD */ |
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aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl, par); |
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} |
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#endif |
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} |
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static void aty_get_pll_ct(const struct fb_info *info, union aty_pll *pll) |
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{ |
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struct atyfb_par *par = (struct atyfb_par *) info->par; |
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u8 tmp, clock; |
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clock = aty_ld_8(CLOCK_CNTL, par) & 0x03U; |
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tmp = clock << 1; |
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pll->ct.vclk_post_div = (aty_ld_pll_ct(VCLK_POST_DIV, par) >> tmp) & 0x03U; |
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pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par) & 0x0FU; |
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pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU; |
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pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); |
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pll->ct.mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par); |
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pll->ct.pll_gen_cntl = aty_ld_pll_ct(PLL_GEN_CNTL, par); |
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pll->ct.pll_vclk_cntl = aty_ld_pll_ct(PLL_VCLK_CNTL, par); |
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if (M64_HAS(GTB_DSP)) { |
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pll->ct.dsp_config = aty_ld_le32(DSP_CONFIG, par); |
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pll->ct.dsp_on_off = aty_ld_le32(DSP_ON_OFF, par); |
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} |
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} |
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static int aty_init_pll_ct(const struct fb_info *info, union aty_pll *pll) |
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{ |
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struct atyfb_par *par = (struct atyfb_par *) info->par; |
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u8 mpost_div, xpost_div, sclk_post_div_real; |
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u32 q, memcntl, trp; |
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u32 dsp_config, dsp_on_off, vga_dsp_config, vga_dsp_on_off; |
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#ifdef DEBUG |
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int pllmclk, pllsclk; |
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#endif |
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pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par); |
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pll->ct.xclk_post_div = pll->ct.pll_ext_cntl & 0x07; |
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pll->ct.xclk_ref_div = 1; |
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switch (pll->ct.xclk_post_div) { |
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case 0: case 1: case 2: case 3: |
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break; |
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case 4: |
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pll->ct.xclk_ref_div = 3; |
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pll->ct.xclk_post_div = 0; |
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break; |
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default: |
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printk(KERN_CRIT "atyfb: Unsupported xclk source: %d.\n", pll->ct.xclk_post_div); |
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return -EINVAL; |
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} |
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pll->ct.mclk_fb_mult = 2; |
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if(pll->ct.pll_ext_cntl & PLL_MFB_TIMES_4_2B) { |
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pll->ct.mclk_fb_mult = 4; |
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pll->ct.xclk_post_div -= 1; |
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} |
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#ifdef DEBUG |
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printk("atyfb(%s): mclk_fb_mult=%d, xclk_post_div=%d\n", |
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__func__, pll->ct.mclk_fb_mult, pll->ct.xclk_post_div); |
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#endif |
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memcntl = aty_ld_le32(MEM_CNTL, par); |
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trp = (memcntl & 0x300) >> 8; |
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pll->ct.xclkpagefaultdelay = ((memcntl & 0xc00) >> 10) + ((memcntl & 0x1000) >> 12) + trp + 2; |
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pll->ct.xclkmaxrasdelay = ((memcntl & 0x70000) >> 16) + trp + 2; |
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|
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if (M64_HAS(FIFO_32)) { |
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pll->ct.fifo_size = 32; |
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} else { |
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pll->ct.fifo_size = 24; |
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pll->ct.xclkpagefaultdelay += 2; |
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pll->ct.xclkmaxrasdelay += 3; |
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} |
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switch (par->ram_type) { |
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case DRAM: |
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if (info->fix.smem_len<=ONE_MB) { |
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pll->ct.dsp_loop_latency = 10; |
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} else { |
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pll->ct.dsp_loop_latency = 8; |
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pll->ct.xclkpagefaultdelay += 2; |
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} |
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break; |
|
case EDO: |
|
case PSEUDO_EDO: |
|
if (info->fix.smem_len<=ONE_MB) { |
|
pll->ct.dsp_loop_latency = 9; |
|
} else { |
|
pll->ct.dsp_loop_latency = 8; |
|
pll->ct.xclkpagefaultdelay += 1; |
|
} |
|
break; |
|
case SDRAM: |
|
if (info->fix.smem_len<=ONE_MB) { |
|
pll->ct.dsp_loop_latency = 11; |
|
} else { |
|
pll->ct.dsp_loop_latency = 10; |
|
pll->ct.xclkpagefaultdelay += 1; |
|
} |
|
break; |
|
case SGRAM: |
|
pll->ct.dsp_loop_latency = 8; |
|
pll->ct.xclkpagefaultdelay += 3; |
|
break; |
|
default: |
|
pll->ct.dsp_loop_latency = 11; |
|
pll->ct.xclkpagefaultdelay += 3; |
|
break; |
|
} |
|
|
|
if (pll->ct.xclkmaxrasdelay <= pll->ct.xclkpagefaultdelay) |
|
pll->ct.xclkmaxrasdelay = pll->ct.xclkpagefaultdelay + 1; |
|
|
|
/* Allow BIOS to override */ |
|
dsp_config = aty_ld_le32(DSP_CONFIG, par); |
|
dsp_on_off = aty_ld_le32(DSP_ON_OFF, par); |
|
vga_dsp_config = aty_ld_le32(VGA_DSP_CONFIG, par); |
|
vga_dsp_on_off = aty_ld_le32(VGA_DSP_ON_OFF, par); |
|
|
|
if (dsp_config) |
|
pll->ct.dsp_loop_latency = (dsp_config & DSP_LOOP_LATENCY) >> 16; |
|
#if 0 |
|
FIXME: is it relevant for us? |
|
if ((!dsp_on_off && !M64_HAS(RESET_3D)) || |
|
((dsp_on_off == vga_dsp_on_off) && |
|
(!dsp_config || !((dsp_config ^ vga_dsp_config) & DSP_XCLKS_PER_QW)))) { |
|
vga_dsp_on_off &= VGA_DSP_OFF; |
|
vga_dsp_config &= VGA_DSP_XCLKS_PER_QW; |
|
if (ATIDivide(vga_dsp_on_off, vga_dsp_config, 5, 1) > 24) |
|
pll->ct.fifo_size = 32; |
|
else |
|
pll->ct.fifo_size = 24; |
|
} |
|
#endif |
|
/* Exit if the user does not want us to tamper with the clock |
|
rates of her chip. */ |
|
if (par->mclk_per == 0) { |
|
u8 mclk_fb_div, pll_ext_cntl; |
|
pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); |
|
pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par); |
|
pll->ct.xclk_post_div_real = aty_postdividers[pll_ext_cntl & 0x07]; |
|
mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par); |
|
if (pll_ext_cntl & PLL_MFB_TIMES_4_2B) |
|
mclk_fb_div <<= 1; |
|
pll->ct.mclk_fb_div = mclk_fb_div; |
|
return 0; |
|
} |
|
|
|
pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per; |
|
|
|
/* FIXME: use the VTB/GTB /3 post divider if it's better suited */ |
|
q = par->ref_clk_per * pll->ct.pll_ref_div * 8 / |
|
(pll->ct.mclk_fb_mult * par->xclk_per); |
|
|
|
if (q < 16*8 || q > 255*8) { |
|
printk(KERN_CRIT "atxfb: xclk out of range\n"); |
|
return -EINVAL; |
|
} else { |
|
xpost_div = (q < 128*8); |
|
xpost_div += (q < 64*8); |
|
xpost_div += (q < 32*8); |
|
} |
|
pll->ct.xclk_post_div_real = aty_postdividers[xpost_div]; |
|
pll->ct.mclk_fb_div = q * pll->ct.xclk_post_div_real / 8; |
|
|
|
#ifdef CONFIG_PPC |
|
if (machine_is(powermac)) { |
|
/* Override PLL_EXT_CNTL & 0x07. */ |
|
pll->ct.xclk_post_div = xpost_div; |
|
pll->ct.xclk_ref_div = 1; |
|
} |
|
#endif |
|
|
|
#ifdef DEBUG |
|
pllmclk = (1000000 * pll->ct.mclk_fb_mult * pll->ct.mclk_fb_div) / |
|
(par->ref_clk_per * pll->ct.pll_ref_div); |
|
printk("atyfb(%s): pllmclk=%d MHz, xclk=%d MHz\n", |
|
__func__, pllmclk, pllmclk / pll->ct.xclk_post_div_real); |
|
#endif |
|
|
|
if (M64_HAS(SDRAM_MAGIC_PLL) && (par->ram_type >= SDRAM)) |
|
pll->ct.pll_gen_cntl = OSC_EN; |
|
else |
|
pll->ct.pll_gen_cntl = OSC_EN | DLL_PWDN /* | FORCE_DCLK_TRI_STATE */; |
|
|
|
if (M64_HAS(MAGIC_POSTDIV)) |
|
pll->ct.pll_ext_cntl = 0; |
|
else |
|
pll->ct.pll_ext_cntl = xpost_div; |
|
|
|
if (pll->ct.mclk_fb_mult == 4) |
|
pll->ct.pll_ext_cntl |= PLL_MFB_TIMES_4_2B; |
|
|
|
if (par->mclk_per == par->xclk_per) { |
|
pll->ct.pll_gen_cntl |= (xpost_div << 4); /* mclk == xclk */ |
|
} else { |
|
/* |
|
* The chip clock is not equal to the memory clock. |
|
* Therefore we will use sclk to clock the chip. |
|
*/ |
|
pll->ct.pll_gen_cntl |= (6 << 4); /* mclk == sclk */ |
|
|
|
q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per; |
|
if (q < 16*8 || q > 255*8) { |
|
printk(KERN_CRIT "atyfb: mclk out of range\n"); |
|
return -EINVAL; |
|
} else { |
|
mpost_div = (q < 128*8); |
|
mpost_div += (q < 64*8); |
|
mpost_div += (q < 32*8); |
|
} |
|
sclk_post_div_real = aty_postdividers[mpost_div]; |
|
pll->ct.sclk_fb_div = q * sclk_post_div_real / 8; |
|
pll->ct.spll_cntl2 = mpost_div << 4; |
|
#ifdef DEBUG |
|
pllsclk = (1000000 * 2 * pll->ct.sclk_fb_div) / |
|
(par->ref_clk_per * pll->ct.pll_ref_div); |
|
printk("atyfb(%s): use sclk, pllsclk=%d MHz, sclk=mclk=%d MHz\n", |
|
__func__, pllsclk, pllsclk / sclk_post_div_real); |
|
#endif |
|
} |
|
|
|
/* Disable the extra precision pixel clock controls since we do not use them. */ |
|
pll->ct.ext_vpll_cntl = aty_ld_pll_ct(EXT_VPLL_CNTL, par); |
|
pll->ct.ext_vpll_cntl &= ~(EXT_VPLL_EN | EXT_VPLL_VGA_EN | EXT_VPLL_INSYNC); |
|
|
|
return 0; |
|
} |
|
|
|
static void aty_resume_pll_ct(const struct fb_info *info, |
|
union aty_pll *pll) |
|
{ |
|
struct atyfb_par *par = info->par; |
|
|
|
if (par->mclk_per != par->xclk_per) { |
|
/* |
|
* This disables the sclk, crashes the computer as reported: |
|
* aty_st_pll_ct(SPLL_CNTL2, 3, info); |
|
* |
|
* So it seems the sclk must be enabled before it is used; |
|
* so PLL_GEN_CNTL must be programmed *after* the sclk. |
|
*/ |
|
aty_st_pll_ct(SCLK_FB_DIV, pll->ct.sclk_fb_div, par); |
|
aty_st_pll_ct(SPLL_CNTL2, pll->ct.spll_cntl2, par); |
|
/* |
|
* SCLK has been started. Wait for the PLL to lock. 5 ms |
|
* should be enough according to mach64 programmer's guide. |
|
*/ |
|
mdelay(5); |
|
} |
|
|
|
aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par); |
|
aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par); |
|
aty_st_pll_ct(MCLK_FB_DIV, pll->ct.mclk_fb_div, par); |
|
aty_st_pll_ct(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, par); |
|
aty_st_pll_ct(EXT_VPLL_CNTL, pll->ct.ext_vpll_cntl, par); |
|
} |
|
|
|
static int dummy(void) |
|
{ |
|
return 0; |
|
} |
|
|
|
const struct aty_dac_ops aty_dac_ct = { |
|
.set_dac = (void *) dummy, |
|
}; |
|
|
|
const struct aty_pll_ops aty_pll_ct = { |
|
.var_to_pll = aty_var_to_pll_ct, |
|
.pll_to_var = aty_pll_to_var_ct, |
|
.set_pll = aty_set_pll_ct, |
|
.get_pll = aty_get_pll_ct, |
|
.init_pll = aty_init_pll_ct, |
|
.resume_pll = aty_resume_pll_ct, |
|
};
|
|
|