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768 lines
18 KiB
768 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Pin controller and GPIO driver for Amlogic Meson SoCs |
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* |
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* Copyright (C) 2014 Beniamino Galvani <[email protected]> |
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*/ |
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|
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/* |
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* The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO, |
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* BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and |
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* X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a |
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* variable number of pins. |
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* |
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* The AO bank is special because it belongs to the Always-On power |
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* domain which can't be powered off; the bank also uses a set of |
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* registers different from the other banks. |
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* |
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* For each pin controller there are 4 different register ranges that |
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* control the following properties of the pins: |
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* 1) pin muxing |
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* 2) pull enable/disable |
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* 3) pull up/down |
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* 4) GPIO direction, output value, input value |
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* |
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* In some cases the register ranges for pull enable and pull |
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* direction are the same and thus there are only 3 register ranges. |
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* |
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* Since Meson G12A SoC, the ao register ranges for gpio, pull enable |
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* and pull direction are the same, so there are only 2 register ranges. |
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* |
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* For the pull and GPIO configuration every bank uses a contiguous |
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* set of bits in the register sets described above; the same register |
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* can be shared by more banks with different offsets. |
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* |
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* In addition to this there are some registers shared between all |
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* banks that control the IRQ functionality. This feature is not |
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* supported at the moment by the driver. |
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*/ |
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|
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#include <linux/device.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/pinctrl/pinconf-generic.h> |
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#include <linux/pinctrl/pinconf.h> |
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#include <linux/pinctrl/pinctrl.h> |
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#include <linux/pinctrl/pinmux.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <linux/seq_file.h> |
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|
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#include "../core.h" |
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#include "../pinctrl-utils.h" |
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#include "pinctrl-meson.h" |
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|
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static const unsigned int meson_bit_strides[] = { |
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1, 1, 1, 1, 1, 2, 1 |
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}; |
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|
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/** |
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* meson_get_bank() - find the bank containing a given pin |
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* |
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* @pc: the pinctrl instance |
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* @pin: the pin number |
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* @bank: the found bank |
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* |
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* Return: 0 on success, a negative value on error |
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*/ |
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static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin, |
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struct meson_bank **bank) |
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{ |
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int i; |
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|
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for (i = 0; i < pc->data->num_banks; i++) { |
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if (pin >= pc->data->banks[i].first && |
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pin <= pc->data->banks[i].last) { |
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*bank = &pc->data->banks[i]; |
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return 0; |
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} |
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} |
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return -EINVAL; |
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} |
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/** |
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* meson_calc_reg_and_bit() - calculate register and bit for a pin |
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* |
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* @bank: the bank containing the pin |
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* @pin: the pin number |
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* @reg_type: the type of register needed (pull-enable, pull, etc...) |
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* @reg: the computed register offset |
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* @bit: the computed bit |
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*/ |
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static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin, |
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enum meson_reg_type reg_type, |
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unsigned int *reg, unsigned int *bit) |
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{ |
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struct meson_reg_desc *desc = &bank->regs[reg_type]; |
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*bit = (desc->bit + pin - bank->first) * meson_bit_strides[reg_type]; |
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*reg = (desc->reg + (*bit / 32)) * 4; |
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*bit &= 0x1f; |
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} |
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static int meson_get_groups_count(struct pinctrl_dev *pcdev) |
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{ |
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); |
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return pc->data->num_groups; |
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} |
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static const char *meson_get_group_name(struct pinctrl_dev *pcdev, |
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unsigned selector) |
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{ |
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); |
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return pc->data->groups[selector].name; |
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} |
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static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector, |
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const unsigned **pins, unsigned *num_pins) |
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{ |
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); |
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*pins = pc->data->groups[selector].pins; |
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*num_pins = pc->data->groups[selector].num_pins; |
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return 0; |
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} |
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static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, |
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unsigned offset) |
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{ |
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seq_printf(s, " %s", dev_name(pcdev->dev)); |
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} |
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static const struct pinctrl_ops meson_pctrl_ops = { |
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.get_groups_count = meson_get_groups_count, |
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.get_group_name = meson_get_group_name, |
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.get_group_pins = meson_get_group_pins, |
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.dt_node_to_map = pinconf_generic_dt_node_to_map_all, |
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.dt_free_map = pinctrl_utils_free_map, |
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.pin_dbg_show = meson_pin_dbg_show, |
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}; |
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int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev) |
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{ |
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); |
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return pc->data->num_funcs; |
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} |
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const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, |
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unsigned selector) |
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{ |
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); |
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return pc->data->funcs[selector].name; |
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} |
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int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, |
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const char * const **groups, |
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unsigned * const num_groups) |
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{ |
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); |
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*groups = pc->data->funcs[selector].groups; |
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*num_groups = pc->data->funcs[selector].num_groups; |
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return 0; |
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} |
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static int meson_pinconf_set_gpio_bit(struct meson_pinctrl *pc, |
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unsigned int pin, |
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unsigned int reg_type, |
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bool arg) |
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{ |
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struct meson_bank *bank; |
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unsigned int reg, bit; |
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int ret; |
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ret = meson_get_bank(pc, pin, &bank); |
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if (ret) |
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return ret; |
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meson_calc_reg_and_bit(bank, pin, reg_type, ®, &bit); |
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return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), |
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arg ? BIT(bit) : 0); |
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} |
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static int meson_pinconf_get_gpio_bit(struct meson_pinctrl *pc, |
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unsigned int pin, |
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unsigned int reg_type) |
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{ |
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struct meson_bank *bank; |
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unsigned int reg, bit, val; |
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int ret; |
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ret = meson_get_bank(pc, pin, &bank); |
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if (ret) |
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return ret; |
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meson_calc_reg_and_bit(bank, pin, reg_type, ®, &bit); |
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ret = regmap_read(pc->reg_gpio, reg, &val); |
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if (ret) |
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return ret; |
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return BIT(bit) & val ? 1 : 0; |
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} |
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static int meson_pinconf_set_output(struct meson_pinctrl *pc, |
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unsigned int pin, |
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bool out) |
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{ |
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return meson_pinconf_set_gpio_bit(pc, pin, REG_DIR, !out); |
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} |
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static int meson_pinconf_get_output(struct meson_pinctrl *pc, |
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unsigned int pin) |
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{ |
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int ret = meson_pinconf_get_gpio_bit(pc, pin, REG_DIR); |
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if (ret < 0) |
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return ret; |
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return !ret; |
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} |
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static int meson_pinconf_set_drive(struct meson_pinctrl *pc, |
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unsigned int pin, |
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bool high) |
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{ |
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return meson_pinconf_set_gpio_bit(pc, pin, REG_OUT, high); |
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} |
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static int meson_pinconf_get_drive(struct meson_pinctrl *pc, |
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unsigned int pin) |
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{ |
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return meson_pinconf_get_gpio_bit(pc, pin, REG_OUT); |
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} |
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static int meson_pinconf_set_output_drive(struct meson_pinctrl *pc, |
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unsigned int pin, |
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bool high) |
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{ |
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int ret; |
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ret = meson_pinconf_set_output(pc, pin, true); |
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if (ret) |
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return ret; |
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return meson_pinconf_set_drive(pc, pin, high); |
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} |
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static int meson_pinconf_disable_bias(struct meson_pinctrl *pc, |
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unsigned int pin) |
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{ |
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struct meson_bank *bank; |
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unsigned int reg, bit = 0; |
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int ret; |
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ret = meson_get_bank(pc, pin, &bank); |
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if (ret) |
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return ret; |
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meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); |
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ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), 0); |
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if (ret) |
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return ret; |
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return 0; |
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} |
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static int meson_pinconf_enable_bias(struct meson_pinctrl *pc, unsigned int pin, |
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bool pull_up) |
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{ |
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struct meson_bank *bank; |
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unsigned int reg, bit, val = 0; |
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int ret; |
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ret = meson_get_bank(pc, pin, &bank); |
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if (ret) |
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return ret; |
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meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); |
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if (pull_up) |
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val = BIT(bit); |
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ret = regmap_update_bits(pc->reg_pull, reg, BIT(bit), val); |
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if (ret) |
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return ret; |
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meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); |
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ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), BIT(bit)); |
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if (ret) |
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return ret; |
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return 0; |
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} |
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static int meson_pinconf_set_drive_strength(struct meson_pinctrl *pc, |
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unsigned int pin, |
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u16 drive_strength_ua) |
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{ |
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struct meson_bank *bank; |
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unsigned int reg, bit, ds_val; |
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int ret; |
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if (!pc->reg_ds) { |
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dev_err(pc->dev, "drive-strength not supported\n"); |
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return -ENOTSUPP; |
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} |
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ret = meson_get_bank(pc, pin, &bank); |
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if (ret) |
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return ret; |
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meson_calc_reg_and_bit(bank, pin, REG_DS, ®, &bit); |
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if (drive_strength_ua <= 500) { |
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ds_val = MESON_PINCONF_DRV_500UA; |
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} else if (drive_strength_ua <= 2500) { |
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ds_val = MESON_PINCONF_DRV_2500UA; |
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} else if (drive_strength_ua <= 3000) { |
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ds_val = MESON_PINCONF_DRV_3000UA; |
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} else if (drive_strength_ua <= 4000) { |
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ds_val = MESON_PINCONF_DRV_4000UA; |
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} else { |
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dev_warn_once(pc->dev, |
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"pin %u: invalid drive-strength : %d , default to 4mA\n", |
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pin, drive_strength_ua); |
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ds_val = MESON_PINCONF_DRV_4000UA; |
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} |
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ret = regmap_update_bits(pc->reg_ds, reg, 0x3 << bit, ds_val << bit); |
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if (ret) |
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return ret; |
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return 0; |
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} |
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static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, |
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unsigned long *configs, unsigned num_configs) |
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{ |
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); |
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enum pin_config_param param; |
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unsigned int arg = 0; |
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int i, ret; |
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for (i = 0; i < num_configs; i++) { |
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param = pinconf_to_config_param(configs[i]); |
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switch (param) { |
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case PIN_CONFIG_DRIVE_STRENGTH_UA: |
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case PIN_CONFIG_OUTPUT_ENABLE: |
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case PIN_CONFIG_OUTPUT: |
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arg = pinconf_to_config_argument(configs[i]); |
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break; |
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default: |
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break; |
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} |
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switch (param) { |
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case PIN_CONFIG_BIAS_DISABLE: |
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ret = meson_pinconf_disable_bias(pc, pin); |
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break; |
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case PIN_CONFIG_BIAS_PULL_UP: |
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ret = meson_pinconf_enable_bias(pc, pin, true); |
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break; |
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case PIN_CONFIG_BIAS_PULL_DOWN: |
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ret = meson_pinconf_enable_bias(pc, pin, false); |
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break; |
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case PIN_CONFIG_DRIVE_STRENGTH_UA: |
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ret = meson_pinconf_set_drive_strength(pc, pin, arg); |
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break; |
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case PIN_CONFIG_OUTPUT_ENABLE: |
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ret = meson_pinconf_set_output(pc, pin, arg); |
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break; |
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case PIN_CONFIG_OUTPUT: |
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ret = meson_pinconf_set_output_drive(pc, pin, arg); |
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break; |
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default: |
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ret = -ENOTSUPP; |
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} |
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if (ret) |
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return ret; |
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} |
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return 0; |
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} |
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static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) |
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{ |
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struct meson_bank *bank; |
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unsigned int reg, bit, val; |
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int ret, conf; |
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ret = meson_get_bank(pc, pin, &bank); |
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if (ret) |
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return ret; |
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meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); |
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ret = regmap_read(pc->reg_pullen, reg, &val); |
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if (ret) |
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return ret; |
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if (!(val & BIT(bit))) { |
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conf = PIN_CONFIG_BIAS_DISABLE; |
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} else { |
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meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); |
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ret = regmap_read(pc->reg_pull, reg, &val); |
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if (ret) |
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return ret; |
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if (val & BIT(bit)) |
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conf = PIN_CONFIG_BIAS_PULL_UP; |
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else |
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conf = PIN_CONFIG_BIAS_PULL_DOWN; |
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} |
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return conf; |
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} |
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static int meson_pinconf_get_drive_strength(struct meson_pinctrl *pc, |
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unsigned int pin, |
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u16 *drive_strength_ua) |
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{ |
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struct meson_bank *bank; |
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unsigned int reg, bit; |
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unsigned int val; |
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int ret; |
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if (!pc->reg_ds) |
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return -ENOTSUPP; |
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ret = meson_get_bank(pc, pin, &bank); |
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if (ret) |
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return ret; |
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meson_calc_reg_and_bit(bank, pin, REG_DS, ®, &bit); |
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ret = regmap_read(pc->reg_ds, reg, &val); |
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if (ret) |
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return ret; |
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switch ((val >> bit) & 0x3) { |
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case MESON_PINCONF_DRV_500UA: |
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*drive_strength_ua = 500; |
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break; |
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case MESON_PINCONF_DRV_2500UA: |
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*drive_strength_ua = 2500; |
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break; |
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case MESON_PINCONF_DRV_3000UA: |
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*drive_strength_ua = 3000; |
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break; |
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case MESON_PINCONF_DRV_4000UA: |
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*drive_strength_ua = 4000; |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, |
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unsigned long *config) |
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{ |
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); |
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enum pin_config_param param = pinconf_to_config_param(*config); |
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u16 arg; |
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int ret; |
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|
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switch (param) { |
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case PIN_CONFIG_BIAS_DISABLE: |
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case PIN_CONFIG_BIAS_PULL_DOWN: |
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case PIN_CONFIG_BIAS_PULL_UP: |
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if (meson_pinconf_get_pull(pc, pin) == param) |
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arg = 1; |
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else |
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return -EINVAL; |
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break; |
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case PIN_CONFIG_DRIVE_STRENGTH_UA: |
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ret = meson_pinconf_get_drive_strength(pc, pin, &arg); |
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if (ret) |
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return ret; |
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break; |
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case PIN_CONFIG_OUTPUT_ENABLE: |
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ret = meson_pinconf_get_output(pc, pin); |
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if (ret <= 0) |
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return -EINVAL; |
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arg = 1; |
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break; |
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case PIN_CONFIG_OUTPUT: |
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ret = meson_pinconf_get_output(pc, pin); |
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if (ret <= 0) |
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return -EINVAL; |
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|
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ret = meson_pinconf_get_drive(pc, pin); |
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if (ret < 0) |
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return -EINVAL; |
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arg = ret; |
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break; |
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|
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default: |
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return -ENOTSUPP; |
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} |
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*config = pinconf_to_config_packed(param, arg); |
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dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config); |
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|
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return 0; |
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} |
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|
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static int meson_pinconf_group_set(struct pinctrl_dev *pcdev, |
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unsigned int num_group, |
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unsigned long *configs, unsigned num_configs) |
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{ |
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); |
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struct meson_pmx_group *group = &pc->data->groups[num_group]; |
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int i; |
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dev_dbg(pc->dev, "set pinconf for group %s\n", group->name); |
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|
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for (i = 0; i < group->num_pins; i++) { |
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meson_pinconf_set(pcdev, group->pins[i], configs, |
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num_configs); |
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} |
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|
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return 0; |
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} |
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|
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static int meson_pinconf_group_get(struct pinctrl_dev *pcdev, |
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unsigned int group, unsigned long *config) |
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{ |
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return -ENOTSUPP; |
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} |
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static const struct pinconf_ops meson_pinconf_ops = { |
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.pin_config_get = meson_pinconf_get, |
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.pin_config_set = meson_pinconf_set, |
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.pin_config_group_get = meson_pinconf_group_get, |
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.pin_config_group_set = meson_pinconf_group_set, |
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.is_generic = true, |
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}; |
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|
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static int meson_gpio_get_direction(struct gpio_chip *chip, unsigned gpio) |
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{ |
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struct meson_pinctrl *pc = gpiochip_get_data(chip); |
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int ret; |
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|
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ret = meson_pinconf_get_output(pc, gpio); |
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if (ret < 0) |
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return ret; |
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|
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return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; |
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} |
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|
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static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) |
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{ |
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return meson_pinconf_set_output(gpiochip_get_data(chip), gpio, false); |
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} |
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|
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static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, |
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int value) |
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{ |
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return meson_pinconf_set_output_drive(gpiochip_get_data(chip), |
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gpio, value); |
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} |
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|
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static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) |
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{ |
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meson_pinconf_set_drive(gpiochip_get_data(chip), gpio, value); |
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} |
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|
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static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) |
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{ |
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struct meson_pinctrl *pc = gpiochip_get_data(chip); |
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unsigned int reg, bit, val; |
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struct meson_bank *bank; |
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int ret; |
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|
|
ret = meson_get_bank(pc, gpio, &bank); |
|
if (ret) |
|
return ret; |
|
|
|
meson_calc_reg_and_bit(bank, gpio, REG_IN, ®, &bit); |
|
regmap_read(pc->reg_gpio, reg, &val); |
|
|
|
return !!(val & BIT(bit)); |
|
} |
|
|
|
static int meson_gpiolib_register(struct meson_pinctrl *pc) |
|
{ |
|
int ret; |
|
|
|
pc->chip.label = pc->data->name; |
|
pc->chip.parent = pc->dev; |
|
pc->chip.request = gpiochip_generic_request; |
|
pc->chip.free = gpiochip_generic_free; |
|
pc->chip.set_config = gpiochip_generic_config; |
|
pc->chip.get_direction = meson_gpio_get_direction; |
|
pc->chip.direction_input = meson_gpio_direction_input; |
|
pc->chip.direction_output = meson_gpio_direction_output; |
|
pc->chip.get = meson_gpio_get; |
|
pc->chip.set = meson_gpio_set; |
|
pc->chip.base = -1; |
|
pc->chip.ngpio = pc->data->num_pins; |
|
pc->chip.can_sleep = false; |
|
pc->chip.of_node = pc->of_node; |
|
pc->chip.of_gpio_n_cells = 2; |
|
|
|
ret = gpiochip_add_data(&pc->chip, pc); |
|
if (ret) { |
|
dev_err(pc->dev, "can't add gpio chip %s\n", |
|
pc->data->name); |
|
return ret; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static struct regmap_config meson_regmap_config = { |
|
.reg_bits = 32, |
|
.val_bits = 32, |
|
.reg_stride = 4, |
|
}; |
|
|
|
static struct regmap *meson_map_resource(struct meson_pinctrl *pc, |
|
struct device_node *node, char *name) |
|
{ |
|
struct resource res; |
|
void __iomem *base; |
|
int i; |
|
|
|
i = of_property_match_string(node, "reg-names", name); |
|
if (of_address_to_resource(node, i, &res)) |
|
return NULL; |
|
|
|
base = devm_ioremap_resource(pc->dev, &res); |
|
if (IS_ERR(base)) |
|
return ERR_CAST(base); |
|
|
|
meson_regmap_config.max_register = resource_size(&res) - 4; |
|
meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL, |
|
"%pOFn-%s", node, |
|
name); |
|
if (!meson_regmap_config.name) |
|
return ERR_PTR(-ENOMEM); |
|
|
|
return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config); |
|
} |
|
|
|
static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, |
|
struct device_node *node) |
|
{ |
|
struct device_node *np, *gpio_np = NULL; |
|
|
|
for_each_child_of_node(node, np) { |
|
if (!of_find_property(np, "gpio-controller", NULL)) |
|
continue; |
|
if (gpio_np) { |
|
dev_err(pc->dev, "multiple gpio nodes\n"); |
|
of_node_put(np); |
|
return -EINVAL; |
|
} |
|
gpio_np = np; |
|
} |
|
|
|
if (!gpio_np) { |
|
dev_err(pc->dev, "no gpio node found\n"); |
|
return -EINVAL; |
|
} |
|
|
|
pc->of_node = gpio_np; |
|
|
|
pc->reg_mux = meson_map_resource(pc, gpio_np, "mux"); |
|
if (IS_ERR_OR_NULL(pc->reg_mux)) { |
|
dev_err(pc->dev, "mux registers not found\n"); |
|
return pc->reg_mux ? PTR_ERR(pc->reg_mux) : -ENOENT; |
|
} |
|
|
|
pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio"); |
|
if (IS_ERR_OR_NULL(pc->reg_gpio)) { |
|
dev_err(pc->dev, "gpio registers not found\n"); |
|
return pc->reg_gpio ? PTR_ERR(pc->reg_gpio) : -ENOENT; |
|
} |
|
|
|
pc->reg_pull = meson_map_resource(pc, gpio_np, "pull"); |
|
if (IS_ERR(pc->reg_pull)) |
|
pc->reg_pull = NULL; |
|
|
|
pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable"); |
|
if (IS_ERR(pc->reg_pullen)) |
|
pc->reg_pullen = NULL; |
|
|
|
pc->reg_ds = meson_map_resource(pc, gpio_np, "ds"); |
|
if (IS_ERR(pc->reg_ds)) { |
|
dev_dbg(pc->dev, "ds registers not found - skipping\n"); |
|
pc->reg_ds = NULL; |
|
} |
|
|
|
if (pc->data->parse_dt) |
|
return pc->data->parse_dt(pc); |
|
|
|
return 0; |
|
} |
|
|
|
int meson8_aobus_parse_dt_extra(struct meson_pinctrl *pc) |
|
{ |
|
if (!pc->reg_pull) |
|
return -EINVAL; |
|
|
|
pc->reg_pullen = pc->reg_pull; |
|
|
|
return 0; |
|
} |
|
|
|
int meson_a1_parse_dt_extra(struct meson_pinctrl *pc) |
|
{ |
|
pc->reg_pull = pc->reg_gpio; |
|
pc->reg_pullen = pc->reg_gpio; |
|
pc->reg_ds = pc->reg_gpio; |
|
|
|
return 0; |
|
} |
|
|
|
int meson_pinctrl_probe(struct platform_device *pdev) |
|
{ |
|
struct device *dev = &pdev->dev; |
|
struct meson_pinctrl *pc; |
|
int ret; |
|
|
|
pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL); |
|
if (!pc) |
|
return -ENOMEM; |
|
|
|
pc->dev = dev; |
|
pc->data = (struct meson_pinctrl_data *) of_device_get_match_data(dev); |
|
|
|
ret = meson_pinctrl_parse_dt(pc, dev->of_node); |
|
if (ret) |
|
return ret; |
|
|
|
pc->desc.name = "pinctrl-meson"; |
|
pc->desc.owner = THIS_MODULE; |
|
pc->desc.pctlops = &meson_pctrl_ops; |
|
pc->desc.pmxops = pc->data->pmx_ops; |
|
pc->desc.confops = &meson_pinconf_ops; |
|
pc->desc.pins = pc->data->pins; |
|
pc->desc.npins = pc->data->num_pins; |
|
|
|
pc->pcdev = devm_pinctrl_register(pc->dev, &pc->desc, pc); |
|
if (IS_ERR(pc->pcdev)) { |
|
dev_err(pc->dev, "can't register pinctrl device"); |
|
return PTR_ERR(pc->pcdev); |
|
} |
|
|
|
return meson_gpiolib_register(pc); |
|
}
|
|
|