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312 lines
8.0 KiB
312 lines
8.0 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* OWL SoC's Pinctrl definitions |
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* |
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* Copyright (c) 2014 Actions Semi Inc. |
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* Author: David Liu <[email protected]> |
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* |
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* Copyright (c) 2018 Linaro Ltd. |
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* Author: Manivannan Sadhasivam <[email protected]> |
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*/ |
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#ifndef __PINCTRL_OWL_H__ |
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#define __PINCTRL_OWL_H__ |
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#define OWL_PINCONF_SLEW_SLOW 0 |
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#define OWL_PINCONF_SLEW_FAST 1 |
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#define MUX_PG(group_name, reg, shift, width) \ |
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{ \ |
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.name = #group_name, \ |
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.pads = group_name##_pads, \ |
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.npads = ARRAY_SIZE(group_name##_pads), \ |
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.funcs = group_name##_funcs, \ |
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.nfuncs = ARRAY_SIZE(group_name##_funcs), \ |
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.mfpctl_reg = MFCTL##reg, \ |
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.mfpctl_shift = shift, \ |
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.mfpctl_width = width, \ |
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.drv_reg = -1, \ |
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.drv_shift = -1, \ |
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.drv_width = -1, \ |
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.sr_reg = -1, \ |
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.sr_shift = -1, \ |
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.sr_width = -1, \ |
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} |
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#define DRV_PG(group_name, reg, shift, width) \ |
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{ \ |
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.name = #group_name, \ |
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.pads = group_name##_pads, \ |
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.npads = ARRAY_SIZE(group_name##_pads), \ |
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.mfpctl_reg = -1, \ |
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.mfpctl_shift = -1, \ |
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.mfpctl_width = -1, \ |
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.drv_reg = PAD_DRV##reg, \ |
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.drv_shift = shift, \ |
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.drv_width = width, \ |
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.sr_reg = -1, \ |
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.sr_shift = -1, \ |
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.sr_width = -1, \ |
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} |
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#define SR_PG(group_name, reg, shift, width) \ |
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{ \ |
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.name = #group_name, \ |
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.pads = group_name##_pads, \ |
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.npads = ARRAY_SIZE(group_name##_pads), \ |
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.mfpctl_reg = -1, \ |
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.mfpctl_shift = -1, \ |
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.mfpctl_width = -1, \ |
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.drv_reg = -1, \ |
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.drv_shift = -1, \ |
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.drv_width = -1, \ |
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.sr_reg = PAD_SR##reg, \ |
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.sr_shift = shift, \ |
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.sr_width = width, \ |
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} |
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#define FUNCTION(fname) \ |
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{ \ |
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.name = #fname, \ |
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.groups = fname##_groups, \ |
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.ngroups = ARRAY_SIZE(fname##_groups), \ |
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} |
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/* PAD PULL UP/DOWN CONFIGURES */ |
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#define PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) \ |
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{ \ |
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.reg = PAD_PULLCTL##pull_reg, \ |
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.shift = pull_sft, \ |
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.width = pull_wdt, \ |
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} |
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#define PAD_PULLCTL_CONF(pad_name, pull_reg, pull_sft, pull_wdt) \ |
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struct owl_pullctl pad_name##_pullctl_conf \ |
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= PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) |
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#define ST_CONF(st_reg, st_sft, st_wdt) \ |
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{ \ |
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.reg = PAD_ST##st_reg, \ |
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.shift = st_sft, \ |
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.width = st_wdt, \ |
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} |
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#define PAD_ST_CONF(pad_name, st_reg, st_sft, st_wdt) \ |
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struct owl_st pad_name##_st_conf \ |
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= ST_CONF(st_reg, st_sft, st_wdt) |
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#define PAD_INFO(name) \ |
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{ \ |
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.pad = name, \ |
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.pullctl = NULL, \ |
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.st = NULL, \ |
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} |
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#define PAD_INFO_ST(name) \ |
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{ \ |
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.pad = name, \ |
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.pullctl = NULL, \ |
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.st = &name##_st_conf, \ |
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} |
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#define PAD_INFO_PULLCTL(name) \ |
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{ \ |
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.pad = name, \ |
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.pullctl = &name##_pullctl_conf, \ |
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.st = NULL, \ |
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} |
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#define PAD_INFO_PULLCTL_ST(name) \ |
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{ \ |
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.pad = name, \ |
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.pullctl = &name##_pullctl_conf, \ |
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.st = &name##_st_conf, \ |
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} |
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#define OWL_GPIO_PORT_A 0 |
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#define OWL_GPIO_PORT_B 1 |
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#define OWL_GPIO_PORT_C 2 |
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#define OWL_GPIO_PORT_D 3 |
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#define OWL_GPIO_PORT_E 4 |
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#define OWL_GPIO_PORT_F 5 |
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#define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat, _intc_ctl,\ |
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_intc_pd, _intc_msk, _intc_type, _share) \ |
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[OWL_GPIO_PORT_##port] = { \ |
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.offset = base, \ |
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.pins = count, \ |
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.outen = _outen, \ |
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.inen = _inen, \ |
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.dat = _dat, \ |
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.intc_ctl = _intc_ctl, \ |
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.intc_pd = _intc_pd, \ |
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.intc_msk = _intc_msk, \ |
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.intc_type = _intc_type, \ |
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.shared_ctl_offset = _share, \ |
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} |
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enum owl_pinconf_drv { |
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OWL_PINCONF_DRV_2MA, |
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OWL_PINCONF_DRV_4MA, |
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OWL_PINCONF_DRV_8MA, |
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OWL_PINCONF_DRV_12MA, |
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}; |
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/* GPIO CTRL Bit Definition */ |
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#define OWL_GPIO_CTLR_PENDING 0 |
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#define OWL_GPIO_CTLR_ENABLE 1 |
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#define OWL_GPIO_CTLR_SAMPLE_CLK_24M 2 |
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/* GPIO TYPE Bit Definition */ |
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#define OWL_GPIO_INT_LEVEL_HIGH 0 |
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#define OWL_GPIO_INT_LEVEL_LOW 1 |
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#define OWL_GPIO_INT_EDGE_RISING 2 |
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#define OWL_GPIO_INT_EDGE_FALLING 3 |
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#define OWL_GPIO_INT_MASK 3 |
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/** |
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* struct owl_pullctl - Actions pad pull control register |
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* @reg: offset to the pull control register |
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* @shift: shift value of the register |
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* @width: width of the register |
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*/ |
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struct owl_pullctl { |
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int reg; |
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unsigned int shift; |
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unsigned int width; |
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}; |
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/** |
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* struct owl_st - Actions pad schmitt trigger enable register |
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* @reg: offset to the schmitt trigger enable register |
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* @shift: shift value of the register |
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* @width: width of the register |
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*/ |
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struct owl_st { |
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int reg; |
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unsigned int shift; |
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unsigned int width; |
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}; |
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/** |
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* struct owl_pingroup - Actions pingroup definition |
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* @name: name of the pin group |
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* @pads: list of pins assigned to this pingroup |
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* @npads: size of @pads array |
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* @funcs: list of pinmux functions for this pingroup |
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* @nfuncs: size of @funcs array |
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* @mfpctl_reg: multiplexing control register offset |
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* @mfpctl_shift: multiplexing control register bit mask |
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* @mfpctl_width: multiplexing control register width |
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* @drv_reg: drive control register offset |
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* @drv_shift: drive control register bit mask |
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* @drv_width: driver control register width |
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* @sr_reg: slew rate control register offset |
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* @sr_shift: slew rate control register bit mask |
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* @sr_width: slew rate control register width |
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*/ |
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struct owl_pingroup { |
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const char *name; |
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unsigned int *pads; |
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unsigned int npads; |
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unsigned int *funcs; |
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unsigned int nfuncs; |
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int mfpctl_reg; |
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unsigned int mfpctl_shift; |
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unsigned int mfpctl_width; |
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int drv_reg; |
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unsigned int drv_shift; |
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unsigned int drv_width; |
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int sr_reg; |
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unsigned int sr_shift; |
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unsigned int sr_width; |
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}; |
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/** |
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* struct owl_padinfo - Actions pinctrl pad info |
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* @pad: pad name of the SoC |
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* @pullctl: pull control register info |
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* @st: schmitt trigger register info |
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*/ |
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struct owl_padinfo { |
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int pad; |
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struct owl_pullctl *pullctl; |
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struct owl_st *st; |
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}; |
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/** |
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* struct owl_pinmux_func - Actions pinctrl mux functions |
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* @name: name of the pinmux function. |
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* @groups: array of pin groups that may select this function. |
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* @ngroups: number of entries in @groups. |
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*/ |
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struct owl_pinmux_func { |
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const char *name; |
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const char * const *groups; |
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unsigned int ngroups; |
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}; |
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/** |
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* struct owl_gpio_port - Actions GPIO port info |
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* @offset: offset of the GPIO port. |
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* @pins: number of pins belongs to the GPIO port. |
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* @outen: offset of the output enable register. |
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* @inen: offset of the input enable register. |
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* @dat: offset of the data register. |
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* @intc_ctl: offset of the interrupt control register. |
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* @intc_pd: offset of the interrupt pending register. |
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* @intc_msk: offset of the interrupt mask register. |
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* @intc_type: offset of the interrupt type register. |
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*/ |
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struct owl_gpio_port { |
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unsigned int offset; |
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unsigned int pins; |
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unsigned int outen; |
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unsigned int inen; |
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unsigned int dat; |
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unsigned int intc_ctl; |
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unsigned int intc_pd; |
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unsigned int intc_msk; |
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unsigned int intc_type; |
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u8 shared_ctl_offset; |
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}; |
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/** |
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* struct owl_pinctrl_soc_data - Actions pin controller driver configuration |
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* @pins: array describing all pins of the pin controller. |
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* @npins: number of entries in @pins. |
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* @functions: array describing all mux functions of this SoC. |
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* @nfunction: number of entries in @functions. |
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* @groups: array describing all pin groups of this SoC. |
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* @ngroups: number of entries in @groups. |
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* @padinfo: array describing the pad info of this SoC. |
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* @ngpios: number of pingroups the driver should expose as GPIOs. |
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* @ports: array describing all GPIO ports of this SoC. |
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* @nports: number of GPIO ports in this SoC. |
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*/ |
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struct owl_pinctrl_soc_data { |
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const struct pinctrl_pin_desc *pins; |
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unsigned int npins; |
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const struct owl_pinmux_func *functions; |
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unsigned int nfunctions; |
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const struct owl_pingroup *groups; |
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unsigned int ngroups; |
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const struct owl_padinfo *padinfo; |
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unsigned int ngpios; |
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const struct owl_gpio_port *ports; |
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unsigned int nports; |
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int (*padctl_val2arg)(const struct owl_padinfo *padinfo, |
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unsigned int param, |
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u32 *arg); |
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int (*padctl_arg2val)(const struct owl_padinfo *info, |
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unsigned int param, |
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u32 *arg); |
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}; |
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int owl_pinctrl_probe(struct platform_device *pdev, |
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struct owl_pinctrl_soc_data *soc_data); |
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#endif /* __PINCTRL_OWL_H__ */
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