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949 lines
24 KiB
949 lines
24 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* phy-ti-pipe3 - PIPE3 PHY driver. |
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* |
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com |
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* Author: Kishon Vijay Abraham I <[email protected]> |
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*/ |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/phy/phy.h> |
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#include <linux/of.h> |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/delay.h> |
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#include <linux/phy/omap_control_phy.h> |
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#include <linux/of_platform.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/regmap.h> |
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#define PLL_STATUS 0x00000004 |
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#define PLL_GO 0x00000008 |
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#define PLL_CONFIGURATION1 0x0000000C |
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#define PLL_CONFIGURATION2 0x00000010 |
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#define PLL_CONFIGURATION3 0x00000014 |
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#define PLL_CONFIGURATION4 0x00000020 |
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#define PLL_REGM_MASK 0x001FFE00 |
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#define PLL_REGM_SHIFT 0x9 |
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#define PLL_REGM_F_MASK 0x0003FFFF |
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#define PLL_REGM_F_SHIFT 0x0 |
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#define PLL_REGN_MASK 0x000001FE |
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#define PLL_REGN_SHIFT 0x1 |
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#define PLL_SELFREQDCO_MASK 0x0000000E |
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#define PLL_SELFREQDCO_SHIFT 0x1 |
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#define PLL_SD_MASK 0x0003FC00 |
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#define PLL_SD_SHIFT 10 |
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#define SET_PLL_GO 0x1 |
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#define PLL_LDOPWDN BIT(15) |
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#define PLL_TICOPWDN BIT(16) |
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#define PLL_LOCK 0x2 |
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#define PLL_IDLE 0x1 |
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#define SATA_PLL_SOFT_RESET BIT(18) |
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#define PIPE3_PHY_PWRCTL_CLK_CMD_MASK GENMASK(21, 14) |
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#define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14 |
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#define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK GENMASK(31, 22) |
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#define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22 |
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#define PIPE3_PHY_RX_POWERON (0x1 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT) |
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#define PIPE3_PHY_TX_POWERON (0x2 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT) |
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#define PCIE_PCS_MASK 0xFF0000 |
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#define PCIE_PCS_DELAY_COUNT_SHIFT 0x10 |
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#define PIPE3_PHY_RX_ANA_PROGRAMMABILITY 0x0000000C |
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#define INTERFACE_MASK GENMASK(31, 27) |
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#define INTERFACE_SHIFT 27 |
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#define INTERFACE_MODE_USBSS BIT(4) |
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#define INTERFACE_MODE_SATA_1P5 BIT(3) |
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#define INTERFACE_MODE_SATA_3P0 BIT(2) |
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#define INTERFACE_MODE_PCIE BIT(0) |
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#define LOSD_MASK GENMASK(17, 14) |
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#define LOSD_SHIFT 14 |
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#define MEM_PLLDIV GENMASK(6, 5) |
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#define PIPE3_PHY_RX_TRIM 0x0000001C |
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#define MEM_DLL_TRIM_SEL_MASK GENMASK(31, 30) |
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#define MEM_DLL_TRIM_SHIFT 30 |
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#define PIPE3_PHY_RX_DLL 0x00000024 |
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#define MEM_DLL_PHINT_RATE_MASK GENMASK(31, 30) |
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#define MEM_DLL_PHINT_RATE_SHIFT 30 |
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#define PIPE3_PHY_RX_DIGITAL_MODES 0x00000028 |
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#define MEM_HS_RATE_MASK GENMASK(28, 27) |
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#define MEM_HS_RATE_SHIFT 27 |
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#define MEM_OVRD_HS_RATE BIT(26) |
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#define MEM_OVRD_HS_RATE_SHIFT 26 |
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#define MEM_CDR_FASTLOCK BIT(23) |
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#define MEM_CDR_FASTLOCK_SHIFT 23 |
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#define MEM_CDR_LBW_MASK GENMASK(22, 21) |
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#define MEM_CDR_LBW_SHIFT 21 |
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#define MEM_CDR_STEPCNT_MASK GENMASK(20, 19) |
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#define MEM_CDR_STEPCNT_SHIFT 19 |
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#define MEM_CDR_STL_MASK GENMASK(18, 16) |
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#define MEM_CDR_STL_SHIFT 16 |
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#define MEM_CDR_THR_MASK GENMASK(15, 13) |
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#define MEM_CDR_THR_SHIFT 13 |
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#define MEM_CDR_THR_MODE BIT(12) |
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#define MEM_CDR_THR_MODE_SHIFT 12 |
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#define MEM_CDR_2NDO_SDM_MODE BIT(11) |
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#define MEM_CDR_2NDO_SDM_MODE_SHIFT 11 |
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#define PIPE3_PHY_RX_EQUALIZER 0x00000038 |
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#define MEM_EQLEV_MASK GENMASK(31, 16) |
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#define MEM_EQLEV_SHIFT 16 |
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#define MEM_EQFTC_MASK GENMASK(15, 11) |
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#define MEM_EQFTC_SHIFT 11 |
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#define MEM_EQCTL_MASK GENMASK(10, 7) |
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#define MEM_EQCTL_SHIFT 7 |
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#define MEM_OVRD_EQLEV BIT(2) |
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#define MEM_OVRD_EQLEV_SHIFT 2 |
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#define MEM_OVRD_EQFTC BIT(1) |
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#define MEM_OVRD_EQFTC_SHIFT 1 |
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#define SATA_PHY_RX_IO_AND_A2D_OVERRIDES 0x44 |
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#define MEM_CDR_LOS_SOURCE_MASK GENMASK(10, 9) |
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#define MEM_CDR_LOS_SOURCE_SHIFT 9 |
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/* |
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* This is an Empirical value that works, need to confirm the actual |
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* value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status |
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* to be correctly reflected in the PIPE3PHY_PLL_STATUS register. |
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*/ |
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#define PLL_IDLE_TIME 100 /* in milliseconds */ |
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#define PLL_LOCK_TIME 100 /* in milliseconds */ |
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enum pipe3_mode { PIPE3_MODE_PCIE = 1, |
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PIPE3_MODE_SATA, |
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PIPE3_MODE_USBSS }; |
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struct pipe3_dpll_params { |
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u16 m; |
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u8 n; |
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u8 freq:3; |
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u8 sd; |
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u32 mf; |
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}; |
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struct pipe3_dpll_map { |
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unsigned long rate; |
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struct pipe3_dpll_params params; |
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}; |
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struct pipe3_settings { |
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u8 ana_interface; |
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u8 ana_losd; |
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u8 dig_fastlock; |
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u8 dig_lbw; |
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u8 dig_stepcnt; |
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u8 dig_stl; |
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u8 dig_thr; |
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u8 dig_thr_mode; |
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u8 dig_2ndo_sdm_mode; |
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u8 dig_hs_rate; |
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u8 dig_ovrd_hs_rate; |
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u8 dll_trim_sel; |
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u8 dll_phint_rate; |
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u8 eq_lev; |
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u8 eq_ftc; |
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u8 eq_ctl; |
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u8 eq_ovrd_lev; |
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u8 eq_ovrd_ftc; |
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}; |
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struct ti_pipe3 { |
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void __iomem *pll_ctrl_base; |
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void __iomem *phy_rx; |
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void __iomem *phy_tx; |
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struct device *dev; |
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struct device *control_dev; |
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struct clk *wkupclk; |
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struct clk *sys_clk; |
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struct clk *refclk; |
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struct clk *div_clk; |
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struct pipe3_dpll_map *dpll_map; |
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struct regmap *phy_power_syscon; /* ctrl. reg. acces */ |
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struct regmap *pcs_syscon; /* ctrl. reg. acces */ |
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struct regmap *dpll_reset_syscon; /* ctrl. reg. acces */ |
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unsigned int dpll_reset_reg; /* reg. index within syscon */ |
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unsigned int power_reg; /* power reg. index within syscon */ |
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unsigned int pcie_pcs_reg; /* pcs reg. index in syscon */ |
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bool sata_refclk_enabled; |
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enum pipe3_mode mode; |
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struct pipe3_settings settings; |
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}; |
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static struct pipe3_dpll_map dpll_map_usb[] = { |
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{12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */ |
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{16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */ |
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{19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */ |
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{20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */ |
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{26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */ |
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{38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */ |
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{ }, /* Terminator */ |
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}; |
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static struct pipe3_dpll_map dpll_map_sata[] = { |
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{12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */ |
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{16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */ |
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{19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */ |
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{20000000, {750, 9, 4, 6, 0} }, /* 20 MHz */ |
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{26000000, {750, 12, 4, 6, 0} }, /* 26 MHz */ |
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{38400000, {625, 15, 4, 6, 0} }, /* 38.4 MHz */ |
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{ }, /* Terminator */ |
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}; |
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struct pipe3_data { |
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enum pipe3_mode mode; |
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struct pipe3_dpll_map *dpll_map; |
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struct pipe3_settings settings; |
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}; |
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static struct pipe3_data data_usb = { |
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.mode = PIPE3_MODE_USBSS, |
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.dpll_map = dpll_map_usb, |
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.settings = { |
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/* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */ |
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.ana_interface = INTERFACE_MODE_USBSS, |
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.ana_losd = 0xa, |
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.dig_fastlock = 1, |
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.dig_lbw = 3, |
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.dig_stepcnt = 0, |
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.dig_stl = 0x3, |
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.dig_thr = 1, |
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.dig_thr_mode = 1, |
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.dig_2ndo_sdm_mode = 0, |
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.dig_hs_rate = 0, |
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.dig_ovrd_hs_rate = 1, |
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.dll_trim_sel = 0x2, |
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.dll_phint_rate = 0x3, |
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.eq_lev = 0, |
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.eq_ftc = 0, |
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.eq_ctl = 0x9, |
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.eq_ovrd_lev = 0, |
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.eq_ovrd_ftc = 0, |
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}, |
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}; |
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static struct pipe3_data data_sata = { |
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.mode = PIPE3_MODE_SATA, |
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.dpll_map = dpll_map_sata, |
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.settings = { |
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/* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */ |
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.ana_interface = INTERFACE_MODE_SATA_3P0, |
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.ana_losd = 0x5, |
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.dig_fastlock = 1, |
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.dig_lbw = 3, |
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.dig_stepcnt = 0, |
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.dig_stl = 0x3, |
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.dig_thr = 1, |
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.dig_thr_mode = 1, |
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.dig_2ndo_sdm_mode = 0, |
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.dig_hs_rate = 0, /* Not in TRM preferred settings */ |
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.dig_ovrd_hs_rate = 0, /* Not in TRM preferred settings */ |
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.dll_trim_sel = 0x1, |
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.dll_phint_rate = 0x2, /* for 1.5 GHz DPLL clock */ |
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.eq_lev = 0, |
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.eq_ftc = 0x1f, |
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.eq_ctl = 0, |
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.eq_ovrd_lev = 1, |
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.eq_ovrd_ftc = 1, |
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}, |
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}; |
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static struct pipe3_data data_pcie = { |
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.mode = PIPE3_MODE_PCIE, |
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.settings = { |
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/* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */ |
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.ana_interface = INTERFACE_MODE_PCIE, |
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.ana_losd = 0xa, |
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.dig_fastlock = 1, |
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.dig_lbw = 3, |
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.dig_stepcnt = 0, |
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.dig_stl = 0x3, |
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.dig_thr = 1, |
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.dig_thr_mode = 1, |
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.dig_2ndo_sdm_mode = 0, |
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.dig_hs_rate = 0, |
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.dig_ovrd_hs_rate = 0, |
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.dll_trim_sel = 0x2, |
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.dll_phint_rate = 0x3, |
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.eq_lev = 0, |
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.eq_ftc = 0x1f, |
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.eq_ctl = 1, |
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.eq_ovrd_lev = 0, |
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.eq_ovrd_ftc = 0, |
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}, |
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}; |
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static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset) |
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{ |
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return __raw_readl(addr + offset); |
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} |
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static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset, |
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u32 data) |
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{ |
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__raw_writel(data, addr + offset); |
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} |
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static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy) |
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{ |
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unsigned long rate; |
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struct pipe3_dpll_map *dpll_map = phy->dpll_map; |
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rate = clk_get_rate(phy->sys_clk); |
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for (; dpll_map->rate; dpll_map++) { |
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if (rate == dpll_map->rate) |
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return &dpll_map->params; |
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} |
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dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate); |
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return NULL; |
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} |
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static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy); |
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static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy); |
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static int ti_pipe3_power_off(struct phy *x) |
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{ |
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int ret; |
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struct ti_pipe3 *phy = phy_get_drvdata(x); |
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if (!phy->phy_power_syscon) { |
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omap_control_phy_power(phy->control_dev, 0); |
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return 0; |
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} |
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ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg, |
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PIPE3_PHY_PWRCTL_CLK_CMD_MASK, 0); |
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return ret; |
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} |
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static void ti_pipe3_calibrate(struct ti_pipe3 *phy); |
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static int ti_pipe3_power_on(struct phy *x) |
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{ |
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u32 val; |
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u32 mask; |
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unsigned long rate; |
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struct ti_pipe3 *phy = phy_get_drvdata(x); |
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bool rx_pending = false; |
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if (!phy->phy_power_syscon) { |
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omap_control_phy_power(phy->control_dev, 1); |
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return 0; |
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} |
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rate = clk_get_rate(phy->sys_clk); |
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if (!rate) { |
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dev_err(phy->dev, "Invalid clock rate\n"); |
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return -EINVAL; |
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} |
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rate = rate / 1000000; |
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mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK; |
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val = rate << OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT; |
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regmap_update_bits(phy->phy_power_syscon, phy->power_reg, |
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mask, val); |
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/* |
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* For PCIe, TX and RX must be powered on simultaneously. |
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* For USB and SATA, TX must be powered on before RX |
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*/ |
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mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK; |
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if (phy->mode == PIPE3_MODE_SATA || phy->mode == PIPE3_MODE_USBSS) { |
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val = PIPE3_PHY_TX_POWERON; |
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rx_pending = true; |
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} else { |
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val = PIPE3_PHY_TX_POWERON | PIPE3_PHY_RX_POWERON; |
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} |
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regmap_update_bits(phy->phy_power_syscon, phy->power_reg, |
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mask, val); |
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if (rx_pending) { |
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val = PIPE3_PHY_TX_POWERON | PIPE3_PHY_RX_POWERON; |
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regmap_update_bits(phy->phy_power_syscon, phy->power_reg, |
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mask, val); |
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} |
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if (phy->mode == PIPE3_MODE_PCIE) |
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ti_pipe3_calibrate(phy); |
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return 0; |
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} |
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static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy) |
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{ |
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u32 val; |
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unsigned long timeout; |
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timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME); |
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do { |
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cpu_relax(); |
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val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); |
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if (val & PLL_LOCK) |
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return 0; |
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} while (!time_after(jiffies, timeout)); |
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dev_err(phy->dev, "DPLL failed to lock\n"); |
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return -EBUSY; |
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} |
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static int ti_pipe3_dpll_program(struct ti_pipe3 *phy) |
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{ |
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u32 val; |
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struct pipe3_dpll_params *dpll_params; |
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dpll_params = ti_pipe3_get_dpll_params(phy); |
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if (!dpll_params) |
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return -EINVAL; |
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val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); |
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val &= ~PLL_REGN_MASK; |
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val |= dpll_params->n << PLL_REGN_SHIFT; |
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ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); |
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val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); |
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val &= ~PLL_SELFREQDCO_MASK; |
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val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; |
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ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); |
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val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); |
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val &= ~PLL_REGM_MASK; |
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val |= dpll_params->m << PLL_REGM_SHIFT; |
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ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); |
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val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4); |
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val &= ~PLL_REGM_F_MASK; |
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val |= dpll_params->mf << PLL_REGM_F_SHIFT; |
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ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val); |
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val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3); |
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val &= ~PLL_SD_MASK; |
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val |= dpll_params->sd << PLL_SD_SHIFT; |
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ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val); |
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ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO); |
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return ti_pipe3_dpll_wait_lock(phy); |
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} |
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static void ti_pipe3_calibrate(struct ti_pipe3 *phy) |
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{ |
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u32 val; |
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struct pipe3_settings *s = &phy->settings; |
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val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY); |
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val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV); |
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val |= (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT); |
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ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val); |
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val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES); |
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val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK | |
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MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK | |
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MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE); |
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val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT | |
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s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT | |
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s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT | |
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s->dig_lbw << MEM_CDR_LBW_SHIFT | |
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s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT | |
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s->dig_stl << MEM_CDR_STL_SHIFT | |
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s->dig_thr << MEM_CDR_THR_SHIFT | |
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s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT | |
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s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT; |
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ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val); |
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|
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val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM); |
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val &= ~MEM_DLL_TRIM_SEL_MASK; |
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val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT; |
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ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val); |
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|
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val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL); |
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val &= ~MEM_DLL_PHINT_RATE_MASK; |
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val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT; |
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ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val); |
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|
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val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER); |
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val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK | |
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MEM_OVRD_EQLEV | MEM_OVRD_EQFTC); |
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val |= s->eq_lev << MEM_EQLEV_SHIFT | |
|
s->eq_ftc << MEM_EQFTC_SHIFT | |
|
s->eq_ctl << MEM_EQCTL_SHIFT | |
|
s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT | |
|
s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT; |
|
ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val); |
|
|
|
if (phy->mode == PIPE3_MODE_SATA) { |
|
val = ti_pipe3_readl(phy->phy_rx, |
|
SATA_PHY_RX_IO_AND_A2D_OVERRIDES); |
|
val &= ~MEM_CDR_LOS_SOURCE_MASK; |
|
ti_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES, |
|
val); |
|
} |
|
} |
|
|
|
static int ti_pipe3_init(struct phy *x) |
|
{ |
|
struct ti_pipe3 *phy = phy_get_drvdata(x); |
|
u32 val; |
|
int ret = 0; |
|
|
|
ti_pipe3_enable_clocks(phy); |
|
/* |
|
* Set pcie_pcs register to 0x96 for proper functioning of phy |
|
* as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table |
|
* 18-1804. |
|
*/ |
|
if (phy->mode == PIPE3_MODE_PCIE) { |
|
if (!phy->pcs_syscon) { |
|
omap_control_pcie_pcs(phy->control_dev, 0x96); |
|
return 0; |
|
} |
|
|
|
val = 0x96 << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT; |
|
ret = regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg, |
|
PCIE_PCS_MASK, val); |
|
return ret; |
|
} |
|
|
|
/* Bring it out of IDLE if it is IDLE */ |
|
val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); |
|
if (val & PLL_IDLE) { |
|
val &= ~PLL_IDLE; |
|
ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); |
|
ret = ti_pipe3_dpll_wait_lock(phy); |
|
} |
|
|
|
/* SATA has issues if re-programmed when locked */ |
|
val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); |
|
if ((val & PLL_LOCK) && phy->mode == PIPE3_MODE_SATA) |
|
return ret; |
|
|
|
/* Program the DPLL */ |
|
ret = ti_pipe3_dpll_program(phy); |
|
if (ret) { |
|
ti_pipe3_disable_clocks(phy); |
|
return -EINVAL; |
|
} |
|
|
|
ti_pipe3_calibrate(phy); |
|
|
|
return ret; |
|
} |
|
|
|
static int ti_pipe3_exit(struct phy *x) |
|
{ |
|
struct ti_pipe3 *phy = phy_get_drvdata(x); |
|
u32 val; |
|
unsigned long timeout; |
|
|
|
/* If dpll_reset_syscon is not present we wont power down SATA DPLL |
|
* due to Errata i783 |
|
*/ |
|
if (phy->mode == PIPE3_MODE_SATA && !phy->dpll_reset_syscon) |
|
return 0; |
|
|
|
/* PCIe doesn't have internal DPLL */ |
|
if (phy->mode != PIPE3_MODE_PCIE) { |
|
/* Put DPLL in IDLE mode */ |
|
val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); |
|
val |= PLL_IDLE; |
|
ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); |
|
|
|
/* wait for LDO and Oscillator to power down */ |
|
timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME); |
|
do { |
|
cpu_relax(); |
|
val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); |
|
if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN)) |
|
break; |
|
} while (!time_after(jiffies, timeout)); |
|
|
|
if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) { |
|
dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n", |
|
val); |
|
return -EBUSY; |
|
} |
|
} |
|
|
|
/* i783: SATA needs control bit toggle after PLL unlock */ |
|
if (phy->mode == PIPE3_MODE_SATA) { |
|
regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg, |
|
SATA_PLL_SOFT_RESET, SATA_PLL_SOFT_RESET); |
|
regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg, |
|
SATA_PLL_SOFT_RESET, 0); |
|
} |
|
|
|
ti_pipe3_disable_clocks(phy); |
|
|
|
return 0; |
|
} |
|
static const struct phy_ops ops = { |
|
.init = ti_pipe3_init, |
|
.exit = ti_pipe3_exit, |
|
.power_on = ti_pipe3_power_on, |
|
.power_off = ti_pipe3_power_off, |
|
.owner = THIS_MODULE, |
|
}; |
|
|
|
static const struct of_device_id ti_pipe3_id_table[]; |
|
|
|
static int ti_pipe3_get_clk(struct ti_pipe3 *phy) |
|
{ |
|
struct clk *clk; |
|
struct device *dev = phy->dev; |
|
|
|
phy->refclk = devm_clk_get(dev, "refclk"); |
|
if (IS_ERR(phy->refclk)) { |
|
dev_err(dev, "unable to get refclk\n"); |
|
/* older DTBs have missing refclk in SATA PHY |
|
* so don't bail out in case of SATA PHY. |
|
*/ |
|
if (phy->mode != PIPE3_MODE_SATA) |
|
return PTR_ERR(phy->refclk); |
|
} |
|
|
|
if (phy->mode != PIPE3_MODE_SATA) { |
|
phy->wkupclk = devm_clk_get(dev, "wkupclk"); |
|
if (IS_ERR(phy->wkupclk)) { |
|
dev_err(dev, "unable to get wkupclk\n"); |
|
return PTR_ERR(phy->wkupclk); |
|
} |
|
} else { |
|
phy->wkupclk = ERR_PTR(-ENODEV); |
|
} |
|
|
|
if (phy->mode != PIPE3_MODE_PCIE || phy->phy_power_syscon) { |
|
phy->sys_clk = devm_clk_get(dev, "sysclk"); |
|
if (IS_ERR(phy->sys_clk)) { |
|
dev_err(dev, "unable to get sysclk\n"); |
|
return -EINVAL; |
|
} |
|
} |
|
|
|
if (phy->mode == PIPE3_MODE_PCIE) { |
|
clk = devm_clk_get(dev, "dpll_ref"); |
|
if (IS_ERR(clk)) { |
|
dev_err(dev, "unable to get dpll ref clk\n"); |
|
return PTR_ERR(clk); |
|
} |
|
clk_set_rate(clk, 1500000000); |
|
|
|
clk = devm_clk_get(dev, "dpll_ref_m2"); |
|
if (IS_ERR(clk)) { |
|
dev_err(dev, "unable to get dpll ref m2 clk\n"); |
|
return PTR_ERR(clk); |
|
} |
|
clk_set_rate(clk, 100000000); |
|
|
|
clk = devm_clk_get(dev, "phy-div"); |
|
if (IS_ERR(clk)) { |
|
dev_err(dev, "unable to get phy-div clk\n"); |
|
return PTR_ERR(clk); |
|
} |
|
clk_set_rate(clk, 100000000); |
|
|
|
phy->div_clk = devm_clk_get(dev, "div-clk"); |
|
if (IS_ERR(phy->div_clk)) { |
|
dev_err(dev, "unable to get div-clk\n"); |
|
return PTR_ERR(phy->div_clk); |
|
} |
|
} else { |
|
phy->div_clk = ERR_PTR(-ENODEV); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy) |
|
{ |
|
struct device *dev = phy->dev; |
|
struct device_node *node = dev->of_node; |
|
struct device_node *control_node; |
|
struct platform_device *control_pdev; |
|
|
|
phy->phy_power_syscon = syscon_regmap_lookup_by_phandle(node, |
|
"syscon-phy-power"); |
|
if (IS_ERR(phy->phy_power_syscon)) { |
|
dev_dbg(dev, |
|
"can't get syscon-phy-power, using control device\n"); |
|
phy->phy_power_syscon = NULL; |
|
} else { |
|
if (of_property_read_u32_index(node, |
|
"syscon-phy-power", 1, |
|
&phy->power_reg)) { |
|
dev_err(dev, "couldn't get power reg. offset\n"); |
|
return -EINVAL; |
|
} |
|
} |
|
|
|
if (!phy->phy_power_syscon) { |
|
control_node = of_parse_phandle(node, "ctrl-module", 0); |
|
if (!control_node) { |
|
dev_err(dev, "Failed to get control device phandle\n"); |
|
return -EINVAL; |
|
} |
|
|
|
control_pdev = of_find_device_by_node(control_node); |
|
if (!control_pdev) { |
|
dev_err(dev, "Failed to get control device\n"); |
|
return -EINVAL; |
|
} |
|
|
|
phy->control_dev = &control_pdev->dev; |
|
} |
|
|
|
if (phy->mode == PIPE3_MODE_PCIE) { |
|
phy->pcs_syscon = syscon_regmap_lookup_by_phandle(node, |
|
"syscon-pcs"); |
|
if (IS_ERR(phy->pcs_syscon)) { |
|
dev_dbg(dev, |
|
"can't get syscon-pcs, using omap control\n"); |
|
phy->pcs_syscon = NULL; |
|
} else { |
|
if (of_property_read_u32_index(node, |
|
"syscon-pcs", 1, |
|
&phy->pcie_pcs_reg)) { |
|
dev_err(dev, |
|
"couldn't get pcie pcs reg. offset\n"); |
|
return -EINVAL; |
|
} |
|
} |
|
} |
|
|
|
if (phy->mode == PIPE3_MODE_SATA) { |
|
phy->dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node, |
|
"syscon-pllreset"); |
|
if (IS_ERR(phy->dpll_reset_syscon)) { |
|
dev_info(dev, |
|
"can't get syscon-pllreset, sata dpll won't idle\n"); |
|
phy->dpll_reset_syscon = NULL; |
|
} else { |
|
if (of_property_read_u32_index(node, |
|
"syscon-pllreset", 1, |
|
&phy->dpll_reset_reg)) { |
|
dev_err(dev, |
|
"couldn't get pllreset reg. offset\n"); |
|
return -EINVAL; |
|
} |
|
} |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int ti_pipe3_get_tx_rx_base(struct ti_pipe3 *phy) |
|
{ |
|
struct resource *res; |
|
struct device *dev = phy->dev; |
|
struct platform_device *pdev = to_platform_device(dev); |
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
|
"phy_rx"); |
|
phy->phy_rx = devm_ioremap_resource(dev, res); |
|
if (IS_ERR(phy->phy_rx)) |
|
return PTR_ERR(phy->phy_rx); |
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
|
"phy_tx"); |
|
phy->phy_tx = devm_ioremap_resource(dev, res); |
|
|
|
return PTR_ERR_OR_ZERO(phy->phy_tx); |
|
} |
|
|
|
static int ti_pipe3_get_pll_base(struct ti_pipe3 *phy) |
|
{ |
|
struct resource *res; |
|
struct device *dev = phy->dev; |
|
struct platform_device *pdev = to_platform_device(dev); |
|
|
|
if (phy->mode == PIPE3_MODE_PCIE) |
|
return 0; |
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
|
"pll_ctrl"); |
|
phy->pll_ctrl_base = devm_ioremap_resource(dev, res); |
|
return PTR_ERR_OR_ZERO(phy->pll_ctrl_base); |
|
} |
|
|
|
static int ti_pipe3_probe(struct platform_device *pdev) |
|
{ |
|
struct ti_pipe3 *phy; |
|
struct phy *generic_phy; |
|
struct phy_provider *phy_provider; |
|
struct device *dev = &pdev->dev; |
|
int ret; |
|
const struct of_device_id *match; |
|
struct pipe3_data *data; |
|
|
|
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); |
|
if (!phy) |
|
return -ENOMEM; |
|
|
|
match = of_match_device(ti_pipe3_id_table, dev); |
|
if (!match) |
|
return -EINVAL; |
|
|
|
data = (struct pipe3_data *)match->data; |
|
if (!data) { |
|
dev_err(dev, "no driver data\n"); |
|
return -EINVAL; |
|
} |
|
|
|
phy->dev = dev; |
|
phy->mode = data->mode; |
|
phy->dpll_map = data->dpll_map; |
|
phy->settings = data->settings; |
|
|
|
ret = ti_pipe3_get_pll_base(phy); |
|
if (ret) |
|
return ret; |
|
|
|
ret = ti_pipe3_get_tx_rx_base(phy); |
|
if (ret) |
|
return ret; |
|
|
|
ret = ti_pipe3_get_sysctrl(phy); |
|
if (ret) |
|
return ret; |
|
|
|
ret = ti_pipe3_get_clk(phy); |
|
if (ret) |
|
return ret; |
|
|
|
platform_set_drvdata(pdev, phy); |
|
pm_runtime_enable(dev); |
|
|
|
/* |
|
* Prevent auto-disable of refclk for SATA PHY due to Errata i783 |
|
*/ |
|
if (phy->mode == PIPE3_MODE_SATA) { |
|
if (!IS_ERR(phy->refclk)) { |
|
clk_prepare_enable(phy->refclk); |
|
phy->sata_refclk_enabled = true; |
|
} |
|
} |
|
|
|
generic_phy = devm_phy_create(dev, NULL, &ops); |
|
if (IS_ERR(generic_phy)) |
|
return PTR_ERR(generic_phy); |
|
|
|
phy_set_drvdata(generic_phy, phy); |
|
|
|
ti_pipe3_power_off(generic_phy); |
|
|
|
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
|
return PTR_ERR_OR_ZERO(phy_provider); |
|
} |
|
|
|
static int ti_pipe3_remove(struct platform_device *pdev) |
|
{ |
|
struct ti_pipe3 *phy = platform_get_drvdata(pdev); |
|
|
|
if (phy->mode == PIPE3_MODE_SATA) { |
|
clk_disable_unprepare(phy->refclk); |
|
phy->sata_refclk_enabled = false; |
|
} |
|
pm_runtime_disable(&pdev->dev); |
|
|
|
return 0; |
|
} |
|
|
|
static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy) |
|
{ |
|
int ret = 0; |
|
|
|
if (!IS_ERR(phy->refclk)) { |
|
ret = clk_prepare_enable(phy->refclk); |
|
if (ret) { |
|
dev_err(phy->dev, "Failed to enable refclk %d\n", ret); |
|
return ret; |
|
} |
|
} |
|
|
|
if (!IS_ERR(phy->wkupclk)) { |
|
ret = clk_prepare_enable(phy->wkupclk); |
|
if (ret) { |
|
dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret); |
|
goto disable_refclk; |
|
} |
|
} |
|
|
|
if (!IS_ERR(phy->div_clk)) { |
|
ret = clk_prepare_enable(phy->div_clk); |
|
if (ret) { |
|
dev_err(phy->dev, "Failed to enable div_clk %d\n", ret); |
|
goto disable_wkupclk; |
|
} |
|
} |
|
|
|
return 0; |
|
|
|
disable_wkupclk: |
|
if (!IS_ERR(phy->wkupclk)) |
|
clk_disable_unprepare(phy->wkupclk); |
|
|
|
disable_refclk: |
|
if (!IS_ERR(phy->refclk)) |
|
clk_disable_unprepare(phy->refclk); |
|
|
|
return ret; |
|
} |
|
|
|
static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy) |
|
{ |
|
if (!IS_ERR(phy->wkupclk)) |
|
clk_disable_unprepare(phy->wkupclk); |
|
if (!IS_ERR(phy->refclk)) |
|
clk_disable_unprepare(phy->refclk); |
|
if (!IS_ERR(phy->div_clk)) |
|
clk_disable_unprepare(phy->div_clk); |
|
} |
|
|
|
static const struct of_device_id ti_pipe3_id_table[] = { |
|
{ |
|
.compatible = "ti,phy-usb3", |
|
.data = &data_usb, |
|
}, |
|
{ |
|
.compatible = "ti,omap-usb3", |
|
.data = &data_usb, |
|
}, |
|
{ |
|
.compatible = "ti,phy-pipe3-sata", |
|
.data = &data_sata, |
|
}, |
|
{ |
|
.compatible = "ti,phy-pipe3-pcie", |
|
.data = &data_pcie, |
|
}, |
|
{} |
|
}; |
|
MODULE_DEVICE_TABLE(of, ti_pipe3_id_table); |
|
|
|
static struct platform_driver ti_pipe3_driver = { |
|
.probe = ti_pipe3_probe, |
|
.remove = ti_pipe3_remove, |
|
.driver = { |
|
.name = "ti-pipe3", |
|
.of_match_table = ti_pipe3_id_table, |
|
}, |
|
}; |
|
|
|
module_platform_driver(ti_pipe3_driver); |
|
|
|
MODULE_ALIAS("platform:ti_pipe3"); |
|
MODULE_AUTHOR("Texas Instruments Inc."); |
|
MODULE_DESCRIPTION("TI PIPE3 phy driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|