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120 lines
3.0 KiB
120 lines
3.0 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* P2U (PIPE to UPHY) driver for Tegra T194 SoC |
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* |
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* Copyright (C) 2019 NVIDIA Corporation. |
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* |
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* Author: Vidya Sagar <[email protected]> |
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*/ |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_platform.h> |
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#include <linux/phy/phy.h> |
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#define P2U_PERIODIC_EQ_CTRL_GEN3 0xc0 |
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#define P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN BIT(0) |
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#define P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN BIT(1) |
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#define P2U_PERIODIC_EQ_CTRL_GEN4 0xc4 |
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#define P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN BIT(1) |
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#define P2U_RX_DEBOUNCE_TIME 0xa4 |
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#define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK 0xffff |
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#define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL 160 |
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struct tegra_p2u { |
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void __iomem *base; |
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}; |
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static inline void p2u_writel(struct tegra_p2u *phy, const u32 value, |
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const u32 reg) |
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{ |
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writel_relaxed(value, phy->base + reg); |
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} |
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static inline u32 p2u_readl(struct tegra_p2u *phy, const u32 reg) |
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{ |
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return readl_relaxed(phy->base + reg); |
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} |
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static int tegra_p2u_power_on(struct phy *x) |
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{ |
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struct tegra_p2u *phy = phy_get_drvdata(x); |
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u32 val; |
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val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN3); |
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val &= ~P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN; |
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val |= P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN; |
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p2u_writel(phy, val, P2U_PERIODIC_EQ_CTRL_GEN3); |
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val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN4); |
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val |= P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN; |
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p2u_writel(phy, val, P2U_PERIODIC_EQ_CTRL_GEN4); |
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val = p2u_readl(phy, P2U_RX_DEBOUNCE_TIME); |
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val &= ~P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK; |
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val |= P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL; |
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p2u_writel(phy, val, P2U_RX_DEBOUNCE_TIME); |
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return 0; |
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} |
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static const struct phy_ops ops = { |
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.power_on = tegra_p2u_power_on, |
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.owner = THIS_MODULE, |
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}; |
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static int tegra_p2u_probe(struct platform_device *pdev) |
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{ |
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struct phy_provider *phy_provider; |
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struct device *dev = &pdev->dev; |
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struct phy *generic_phy; |
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struct tegra_p2u *phy; |
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struct resource *res; |
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); |
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if (!phy) |
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return -ENOMEM; |
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctl"); |
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phy->base = devm_ioremap_resource(dev, res); |
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if (IS_ERR(phy->base)) |
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return PTR_ERR(phy->base); |
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platform_set_drvdata(pdev, phy); |
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generic_phy = devm_phy_create(dev, NULL, &ops); |
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if (IS_ERR(generic_phy)) |
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return PTR_ERR(generic_phy); |
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phy_set_drvdata(generic_phy, phy); |
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
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if (IS_ERR(phy_provider)) |
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return PTR_ERR(phy_provider); |
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return 0; |
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} |
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static const struct of_device_id tegra_p2u_id_table[] = { |
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{ |
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.compatible = "nvidia,tegra194-p2u", |
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}, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(of, tegra_p2u_id_table); |
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static struct platform_driver tegra_p2u_driver = { |
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.probe = tegra_p2u_probe, |
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.driver = { |
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.name = "tegra194-p2u", |
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.of_match_table = tegra_p2u_id_table, |
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}, |
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}; |
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module_platform_driver(tegra_p2u_driver); |
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MODULE_AUTHOR("Vidya Sagar <[email protected]>"); |
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MODULE_DESCRIPTION("NVIDIA Tegra194 PIPE2UPHY PHY driver"); |
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MODULE_LICENSE("GPL v2");
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