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56 lines
1.5 KiB
56 lines
1.5 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright (c) 2018 MediaTek Inc. |
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* Author: Chunhui Dai <[email protected]> |
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*/ |
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#ifndef _MTK_HDMI_PHY_H |
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#define _MTK_HDMI_PHY_H |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/types.h> |
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struct mtk_hdmi_phy; |
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struct mtk_hdmi_phy_conf { |
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unsigned long flags; |
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bool pll_default_off; |
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const struct clk_ops *hdmi_phy_clk_ops; |
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void (*hdmi_phy_enable_tmds)(struct mtk_hdmi_phy *hdmi_phy); |
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void (*hdmi_phy_disable_tmds)(struct mtk_hdmi_phy *hdmi_phy); |
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}; |
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struct mtk_hdmi_phy { |
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void __iomem *regs; |
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struct device *dev; |
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struct mtk_hdmi_phy_conf *conf; |
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struct clk *pll; |
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struct clk_hw pll_hw; |
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unsigned long pll_rate; |
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unsigned char drv_imp_clk; |
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unsigned char drv_imp_d2; |
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unsigned char drv_imp_d1; |
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unsigned char drv_imp_d0; |
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unsigned int ibias; |
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unsigned int ibias_up; |
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}; |
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void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, |
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u32 bits); |
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void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, |
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u32 bits); |
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void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset, |
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u32 val, u32 mask); |
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struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw); |
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extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf; |
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extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf; |
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#endif /* _MTK_HDMI_PHY_H */
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