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484 lines
18 KiB
484 lines
18 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. |
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* Copyright (C) 2018-2020 Linaro Ltd. |
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*/ |
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#ifndef _IPA_REG_H_ |
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#define _IPA_REG_H_ |
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#include <linux/bitfield.h> |
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#include "ipa_version.h" |
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struct ipa; |
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/** |
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* DOC: IPA Registers |
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* |
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* IPA registers are located within the "ipa-reg" address space defined by |
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* Device Tree. The offset of each register within that space is specified |
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* by symbols defined below. The address space is mapped to virtual memory |
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* space in ipa_mem_init(). All IPA registers are 32 bits wide. |
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* |
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* Certain register types are duplicated for a number of instances of |
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* something. For example, each IPA endpoint has an set of registers |
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* defining its configuration. The offset to an endpoint's set of registers |
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* is computed based on an "base" offset, plus an endpoint's ID multiplied |
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* and a "stride" value for the register. For such registers, the offset is |
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* computed by a function-like macro that takes a parameter used in the |
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* computation. |
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* |
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* Some register offsets depend on execution environment. For these an "ee" |
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* parameter is supplied to the offset macro. The "ee" value is a member of |
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* the gsi_ee enumerated type. |
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* |
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* The offset of a register dependent on endpoint ID is computed by a macro |
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* that is supplied a parameter "ep", "txep", or "rxep". A register with an |
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* "ep" parameter is valid for any endpoint; a register with a "txep" or |
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* "rxep" parameter is valid only for TX or RX endpoints, respectively. The |
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* "*ep" value is assumed to be less than the maximum valid endpoint ID |
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* for the current hardware, and that will not exceed IPA_ENDPOINT_MAX. |
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* |
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* The offset of registers related to filter and route tables is computed |
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* by a macro that is supplied a parameter "er". The "er" represents an |
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* endpoint ID for filters, or a route ID for routes. For filters, the |
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* endpoint ID must be less than IPA_ENDPOINT_MAX, but is further restricted |
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* because not all endpoints support filtering. For routes, the route ID |
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* must be less than IPA_ROUTE_MAX. |
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* |
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* The offset of registers related to resource types is computed by a macro |
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* that is supplied a parameter "rt". The "rt" represents a resource type, |
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* which is is a member of the ipa_resource_type_src enumerated type for |
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* source endpoint resources or the ipa_resource_type_dst enumerated type |
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* for destination endpoint resources. |
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* |
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* Some registers encode multiple fields within them. For these, each field |
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* has a symbol below defining a field mask that encodes both the position |
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* and width of the field within its register. |
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* |
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* In some cases, different versions of IPA hardware use different offset or |
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* field mask values. In such cases an inline_function(ipa) is used rather |
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* than a MACRO to define the offset or field mask to use. |
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* |
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* Finally, some registers hold bitmasks representing endpoints. In such |
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* cases the @available field in the @ipa structure defines the "full" set |
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* of valid bits for the register. |
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*/ |
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#define IPA_REG_ENABLED_PIPES_OFFSET 0x00000038 |
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#define IPA_REG_COMP_CFG_OFFSET 0x0000003c |
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#define ENABLE_FMASK GENMASK(0, 0) |
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#define GSI_SNOC_BYPASS_DIS_FMASK GENMASK(1, 1) |
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#define GEN_QMB_0_SNOC_BYPASS_DIS_FMASK GENMASK(2, 2) |
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#define GEN_QMB_1_SNOC_BYPASS_DIS_FMASK GENMASK(3, 3) |
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#define IPA_DCMP_FAST_CLK_EN_FMASK GENMASK(4, 4) |
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#define IPA_QMB_SELECT_CONS_EN_FMASK GENMASK(5, 5) |
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#define IPA_QMB_SELECT_PROD_EN_FMASK GENMASK(6, 6) |
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#define GSI_MULTI_INORDER_RD_DIS_FMASK GENMASK(7, 7) |
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#define GSI_MULTI_INORDER_WR_DIS_FMASK GENMASK(8, 8) |
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#define GEN_QMB_0_MULTI_INORDER_RD_DIS_FMASK GENMASK(9, 9) |
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#define GEN_QMB_1_MULTI_INORDER_RD_DIS_FMASK GENMASK(10, 10) |
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#define GEN_QMB_0_MULTI_INORDER_WR_DIS_FMASK GENMASK(11, 11) |
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#define GEN_QMB_1_MULTI_INORDER_WR_DIS_FMASK GENMASK(12, 12) |
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#define GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS_FMASK GENMASK(13, 13) |
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#define GSI_SNOC_CNOC_LOOP_PROT_DISABLE_FMASK GENMASK(14, 14) |
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#define GSI_MULTI_AXI_MASTERS_DIS_FMASK GENMASK(15, 15) |
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#define IPA_QMB_SELECT_GLOBAL_EN_FMASK GENMASK(16, 16) |
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#define IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_FMASK GENMASK(20, 17) |
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#define IPA_REG_CLKON_CFG_OFFSET 0x00000044 |
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#define RX_FMASK GENMASK(0, 0) |
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#define PROC_FMASK GENMASK(1, 1) |
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#define TX_WRAPPER_FMASK GENMASK(2, 2) |
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#define MISC_FMASK GENMASK(3, 3) |
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#define RAM_ARB_FMASK GENMASK(4, 4) |
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#define FTCH_HPS_FMASK GENMASK(5, 5) |
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#define FTCH_DPS_FMASK GENMASK(6, 6) |
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#define HPS_FMASK GENMASK(7, 7) |
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#define DPS_FMASK GENMASK(8, 8) |
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#define RX_HPS_CMDQS_FMASK GENMASK(9, 9) |
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#define HPS_DPS_CMDQS_FMASK GENMASK(10, 10) |
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#define DPS_TX_CMDQS_FMASK GENMASK(11, 11) |
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#define RSRC_MNGR_FMASK GENMASK(12, 12) |
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#define CTX_HANDLER_FMASK GENMASK(13, 13) |
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#define ACK_MNGR_FMASK GENMASK(14, 14) |
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#define D_DCPH_FMASK GENMASK(15, 15) |
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#define H_DCPH_FMASK GENMASK(16, 16) |
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#define DCMP_FMASK GENMASK(17, 17) |
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#define NTF_TX_CMDQS_FMASK GENMASK(18, 18) |
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#define TX_0_FMASK GENMASK(19, 19) |
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#define TX_1_FMASK GENMASK(20, 20) |
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#define FNR_FMASK GENMASK(21, 21) |
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#define QSB2AXI_CMDQ_L_FMASK GENMASK(22, 22) |
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#define AGGR_WRAPPER_FMASK GENMASK(23, 23) |
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#define RAM_SLAVEWAY_FMASK GENMASK(24, 24) |
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#define QMB_FMASK GENMASK(25, 25) |
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#define WEIGHT_ARB_FMASK GENMASK(26, 26) |
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#define GSI_IF_FMASK GENMASK(27, 27) |
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#define GLOBAL_FMASK GENMASK(28, 28) |
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#define GLOBAL_2X_CLK_FMASK GENMASK(29, 29) |
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#define IPA_REG_ROUTE_OFFSET 0x00000048 |
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#define ROUTE_DIS_FMASK GENMASK(0, 0) |
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#define ROUTE_DEF_PIPE_FMASK GENMASK(5, 1) |
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#define ROUTE_DEF_HDR_TABLE_FMASK GENMASK(6, 6) |
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#define ROUTE_DEF_HDR_OFST_FMASK GENMASK(16, 7) |
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#define ROUTE_FRAG_DEF_PIPE_FMASK GENMASK(21, 17) |
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#define ROUTE_DEF_RETAIN_HDR_FMASK GENMASK(24, 24) |
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#define IPA_REG_SHARED_MEM_SIZE_OFFSET 0x00000054 |
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#define SHARED_MEM_SIZE_FMASK GENMASK(15, 0) |
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#define SHARED_MEM_BADDR_FMASK GENMASK(31, 16) |
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#define IPA_REG_QSB_MAX_WRITES_OFFSET 0x00000074 |
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#define GEN_QMB_0_MAX_WRITES_FMASK GENMASK(3, 0) |
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#define GEN_QMB_1_MAX_WRITES_FMASK GENMASK(7, 4) |
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#define IPA_REG_QSB_MAX_READS_OFFSET 0x00000078 |
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#define GEN_QMB_0_MAX_READS_FMASK GENMASK(3, 0) |
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#define GEN_QMB_1_MAX_READS_FMASK GENMASK(7, 4) |
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/* The next two fields are present for IPA v4.0 and above */ |
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#define GEN_QMB_0_MAX_READS_BEATS_FMASK GENMASK(23, 16) |
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#define GEN_QMB_1_MAX_READS_BEATS_FMASK GENMASK(31, 24) |
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static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version) |
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{ |
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if (version == IPA_VERSION_3_5_1) |
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return 0x0000010c; |
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return 0x000000b4; |
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} |
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/* ipa->available defines the valid bits in the STATE_AGGR_ACTIVE register */ |
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/* The next register is present for IPA v4.2 and above */ |
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#define IPA_REG_FILT_ROUT_HASH_EN_OFFSET 0x00000148 |
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#define IPV6_ROUTER_HASH_EN GENMASK(0, 0) |
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#define IPV6_FILTER_HASH_EN GENMASK(4, 4) |
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#define IPV4_ROUTER_HASH_EN GENMASK(8, 8) |
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#define IPV4_FILTER_HASH_EN GENMASK(12, 12) |
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static inline u32 ipa_reg_filt_rout_hash_flush_offset(enum ipa_version version) |
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{ |
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if (version == IPA_VERSION_3_5_1) |
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return 0x0000090; |
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return 0x000014c; |
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} |
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#define IPV6_ROUTER_HASH_FLUSH GENMASK(0, 0) |
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#define IPV6_FILTER_HASH_FLUSH GENMASK(4, 4) |
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#define IPV4_ROUTER_HASH_FLUSH GENMASK(8, 8) |
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#define IPV4_FILTER_HASH_FLUSH GENMASK(12, 12) |
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#define IPA_REG_BCR_OFFSET 0x000001d0 |
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#define BCR_CMDQ_L_LACK_ONE_ENTRY BIT(0) |
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#define BCR_TX_NOT_USING_BRESP BIT(1) |
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#define BCR_SUSPEND_L2_IRQ BIT(3) |
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#define BCR_HOLB_DROP_L2_IRQ BIT(4) |
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#define BCR_DUAL_TX BIT(5) |
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/* Backward compatibility register value to use for each version */ |
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static inline u32 ipa_reg_bcr_val(enum ipa_version version) |
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{ |
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if (version == IPA_VERSION_3_5_1) |
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return BCR_CMDQ_L_LACK_ONE_ENTRY | BCR_TX_NOT_USING_BRESP | |
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BCR_SUSPEND_L2_IRQ | BCR_HOLB_DROP_L2_IRQ | BCR_DUAL_TX; |
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if (version == IPA_VERSION_4_0 || version == IPA_VERSION_4_1) |
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return BCR_CMDQ_L_LACK_ONE_ENTRY | BCR_SUSPEND_L2_IRQ | |
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BCR_HOLB_DROP_L2_IRQ | BCR_DUAL_TX; |
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return 0x00000000; |
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} |
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#define IPA_REG_LOCAL_PKT_PROC_CNTXT_BASE_OFFSET 0x000001e8 |
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#define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec |
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/* ipa->available defines the valid bits in the AGGR_FORCE_CLOSE register */ |
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/* The internal inactivity timer clock is used for the aggregation timer */ |
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#define TIMER_FREQUENCY 32000 /* 32 KHz inactivity timer clock */ |
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#define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0 |
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#define AGGR_GRANULARITY GENMASK(8, 4) |
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/* Compute the value to use in the AGGR_GRANULARITY field representing the |
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* given number of microseconds. The value is one less than the number of |
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* timer ticks in the requested period. Zero not a valid granularity value. |
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*/ |
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static inline u32 ipa_aggr_granularity_val(u32 usec) |
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{ |
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return DIV_ROUND_CLOSEST(usec * TIMER_FREQUENCY, USEC_PER_SEC) - 1; |
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} |
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#define IPA_REG_TX_CFG_OFFSET 0x000001fc |
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/* The first three fields are present for IPA v3.5.1 only */ |
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#define TX0_PREFETCH_DISABLE GENMASK(0, 0) |
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#define TX1_PREFETCH_DISABLE GENMASK(1, 1) |
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#define PREFETCH_ALMOST_EMPTY_SIZE GENMASK(4, 2) |
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/* The next fields are present for IPA v4.0 and above */ |
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#define PREFETCH_ALMOST_EMPTY_SIZE_TX0 GENMASK(5, 2) |
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#define DMAW_SCND_OUTSD_PRED_THRESHOLD GENMASK(9, 6) |
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#define DMAW_SCND_OUTSD_PRED_EN GENMASK(10, 10) |
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#define DMAW_MAX_BEATS_256_DIS GENMASK(11, 11) |
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#define PA_MASK_EN GENMASK(12, 12) |
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#define PREFETCH_ALMOST_EMPTY_SIZE_TX1 GENMASK(16, 13) |
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/* The last two fields are present for IPA v4.2 and above */ |
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#define SSPND_PA_NO_START_STATE GENMASK(18, 18) |
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#define SSPND_PA_NO_BQ_STATE GENMASK(19, 19) |
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#define IPA_REG_FLAVOR_0_OFFSET 0x00000210 |
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#define BAM_MAX_PIPES_FMASK GENMASK(4, 0) |
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#define BAM_MAX_CONS_PIPES_FMASK GENMASK(12, 8) |
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#define BAM_MAX_PROD_PIPES_FMASK GENMASK(20, 16) |
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#define BAM_PROD_LOWEST_FMASK GENMASK(27, 24) |
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static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) |
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{ |
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if (version == IPA_VERSION_4_2) |
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return 0x00000240; |
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return 0x00000220; |
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} |
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#define ENTER_IDLE_DEBOUNCE_THRESH_FMASK GENMASK(15, 0) |
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#define CONST_NON_IDLE_ENABLE_FMASK GENMASK(16, 16) |
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#define IPA_REG_SRC_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ |
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(0x00000400 + 0x0020 * (rt)) |
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#define IPA_REG_SRC_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ |
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(0x00000404 + 0x0020 * (rt)) |
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#define IPA_REG_SRC_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ |
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(0x00000408 + 0x0020 * (rt)) |
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#define IPA_REG_DST_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ |
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(0x00000500 + 0x0020 * (rt)) |
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#define IPA_REG_DST_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ |
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(0x00000504 + 0x0020 * (rt)) |
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#define IPA_REG_DST_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ |
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(0x00000508 + 0x0020 * (rt)) |
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#define X_MIN_LIM_FMASK GENMASK(5, 0) |
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#define X_MAX_LIM_FMASK GENMASK(13, 8) |
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#define Y_MIN_LIM_FMASK GENMASK(21, 16) |
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#define Y_MAX_LIM_FMASK GENMASK(29, 24) |
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#define IPA_REG_ENDP_INIT_CTRL_N_OFFSET(ep) \ |
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(0x00000800 + 0x0070 * (ep)) |
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#define ENDP_SUSPEND_FMASK GENMASK(0, 0) |
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#define ENDP_DELAY_FMASK GENMASK(1, 1) |
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#define IPA_REG_ENDP_INIT_CFG_N_OFFSET(ep) \ |
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(0x00000808 + 0x0070 * (ep)) |
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#define FRAG_OFFLOAD_EN_FMASK GENMASK(0, 0) |
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#define CS_OFFLOAD_EN_FMASK GENMASK(2, 1) |
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#define CS_METADATA_HDR_OFFSET_FMASK GENMASK(6, 3) |
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#define CS_GEN_QMB_MASTER_SEL_FMASK GENMASK(8, 8) |
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#define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \ |
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(0x00000810 + 0x0070 * (ep)) |
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#define HDR_LEN_FMASK GENMASK(5, 0) |
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#define HDR_OFST_METADATA_VALID_FMASK GENMASK(6, 6) |
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#define HDR_OFST_METADATA_FMASK GENMASK(12, 7) |
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#define HDR_ADDITIONAL_CONST_LEN_FMASK GENMASK(18, 13) |
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#define HDR_OFST_PKT_SIZE_VALID_FMASK GENMASK(19, 19) |
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#define HDR_OFST_PKT_SIZE_FMASK GENMASK(25, 20) |
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#define HDR_A5_MUX_FMASK GENMASK(26, 26) |
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#define HDR_LEN_INC_DEAGG_HDR_FMASK GENMASK(27, 27) |
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#define HDR_METADATA_REG_VALID_FMASK GENMASK(28, 28) |
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#define IPA_REG_ENDP_INIT_HDR_EXT_N_OFFSET(ep) \ |
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(0x00000814 + 0x0070 * (ep)) |
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#define HDR_ENDIANNESS_FMASK GENMASK(0, 0) |
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#define HDR_TOTAL_LEN_OR_PAD_VALID_FMASK GENMASK(1, 1) |
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#define HDR_TOTAL_LEN_OR_PAD_FMASK GENMASK(2, 2) |
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#define HDR_PAYLOAD_LEN_INC_PADDING_FMASK GENMASK(3, 3) |
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#define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK GENMASK(9, 4) |
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#define HDR_PAD_TO_ALIGNMENT_FMASK GENMASK(13, 10) |
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/* Valid only for RX (IPA producer) endpoints */ |
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#define IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(rxep) \ |
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(0x00000818 + 0x0070 * (rxep)) |
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/* Valid only for TX (IPA consumer) endpoints */ |
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#define IPA_REG_ENDP_INIT_MODE_N_OFFSET(txep) \ |
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(0x00000820 + 0x0070 * (txep)) |
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#define MODE_FMASK GENMASK(2, 0) |
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#define DEST_PIPE_INDEX_FMASK GENMASK(8, 4) |
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#define BYTE_THRESHOLD_FMASK GENMASK(27, 12) |
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#define PIPE_REPLICATION_EN_FMASK GENMASK(28, 28) |
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#define PAD_EN_FMASK GENMASK(29, 29) |
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#define HDR_FTCH_DISABLE_FMASK GENMASK(30, 30) |
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#define IPA_REG_ENDP_INIT_AGGR_N_OFFSET(ep) \ |
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(0x00000824 + 0x0070 * (ep)) |
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#define AGGR_EN_FMASK GENMASK(1, 0) |
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#define AGGR_TYPE_FMASK GENMASK(4, 2) |
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#define AGGR_BYTE_LIMIT_FMASK GENMASK(9, 5) |
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#define AGGR_TIME_LIMIT_FMASK GENMASK(14, 10) |
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#define AGGR_PKT_LIMIT_FMASK GENMASK(20, 15) |
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#define AGGR_SW_EOF_ACTIVE_FMASK GENMASK(21, 21) |
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#define AGGR_FORCE_CLOSE_FMASK GENMASK(22, 22) |
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#define AGGR_HARD_BYTE_LIMIT_ENABLE_FMASK GENMASK(24, 24) |
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/* Valid only for RX (IPA producer) endpoints */ |
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#define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(rxep) \ |
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(0x0000082c + 0x0070 * (rxep)) |
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#define HOL_BLOCK_EN_FMASK GENMASK(0, 0) |
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/* Valid only for RX (IPA producer) endpoints */ |
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#define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(rxep) \ |
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(0x00000830 + 0x0070 * (rxep)) |
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/* The next fields are present for IPA v4.2 only */ |
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#define BASE_VALUE_FMASK GENMASK(4, 0) |
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#define SCALE_FMASK GENMASK(12, 8) |
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/* Valid only for TX (IPA consumer) endpoints */ |
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#define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(txep) \ |
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(0x00000834 + 0x0070 * (txep)) |
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#define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0) |
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#define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7) |
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#define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8) |
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#define MAX_PACKET_LEN_FMASK GENMASK(31, 16) |
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#define IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(ep) \ |
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(0x00000838 + 0x0070 * (ep)) |
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#define RSRC_GRP_FMASK GENMASK(1, 0) |
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/* Valid only for TX (IPA consumer) endpoints */ |
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#define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(txep) \ |
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(0x0000083c + 0x0070 * (txep)) |
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#define HPS_SEQ_TYPE_FMASK GENMASK(3, 0) |
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#define DPS_SEQ_TYPE_FMASK GENMASK(7, 4) |
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#define HPS_REP_SEQ_TYPE_FMASK GENMASK(11, 8) |
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#define DPS_REP_SEQ_TYPE_FMASK GENMASK(15, 12) |
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#define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \ |
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(0x00000840 + 0x0070 * (ep)) |
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#define STATUS_EN_FMASK GENMASK(0, 0) |
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#define STATUS_ENDP_FMASK GENMASK(5, 1) |
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#define STATUS_LOCATION_FMASK GENMASK(8, 8) |
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/* The next field is present for IPA v4.0 and above */ |
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#define STATUS_PKT_SUPPRESS_FMASK GENMASK(9, 9) |
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/* "er" is either an endpoint ID (for filters) or a route ID (for routes) */ |
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#define IPA_REG_ENDP_FILTER_ROUTER_HSH_CFG_N_OFFSET(er) \ |
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(0x0000085c + 0x0070 * (er)) |
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#define FILTER_HASH_MSK_SRC_ID_FMASK GENMASK(0, 0) |
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#define FILTER_HASH_MSK_SRC_IP_FMASK GENMASK(1, 1) |
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#define FILTER_HASH_MSK_DST_IP_FMASK GENMASK(2, 2) |
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#define FILTER_HASH_MSK_SRC_PORT_FMASK GENMASK(3, 3) |
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#define FILTER_HASH_MSK_DST_PORT_FMASK GENMASK(4, 4) |
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#define FILTER_HASH_MSK_PROTOCOL_FMASK GENMASK(5, 5) |
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#define FILTER_HASH_MSK_METADATA_FMASK GENMASK(6, 6) |
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#define IPA_REG_ENDP_FILTER_HASH_MSK_ALL GENMASK(6, 0) |
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#define ROUTER_HASH_MSK_SRC_ID_FMASK GENMASK(16, 16) |
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#define ROUTER_HASH_MSK_SRC_IP_FMASK GENMASK(17, 17) |
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#define ROUTER_HASH_MSK_DST_IP_FMASK GENMASK(18, 18) |
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#define ROUTER_HASH_MSK_SRC_PORT_FMASK GENMASK(19, 19) |
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#define ROUTER_HASH_MSK_DST_PORT_FMASK GENMASK(20, 20) |
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#define ROUTER_HASH_MSK_PROTOCOL_FMASK GENMASK(21, 21) |
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#define ROUTER_HASH_MSK_METADATA_FMASK GENMASK(22, 22) |
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#define IPA_REG_ENDP_ROUTER_HASH_MSK_ALL GENMASK(22, 16) |
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#define IPA_REG_IRQ_STTS_OFFSET \ |
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IPA_REG_IRQ_STTS_EE_N_OFFSET(GSI_EE_AP) |
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#define IPA_REG_IRQ_STTS_EE_N_OFFSET(ee) \ |
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(0x00003008 + 0x1000 * (ee)) |
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#define IPA_REG_IRQ_EN_OFFSET \ |
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IPA_REG_IRQ_EN_EE_N_OFFSET(GSI_EE_AP) |
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#define IPA_REG_IRQ_EN_EE_N_OFFSET(ee) \ |
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(0x0000300c + 0x1000 * (ee)) |
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#define IPA_REG_IRQ_CLR_OFFSET \ |
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IPA_REG_IRQ_CLR_EE_N_OFFSET(GSI_EE_AP) |
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#define IPA_REG_IRQ_CLR_EE_N_OFFSET(ee) \ |
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(0x00003010 + 0x1000 * (ee)) |
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#define IPA_REG_IRQ_UC_OFFSET \ |
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IPA_REG_IRQ_UC_EE_N_OFFSET(GSI_EE_AP) |
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#define IPA_REG_IRQ_UC_EE_N_OFFSET(ee) \ |
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(0x0000301c + 0x1000 * (ee)) |
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#define IPA_REG_IRQ_SUSPEND_INFO_OFFSET \ |
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IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(GSI_EE_AP) |
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#define IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(ee) \ |
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(0x00003030 + 0x1000 * (ee)) |
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/* ipa->available defines the valid bits in the SUSPEND_INFO register */ |
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#define IPA_REG_SUSPEND_IRQ_EN_OFFSET \ |
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IPA_REG_SUSPEND_IRQ_EN_EE_N_OFFSET(GSI_EE_AP) |
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#define IPA_REG_SUSPEND_IRQ_EN_EE_N_OFFSET(ee) \ |
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(0x00003034 + 0x1000 * (ee)) |
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/* ipa->available defines the valid bits in the SUSPEND_IRQ_EN register */ |
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#define IPA_REG_SUSPEND_IRQ_CLR_OFFSET \ |
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IPA_REG_SUSPEND_IRQ_CLR_EE_N_OFFSET(GSI_EE_AP) |
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#define IPA_REG_SUSPEND_IRQ_CLR_EE_N_OFFSET(ee) \ |
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(0x00003038 + 0x1000 * (ee)) |
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/* ipa->available defines the valid bits in the SUSPEND_IRQ_CLR register */ |
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/** enum ipa_cs_offload_en - checksum offload field in ENDP_INIT_CFG_N */ |
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enum ipa_cs_offload_en { |
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IPA_CS_OFFLOAD_NONE = 0, |
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IPA_CS_OFFLOAD_UL = 1, |
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IPA_CS_OFFLOAD_DL = 2, |
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IPA_CS_RSVD |
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}; |
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/** enum ipa_aggr_en - aggregation enable field in ENDP_INIT_AGGR_N */ |
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enum ipa_aggr_en { |
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IPA_BYPASS_AGGR = 0, |
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IPA_ENABLE_AGGR = 1, |
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IPA_ENABLE_DEAGGR = 2, |
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}; |
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/** enum ipa_aggr_type - aggregation type field in in_ENDP_INIT_AGGR_N */ |
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enum ipa_aggr_type { |
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IPA_MBIM_16 = 0, |
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IPA_HDLC = 1, |
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IPA_TLP = 2, |
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IPA_RNDIS = 3, |
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IPA_GENERIC = 4, |
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IPA_COALESCE = 5, |
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IPA_QCMAP = 6, |
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}; |
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/** enum ipa_mode - mode field in ENDP_INIT_MODE_N */ |
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enum ipa_mode { |
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IPA_BASIC = 0, |
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IPA_ENABLE_FRAMING_HDLC = 1, |
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IPA_ENABLE_DEFRAMING_HDLC = 2, |
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IPA_DMA = 3, |
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}; |
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/** |
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* enum ipa_seq_type - HPS and DPS sequencer type fields in in ENDP_INIT_SEQ_N |
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* @IPA_SEQ_DMA_ONLY: only DMA is performed |
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* @IPA_SEQ_PKT_PROCESS_NO_DEC_UCP: |
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* packet processing + no decipher + microcontroller (Ethernet Bridging) |
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* @IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP: |
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* second packet processing pass + no decipher + microcontroller |
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* @IPA_SEQ_DMA_DEC: DMA + cipher/decipher |
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* @IPA_SEQ_DMA_COMP_DECOMP: DMA + compression/decompression |
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* @IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP: |
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* packet processing + no decipher + no uCP + HPS REP DMA parser |
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* @IPA_SEQ_INVALID: invalid sequencer type |
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* |
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* The values defined here are broken into 4-bit nibbles that are written |
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* into fields of the INIT_SEQ_N endpoint registers. |
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*/ |
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enum ipa_seq_type { |
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IPA_SEQ_DMA_ONLY = 0x0000, |
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IPA_SEQ_PKT_PROCESS_NO_DEC_UCP = 0x0002, |
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IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP = 0x0004, |
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IPA_SEQ_DMA_DEC = 0x0011, |
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IPA_SEQ_DMA_COMP_DECOMP = 0x0020, |
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IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP = 0x0806, |
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IPA_SEQ_INVALID = 0xffff, |
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}; |
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int ipa_reg_init(struct ipa *ipa); |
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void ipa_reg_exit(struct ipa *ipa); |
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#endif /* _IPA_REG_H_ */
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