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551 lines
12 KiB
551 lines
12 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* SuperH Ethernet device driver |
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* |
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* Copyright (C) 2006-2012 Nobuhiro Iwamatsu |
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* Copyright (C) 2008-2012 Renesas Solutions Corp. |
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*/ |
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#ifndef __SH_ETH_H__ |
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#define __SH_ETH_H__ |
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#define CARDNAME "sh-eth" |
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#define TX_TIMEOUT (5*HZ) |
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#define TX_RING_SIZE 64 /* Tx ring size */ |
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#define RX_RING_SIZE 64 /* Rx ring size */ |
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#define TX_RING_MIN 64 |
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#define RX_RING_MIN 64 |
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#define TX_RING_MAX 1024 |
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#define RX_RING_MAX 1024 |
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#define PKT_BUF_SZ 1538 |
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#define SH_ETH_TSU_TIMEOUT_MS 500 |
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#define SH_ETH_TSU_CAM_ENTRIES 32 |
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enum { |
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/* IMPORTANT: To keep ethtool register dump working, add new |
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* register names immediately before SH_ETH_MAX_REGISTER_OFFSET. |
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*/ |
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/* E-DMAC registers */ |
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EDSR = 0, |
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EDMR, |
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EDTRR, |
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EDRRR, |
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EESR, |
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EESIPR, |
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TDLAR, |
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TDFAR, |
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TDFXR, |
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TDFFR, |
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RDLAR, |
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RDFAR, |
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RDFXR, |
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RDFFR, |
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TRSCER, |
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RMFCR, |
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TFTR, |
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FDR, |
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RMCR, |
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EDOCR, |
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TFUCR, |
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RFOCR, |
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RMIIMODE, |
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FCFTR, |
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RPADIR, |
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TRIMD, |
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RBWAR, |
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TBRAR, |
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/* Ether registers */ |
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ECMR, |
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ECSR, |
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ECSIPR, |
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PIR, |
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PSR, |
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RDMLR, |
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PIPR, |
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RFLR, |
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IPGR, |
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APR, |
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MPR, |
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PFTCR, |
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PFRCR, |
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RFCR, |
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RFCF, |
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TPAUSER, |
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TPAUSECR, |
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BCFR, |
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BCFRR, |
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GECMR, |
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BCULR, |
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MAHR, |
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MALR, |
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TROCR, |
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CDCR, |
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LCCR, |
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CNDCR, |
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CEFCR, |
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FRECR, |
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TSFRCR, |
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TLFRCR, |
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CERCR, |
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CEECR, |
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MAFCR, |
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RTRATE, |
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CSMR, |
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RMII_MII, |
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/* TSU Absolute address */ |
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ARSTR, |
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TSU_CTRST, |
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TSU_FWEN0, |
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TSU_FWEN1, |
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TSU_FCM, |
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TSU_BSYSL0, |
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TSU_BSYSL1, |
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TSU_PRISL0, |
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TSU_PRISL1, |
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TSU_FWSL0, |
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TSU_FWSL1, |
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TSU_FWSLC, |
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TSU_QTAG0, /* Same as TSU_QTAGM0 */ |
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TSU_QTAG1, /* Same as TSU_QTAGM1 */ |
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TSU_QTAGM0, |
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TSU_QTAGM1, |
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TSU_FWSR, |
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TSU_FWINMK, |
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TSU_ADQT0, |
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TSU_ADQT1, |
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TSU_VTAG0, |
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TSU_VTAG1, |
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TSU_ADSBSY, |
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TSU_TEN, |
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TSU_POST1, |
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TSU_POST2, |
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TSU_POST3, |
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TSU_POST4, |
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TSU_ADRH0, |
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/* TSU_ADR{H,L}{0..31} are assumed to be contiguous */ |
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TXNLCR0, |
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TXALCR0, |
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RXNLCR0, |
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RXALCR0, |
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FWNLCR0, |
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FWALCR0, |
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TXNLCR1, |
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TXALCR1, |
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RXNLCR1, |
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RXALCR1, |
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FWNLCR1, |
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FWALCR1, |
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/* This value must be written at last. */ |
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SH_ETH_MAX_REGISTER_OFFSET, |
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}; |
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enum { |
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SH_ETH_REG_GIGABIT, |
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SH_ETH_REG_FAST_RCAR, |
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SH_ETH_REG_FAST_SH4, |
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SH_ETH_REG_FAST_SH3_SH2 |
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}; |
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/* Driver's parameters */ |
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#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RENESAS) |
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#define SH_ETH_RX_ALIGN 32 |
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#else |
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#define SH_ETH_RX_ALIGN 2 |
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#endif |
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/* Register's bits |
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*/ |
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/* EDSR : sh7734, sh7757, sh7763, r8a7740, and r7s72100 only */ |
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enum EDSR_BIT { |
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EDSR_ENT = 0x01, EDSR_ENR = 0x02, |
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}; |
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#define EDSR_ENALL (EDSR_ENT|EDSR_ENR) |
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/* GECMR : sh7734, sh7763 and r8a7740 only */ |
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enum GECMR_BIT { |
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GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01, |
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}; |
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/* EDMR */ |
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enum DMAC_M_BIT { |
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EDMR_NBST = 0x80, |
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EDMR_EL = 0x40, /* Litte endian */ |
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EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, |
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EDMR_SRST_GETHER = 0x03, |
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EDMR_SRST_ETHER = 0x01, |
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}; |
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/* EDTRR */ |
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enum DMAC_T_BIT { |
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EDTRR_TRNS_GETHER = 0x03, |
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EDTRR_TRNS_ETHER = 0x01, |
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}; |
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/* EDRRR */ |
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enum EDRRR_R_BIT { |
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EDRRR_R = 0x01, |
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}; |
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/* TPAUSER */ |
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enum TPAUSER_BIT { |
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TPAUSER_TPAUSE = 0x0000ffff, |
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TPAUSER_UNLIMITED = 0, |
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}; |
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/* BCFR */ |
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enum BCFR_BIT { |
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BCFR_RPAUSE = 0x0000ffff, |
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BCFR_UNLIMITED = 0, |
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}; |
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/* PIR */ |
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enum PIR_BIT { |
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PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01, |
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}; |
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/* PSR */ |
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enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; |
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/* EESR */ |
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enum EESR_BIT { |
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EESR_TWB1 = 0x80000000, |
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EESR_TWB = 0x40000000, /* same as TWB0 */ |
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EESR_TC1 = 0x20000000, |
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EESR_TUC = 0x10000000, |
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EESR_ROC = 0x08000000, |
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EESR_TABT = 0x04000000, |
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EESR_RABT = 0x02000000, |
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EESR_RFRMER = 0x01000000, /* same as RFCOF */ |
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EESR_ADE = 0x00800000, |
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EESR_ECI = 0x00400000, |
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EESR_FTC = 0x00200000, /* same as TC or TC0 */ |
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EESR_TDE = 0x00100000, |
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EESR_TFE = 0x00080000, /* same as TFUF */ |
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EESR_FRC = 0x00040000, /* same as FR */ |
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EESR_RDE = 0x00020000, |
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EESR_RFE = 0x00010000, |
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EESR_CND = 0x00000800, |
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EESR_DLC = 0x00000400, |
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EESR_CD = 0x00000200, |
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EESR_TRO = 0x00000100, |
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EESR_RMAF = 0x00000080, |
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EESR_CEEF = 0x00000040, |
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EESR_CELF = 0x00000020, |
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EESR_RRF = 0x00000010, |
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EESR_RTLF = 0x00000008, |
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EESR_RTSF = 0x00000004, |
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EESR_PRE = 0x00000002, |
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EESR_CERF = 0x00000001, |
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}; |
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#define EESR_RX_CHECK (EESR_FRC | /* Frame recv */ \ |
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EESR_RMAF | /* Multicast address recv */ \ |
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EESR_RRF | /* Bit frame recv */ \ |
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EESR_RTLF | /* Long frame recv */ \ |
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EESR_RTSF | /* Short frame recv */ \ |
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EESR_PRE | /* PHY-LSI recv error */ \ |
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EESR_CERF) /* Recv frame CRC error */ |
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#define DEFAULT_TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \ |
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EESR_TRO) |
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#define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | \ |
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EESR_RDE | EESR_RFRMER | EESR_ADE | \ |
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EESR_TFE | EESR_TDE) |
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/* EESIPR */ |
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enum EESIPR_BIT { |
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EESIPR_TWB1IP = 0x80000000, |
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EESIPR_TWBIP = 0x40000000, /* same as TWB0IP */ |
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EESIPR_TC1IP = 0x20000000, |
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EESIPR_TUCIP = 0x10000000, |
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EESIPR_ROCIP = 0x08000000, |
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EESIPR_TABTIP = 0x04000000, |
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EESIPR_RABTIP = 0x02000000, |
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EESIPR_RFCOFIP = 0x01000000, |
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EESIPR_ADEIP = 0x00800000, |
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EESIPR_ECIIP = 0x00400000, |
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EESIPR_FTCIP = 0x00200000, /* same as TC0IP */ |
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EESIPR_TDEIP = 0x00100000, |
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EESIPR_TFUFIP = 0x00080000, |
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EESIPR_FRIP = 0x00040000, |
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EESIPR_RDEIP = 0x00020000, |
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EESIPR_RFOFIP = 0x00010000, |
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EESIPR_CNDIP = 0x00000800, |
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EESIPR_DLCIP = 0x00000400, |
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EESIPR_CDIP = 0x00000200, |
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EESIPR_TROIP = 0x00000100, |
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EESIPR_RMAFIP = 0x00000080, |
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EESIPR_CEEFIP = 0x00000040, |
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EESIPR_CELFIP = 0x00000020, |
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EESIPR_RRFIP = 0x00000010, |
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EESIPR_RTLFIP = 0x00000008, |
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EESIPR_RTSFIP = 0x00000004, |
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EESIPR_PREIP = 0x00000002, |
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EESIPR_CERFIP = 0x00000001, |
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}; |
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/* Receive descriptor 0 bits */ |
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enum RD_STS_BIT { |
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RD_RACT = 0x80000000, RD_RDLE = 0x40000000, |
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RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000, |
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RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, |
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RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, |
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RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, |
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RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008, |
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RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, |
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RD_RFS1 = 0x00000001, |
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}; |
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#define RDF1ST RD_RFP1 |
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#define RDFEND RD_RFP0 |
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#define RD_RFP (RD_RFP1|RD_RFP0) |
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/* Receive descriptor 1 bits */ |
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enum RD_LEN_BIT { |
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RD_RFL = 0x0000ffff, /* receive frame length */ |
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RD_RBL = 0xffff0000, /* receive buffer length */ |
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}; |
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/* FCFTR */ |
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enum FCFTR_BIT { |
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FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, |
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FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004, |
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FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, |
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}; |
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#define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0) |
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#define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0) |
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/* Transmit descriptor 0 bits */ |
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enum TD_STS_BIT { |
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TD_TACT = 0x80000000, TD_TDLE = 0x40000000, |
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TD_TFP1 = 0x20000000, TD_TFP0 = 0x10000000, |
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TD_TFE = 0x08000000, TD_TWBI = 0x04000000, |
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}; |
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#define TDF1ST TD_TFP1 |
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#define TDFEND TD_TFP0 |
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#define TD_TFP (TD_TFP1|TD_TFP0) |
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/* Transmit descriptor 1 bits */ |
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enum TD_LEN_BIT { |
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TD_TBL = 0xffff0000, /* transmit buffer length */ |
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}; |
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/* RMCR */ |
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enum RMCR_BIT { |
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RMCR_RNC = 0x00000001, |
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}; |
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/* ECMR */ |
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enum FELIC_MODE_BIT { |
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ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000, |
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ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000, |
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ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, |
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ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, |
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ECMR_MPDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, |
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ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, |
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ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001, |
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}; |
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/* ECSR */ |
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enum ECSR_STATUS_BIT { |
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ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, |
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ECSR_LCHNG = 0x04, |
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ECSR_MPD = 0x02, ECSR_ICD = 0x01, |
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}; |
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#define DEFAULT_ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \ |
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ECSR_ICD | ECSIPR_MPDIP) |
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/* ECSIPR */ |
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enum ECSIPR_STATUS_MASK_BIT { |
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ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10, |
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ECSIPR_LCHNGIP = 0x04, |
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ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01, |
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}; |
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#define DEFAULT_ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \ |
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ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) |
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/* APR */ |
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enum APR_BIT { |
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APR_AP = 0x0000ffff, |
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}; |
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/* MPR */ |
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enum MPR_BIT { |
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MPR_MP = 0x0000ffff, |
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}; |
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/* TRSCER */ |
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enum DESC_I_BIT { |
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DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200, |
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DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010, |
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DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002, |
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DESC_I_RINT1 = 0x0001, |
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}; |
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#define DEFAULT_TRSCER_ERR_MASK (DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2) |
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/* RPADIR */ |
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enum RPADIR_BIT { |
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RPADIR_PADS = 0x1f0000, RPADIR_PADR = 0xffff, |
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}; |
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/* FDR */ |
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#define DEFAULT_FDR_INIT 0x00000707 |
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/* ARSTR */ |
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enum ARSTR_BIT { ARSTR_ARST = 0x00000001, }; |
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/* TSU_FWEN0 */ |
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enum TSU_FWEN0_BIT { |
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TSU_FWEN0_0 = 0x00000001, |
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}; |
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/* TSU_ADSBSY */ |
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enum TSU_ADSBSY_BIT { |
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TSU_ADSBSY_0 = 0x00000001, |
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}; |
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/* TSU_TEN */ |
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enum TSU_TEN_BIT { |
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TSU_TEN_0 = 0x80000000, |
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}; |
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/* TSU_FWSL0 */ |
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enum TSU_FWSL0_BIT { |
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TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800, |
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TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200, |
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TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010, |
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}; |
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/* TSU_FWSLC */ |
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enum TSU_FWSLC_BIT { |
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TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000, |
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TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040, |
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TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010, |
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TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004, |
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TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001, |
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}; |
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/* TSU_VTAGn */ |
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#define TSU_VTAG_ENABLE 0x80000000 |
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#define TSU_VTAG_VID_MASK 0x00000fff |
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/* The sh ether Tx buffer descriptors. |
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* This structure should be 20 bytes. |
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*/ |
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struct sh_eth_txdesc { |
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u32 status; /* TD0 */ |
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u32 len; /* TD1 */ |
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u32 addr; /* TD2 */ |
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u32 pad0; /* padding data */ |
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} __aligned(2) __packed; |
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/* The sh ether Rx buffer descriptors. |
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* This structure should be 20 bytes. |
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*/ |
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struct sh_eth_rxdesc { |
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u32 status; /* RD0 */ |
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u32 len; /* RD1 */ |
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u32 addr; /* RD2 */ |
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u32 pad0; /* padding data */ |
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} __aligned(2) __packed; |
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/* This structure is used by each CPU dependency handling. */ |
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struct sh_eth_cpu_data { |
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/* mandatory functions */ |
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int (*soft_reset)(struct net_device *ndev); |
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/* optional functions */ |
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void (*chip_reset)(struct net_device *ndev); |
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void (*set_duplex)(struct net_device *ndev); |
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void (*set_rate)(struct net_device *ndev); |
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/* mandatory initialize value */ |
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int register_type; |
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u32 edtrr_trns; |
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u32 eesipr_value; |
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/* optional initialize value */ |
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u32 ecsr_value; |
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u32 ecsipr_value; |
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u32 fdr_value; |
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u32 fcftr_value; |
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/* interrupt checking mask */ |
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u32 tx_check; |
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u32 eesr_err_check; |
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/* Error mask */ |
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u32 trscer_err_mask; |
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/* hardware features */ |
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unsigned long irq_flags; /* IRQ configuration flags */ |
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unsigned no_psr:1; /* EtherC DOES NOT have PSR */ |
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unsigned apr:1; /* EtherC has APR */ |
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unsigned mpr:1; /* EtherC has MPR */ |
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unsigned tpauser:1; /* EtherC has TPAUSER */ |
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unsigned gecmr:1; /* EtherC has GECMR */ |
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unsigned bculr:1; /* EtherC has BCULR */ |
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unsigned tsu:1; /* EtherC has TSU */ |
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unsigned hw_swap:1; /* E-DMAC has DE bit in EDMR */ |
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unsigned nbst:1; /* E-DMAC has NBST bit in EDMR */ |
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unsigned rpadir:1; /* E-DMAC has RPADIR */ |
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unsigned no_trimd:1; /* E-DMAC DOES NOT have TRIMD */ |
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unsigned no_ade:1; /* E-DMAC DOES NOT have ADE bit in EESR */ |
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unsigned no_xdfar:1; /* E-DMAC DOES NOT have RDFAR/TDFAR */ |
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unsigned xdfar_rw:1; /* E-DMAC has writeable RDFAR/TDFAR */ |
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unsigned csmr:1; /* E-DMAC has CSMR */ |
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unsigned rx_csum:1; /* EtherC has ECMR.RCSC */ |
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unsigned select_mii:1; /* EtherC has RMII_MII (MII select register) */ |
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unsigned rmiimode:1; /* EtherC has RMIIMODE register */ |
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unsigned rtrate:1; /* EtherC has RTRATE register */ |
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unsigned magic:1; /* EtherC has ECMR.MPDE and ECSR.MPD */ |
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unsigned no_tx_cntrs:1; /* EtherC DOES NOT have TX error counters */ |
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unsigned cexcr:1; /* EtherC has CERCR/CEECR */ |
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unsigned dual_port:1; /* Dual EtherC/E-DMAC */ |
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}; |
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struct sh_eth_private { |
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struct platform_device *pdev; |
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struct sh_eth_cpu_data *cd; |
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const u16 *reg_offset; |
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void __iomem *addr; |
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void __iomem *tsu_addr; |
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struct clk *clk; |
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u32 num_rx_ring; |
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u32 num_tx_ring; |
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dma_addr_t rx_desc_dma; |
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dma_addr_t tx_desc_dma; |
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struct sh_eth_rxdesc *rx_ring; |
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struct sh_eth_txdesc *tx_ring; |
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struct sk_buff **rx_skbuff; |
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struct sk_buff **tx_skbuff; |
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spinlock_t lock; /* Register access lock */ |
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u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */ |
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u32 cur_tx, dirty_tx; |
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u32 rx_buf_sz; /* Based on MTU+slack. */ |
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struct napi_struct napi; |
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bool irq_enabled; |
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/* MII transceiver section. */ |
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u32 phy_id; /* PHY ID */ |
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struct mii_bus *mii_bus; /* MDIO bus control */ |
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int link; |
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phy_interface_t phy_interface; |
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int msg_enable; |
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int speed; |
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int duplex; |
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int port; /* for TSU */ |
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int vlan_num_ids; /* for VLAN tag filter */ |
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unsigned no_ether_link:1; |
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unsigned ether_link_active_low:1; |
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unsigned is_opened:1; |
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unsigned wol_enabled:1; |
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}; |
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#endif /* #ifndef __SH_ETH_H__ */
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