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126 lines
2.9 KiB
126 lines
2.9 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// Copyright (c) 2018-2019 MediaTek Inc. |
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/* A library for MediaTek SGMII circuit |
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* |
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* Author: Sean Wang <[email protected]> |
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* |
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*/ |
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#include <linux/mfd/syscon.h> |
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#include <linux/of.h> |
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#include <linux/regmap.h> |
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#include "mtk_eth_soc.h" |
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int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3) |
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{ |
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struct device_node *np; |
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int i; |
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ss->ana_rgc3 = ana_rgc3; |
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for (i = 0; i < MTK_MAX_DEVS; i++) { |
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np = of_parse_phandle(r, "mediatek,sgmiisys", i); |
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if (!np) |
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break; |
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ss->regmap[i] = syscon_node_to_regmap(np); |
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if (IS_ERR(ss->regmap[i])) |
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return PTR_ERR(ss->regmap[i]); |
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} |
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return 0; |
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} |
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int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id) |
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{ |
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unsigned int val; |
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if (!ss->regmap[id]) |
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return -EINVAL; |
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/* Setup the link timer and QPHY power up inside SGMIISYS */ |
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regmap_write(ss->regmap[id], SGMSYS_PCS_LINK_TIMER, |
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SGMII_LINK_TIMER_DEFAULT); |
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regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val); |
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val |= SGMII_REMOTE_FAULT_DIS; |
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regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val); |
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regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val); |
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val |= SGMII_AN_RESTART; |
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regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val); |
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regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val); |
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val &= ~SGMII_PHYA_PWD; |
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regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val); |
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return 0; |
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} |
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int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id, |
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const struct phylink_link_state *state) |
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{ |
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unsigned int val; |
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if (!ss->regmap[id]) |
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return -EINVAL; |
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regmap_read(ss->regmap[id], ss->ana_rgc3, &val); |
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val &= ~RG_PHY_SPEED_MASK; |
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if (state->interface == PHY_INTERFACE_MODE_2500BASEX) |
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val |= RG_PHY_SPEED_3_125G; |
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regmap_write(ss->regmap[id], ss->ana_rgc3, val); |
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/* Disable SGMII AN */ |
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regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val); |
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val &= ~SGMII_AN_ENABLE; |
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regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val); |
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/* SGMII force mode setting */ |
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regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val); |
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val &= ~SGMII_IF_MODE_MASK; |
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switch (state->speed) { |
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case SPEED_10: |
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val |= SGMII_SPEED_10; |
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break; |
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case SPEED_100: |
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val |= SGMII_SPEED_100; |
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break; |
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case SPEED_2500: |
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case SPEED_1000: |
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val |= SGMII_SPEED_1000; |
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break; |
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} |
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if (state->duplex == DUPLEX_FULL) |
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val |= SGMII_DUPLEX_FULL; |
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regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val); |
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/* Release PHYA power down state */ |
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regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val); |
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val &= ~SGMII_PHYA_PWD; |
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regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val); |
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return 0; |
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} |
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void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id) |
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{ |
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struct mtk_sgmii *ss = eth->sgmii; |
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unsigned int val, sid; |
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/* Decide how GMAC and SGMIISYS be mapped */ |
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sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? |
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0 : mac_id; |
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if (!ss->regmap[sid]) |
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return; |
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regmap_read(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, &val); |
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val |= SGMII_AN_RESTART; |
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regmap_write(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, val); |
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}
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