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717 lines
18 KiB
717 lines
18 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* Copyright(c) 1999 - 2018 Intel Corporation. */ |
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#ifndef _E1000_HW_H_ |
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#define _E1000_HW_H_ |
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#include "regs.h" |
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#include "defines.h" |
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struct e1000_hw; |
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#define E1000_DEV_ID_82571EB_COPPER 0x105E |
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#define E1000_DEV_ID_82571EB_FIBER 0x105F |
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#define E1000_DEV_ID_82571EB_SERDES 0x1060 |
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#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 |
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#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 |
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#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 |
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#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC |
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#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 |
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#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA |
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#define E1000_DEV_ID_82572EI_COPPER 0x107D |
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#define E1000_DEV_ID_82572EI_FIBER 0x107E |
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#define E1000_DEV_ID_82572EI_SERDES 0x107F |
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#define E1000_DEV_ID_82572EI 0x10B9 |
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#define E1000_DEV_ID_82573E 0x108B |
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#define E1000_DEV_ID_82573E_IAMT 0x108C |
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#define E1000_DEV_ID_82573L 0x109A |
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#define E1000_DEV_ID_82574L 0x10D3 |
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#define E1000_DEV_ID_82574LA 0x10F6 |
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#define E1000_DEV_ID_82583V 0x150C |
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#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 |
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#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 |
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#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA |
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#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB |
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#define E1000_DEV_ID_ICH8_82567V_3 0x1501 |
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#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 |
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#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A |
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#define E1000_DEV_ID_ICH8_IGP_C 0x104B |
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#define E1000_DEV_ID_ICH8_IFE 0x104C |
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#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 |
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#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 |
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#define E1000_DEV_ID_ICH8_IGP_M 0x104D |
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#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD |
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#define E1000_DEV_ID_ICH9_BM 0x10E5 |
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#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 |
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#define E1000_DEV_ID_ICH9_IGP_M 0x10BF |
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#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB |
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#define E1000_DEV_ID_ICH9_IGP_C 0x294C |
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#define E1000_DEV_ID_ICH9_IFE 0x10C0 |
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#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 |
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#define E1000_DEV_ID_ICH9_IFE_G 0x10C2 |
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#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC |
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#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD |
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#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE |
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#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE |
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#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF |
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#define E1000_DEV_ID_ICH10_D_BM_V 0x1525 |
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#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA |
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#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB |
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#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF |
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#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 |
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#define E1000_DEV_ID_PCH2_LV_LM 0x1502 |
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#define E1000_DEV_ID_PCH2_LV_V 0x1503 |
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#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A |
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#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B |
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#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A |
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#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 |
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#define E1000_DEV_ID_PCH_I218_LM2 0x15A0 |
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#define E1000_DEV_ID_PCH_I218_V2 0x15A1 |
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#define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ |
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#define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ |
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#define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* SPT PCH */ |
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#define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* SPT PCH */ |
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#define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* SPT-H PCH */ |
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#define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* SPT-H PCH */ |
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#define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LBG PCH */ |
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#define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 |
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#define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 |
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#define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 |
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#define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 |
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#define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD |
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#define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE |
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#define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB |
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#define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC |
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#define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF |
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#define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0 |
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#define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1 |
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#define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2 |
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#define E1000_DEV_ID_PCH_CMP_I219_LM10 0x0D4E |
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#define E1000_DEV_ID_PCH_CMP_I219_V10 0x0D4F |
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#define E1000_DEV_ID_PCH_CMP_I219_LM11 0x0D4C |
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#define E1000_DEV_ID_PCH_CMP_I219_V11 0x0D4D |
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#define E1000_DEV_ID_PCH_CMP_I219_LM12 0x0D53 |
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#define E1000_DEV_ID_PCH_CMP_I219_V12 0x0D55 |
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#define E1000_DEV_ID_PCH_TGP_I219_LM13 0x15FB |
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#define E1000_DEV_ID_PCH_TGP_I219_V13 0x15FC |
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#define E1000_DEV_ID_PCH_TGP_I219_LM14 0x15F9 |
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#define E1000_DEV_ID_PCH_TGP_I219_V14 0x15FA |
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#define E1000_DEV_ID_PCH_TGP_I219_LM15 0x15F4 |
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#define E1000_DEV_ID_PCH_TGP_I219_V15 0x15F5 |
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#define E1000_DEV_ID_PCH_ADP_I219_LM16 0x1A1E |
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#define E1000_DEV_ID_PCH_ADP_I219_V16 0x1A1F |
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#define E1000_DEV_ID_PCH_ADP_I219_LM17 0x1A1C |
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#define E1000_DEV_ID_PCH_ADP_I219_V17 0x1A1D |
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#define E1000_DEV_ID_PCH_MTP_I219_LM18 0x550A |
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#define E1000_DEV_ID_PCH_MTP_I219_V18 0x550B |
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#define E1000_DEV_ID_PCH_MTP_I219_LM19 0x550C |
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#define E1000_DEV_ID_PCH_MTP_I219_V19 0x550D |
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#define E1000_REVISION_4 4 |
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#define E1000_FUNC_1 1 |
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#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 |
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#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 |
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enum e1000_mac_type { |
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e1000_82571, |
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e1000_82572, |
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e1000_82573, |
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e1000_82574, |
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e1000_82583, |
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e1000_80003es2lan, |
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e1000_ich8lan, |
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e1000_ich9lan, |
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e1000_ich10lan, |
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e1000_pchlan, |
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e1000_pch2lan, |
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e1000_pch_lpt, |
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e1000_pch_spt, |
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e1000_pch_cnp, |
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e1000_pch_tgp, |
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e1000_pch_adp, |
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e1000_pch_mtp, |
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}; |
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enum e1000_media_type { |
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e1000_media_type_unknown = 0, |
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e1000_media_type_copper = 1, |
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e1000_media_type_fiber = 2, |
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e1000_media_type_internal_serdes = 3, |
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e1000_num_media_types |
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}; |
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enum e1000_nvm_type { |
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e1000_nvm_unknown = 0, |
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e1000_nvm_none, |
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e1000_nvm_eeprom_spi, |
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e1000_nvm_flash_hw, |
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e1000_nvm_flash_sw |
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}; |
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enum e1000_nvm_override { |
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e1000_nvm_override_none = 0, |
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e1000_nvm_override_spi_small, |
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e1000_nvm_override_spi_large |
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}; |
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enum e1000_phy_type { |
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e1000_phy_unknown = 0, |
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e1000_phy_none, |
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e1000_phy_m88, |
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e1000_phy_igp, |
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e1000_phy_igp_2, |
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e1000_phy_gg82563, |
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e1000_phy_igp_3, |
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e1000_phy_ife, |
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e1000_phy_bm, |
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e1000_phy_82578, |
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e1000_phy_82577, |
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e1000_phy_82579, |
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e1000_phy_i217, |
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}; |
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enum e1000_bus_width { |
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e1000_bus_width_unknown = 0, |
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e1000_bus_width_pcie_x1, |
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e1000_bus_width_pcie_x2, |
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e1000_bus_width_pcie_x4 = 4, |
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e1000_bus_width_pcie_x8 = 8, |
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e1000_bus_width_32, |
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e1000_bus_width_64, |
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e1000_bus_width_reserved |
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}; |
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enum e1000_1000t_rx_status { |
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e1000_1000t_rx_status_not_ok = 0, |
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e1000_1000t_rx_status_ok, |
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e1000_1000t_rx_status_undefined = 0xFF |
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}; |
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enum e1000_rev_polarity { |
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e1000_rev_polarity_normal = 0, |
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e1000_rev_polarity_reversed, |
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e1000_rev_polarity_undefined = 0xFF |
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}; |
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enum e1000_fc_mode { |
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e1000_fc_none = 0, |
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e1000_fc_rx_pause, |
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e1000_fc_tx_pause, |
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e1000_fc_full, |
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e1000_fc_default = 0xFF |
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}; |
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enum e1000_ms_type { |
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e1000_ms_hw_default = 0, |
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e1000_ms_force_master, |
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e1000_ms_force_slave, |
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e1000_ms_auto |
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}; |
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enum e1000_smart_speed { |
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e1000_smart_speed_default = 0, |
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e1000_smart_speed_on, |
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e1000_smart_speed_off |
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}; |
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enum e1000_serdes_link_state { |
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e1000_serdes_link_down = 0, |
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e1000_serdes_link_autoneg_progress, |
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e1000_serdes_link_autoneg_complete, |
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e1000_serdes_link_forced_up |
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}; |
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/* Receive Descriptor - Extended */ |
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union e1000_rx_desc_extended { |
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struct { |
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__le64 buffer_addr; |
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__le64 reserved; |
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} read; |
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struct { |
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struct { |
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__le32 mrq; /* Multiple Rx Queues */ |
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union { |
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__le32 rss; /* RSS Hash */ |
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struct { |
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__le16 ip_id; /* IP id */ |
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__le16 csum; /* Packet Checksum */ |
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} csum_ip; |
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} hi_dword; |
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} lower; |
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struct { |
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__le32 status_error; /* ext status/error */ |
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__le16 length; |
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__le16 vlan; /* VLAN tag */ |
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} upper; |
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} wb; /* writeback */ |
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}; |
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#define MAX_PS_BUFFERS 4 |
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/* Number of packet split data buffers (not including the header buffer) */ |
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#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) |
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/* Receive Descriptor - Packet Split */ |
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union e1000_rx_desc_packet_split { |
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struct { |
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/* one buffer for protocol header(s), three data buffers */ |
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__le64 buffer_addr[MAX_PS_BUFFERS]; |
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} read; |
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struct { |
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struct { |
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__le32 mrq; /* Multiple Rx Queues */ |
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union { |
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__le32 rss; /* RSS Hash */ |
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struct { |
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__le16 ip_id; /* IP id */ |
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__le16 csum; /* Packet Checksum */ |
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} csum_ip; |
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} hi_dword; |
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} lower; |
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struct { |
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__le32 status_error; /* ext status/error */ |
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__le16 length0; /* length of buffer 0 */ |
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__le16 vlan; /* VLAN tag */ |
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} middle; |
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struct { |
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__le16 header_status; |
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/* length of buffers 1-3 */ |
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__le16 length[PS_PAGE_BUFFERS]; |
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} upper; |
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__le64 reserved; |
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} wb; /* writeback */ |
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}; |
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/* Transmit Descriptor */ |
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struct e1000_tx_desc { |
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__le64 buffer_addr; /* Address of the descriptor's data buffer */ |
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union { |
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__le32 data; |
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struct { |
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__le16 length; /* Data buffer length */ |
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u8 cso; /* Checksum offset */ |
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u8 cmd; /* Descriptor control */ |
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} flags; |
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} lower; |
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union { |
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__le32 data; |
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struct { |
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u8 status; /* Descriptor status */ |
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u8 css; /* Checksum start */ |
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__le16 special; |
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} fields; |
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} upper; |
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}; |
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/* Offload Context Descriptor */ |
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struct e1000_context_desc { |
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union { |
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__le32 ip_config; |
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struct { |
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u8 ipcss; /* IP checksum start */ |
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u8 ipcso; /* IP checksum offset */ |
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__le16 ipcse; /* IP checksum end */ |
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} ip_fields; |
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} lower_setup; |
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union { |
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__le32 tcp_config; |
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struct { |
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u8 tucss; /* TCP checksum start */ |
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u8 tucso; /* TCP checksum offset */ |
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__le16 tucse; /* TCP checksum end */ |
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} tcp_fields; |
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} upper_setup; |
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__le32 cmd_and_length; |
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union { |
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__le32 data; |
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struct { |
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u8 status; /* Descriptor status */ |
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u8 hdr_len; /* Header length */ |
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__le16 mss; /* Maximum segment size */ |
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} fields; |
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} tcp_seg_setup; |
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}; |
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/* Offload data descriptor */ |
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struct e1000_data_desc { |
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__le64 buffer_addr; /* Address of the descriptor's buffer address */ |
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union { |
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__le32 data; |
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struct { |
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__le16 length; /* Data buffer length */ |
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u8 typ_len_ext; |
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u8 cmd; |
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} flags; |
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} lower; |
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union { |
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__le32 data; |
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struct { |
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u8 status; /* Descriptor status */ |
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u8 popts; /* Packet Options */ |
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__le16 special; |
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} fields; |
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} upper; |
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}; |
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/* Statistics counters collected by the MAC */ |
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struct e1000_hw_stats { |
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u64 crcerrs; |
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u64 algnerrc; |
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u64 symerrs; |
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u64 rxerrc; |
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u64 mpc; |
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u64 scc; |
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u64 ecol; |
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u64 mcc; |
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u64 latecol; |
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u64 colc; |
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u64 dc; |
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u64 tncrs; |
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u64 sec; |
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u64 cexterr; |
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u64 rlec; |
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u64 xonrxc; |
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u64 xontxc; |
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u64 xoffrxc; |
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u64 xofftxc; |
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u64 fcruc; |
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u64 prc64; |
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u64 prc127; |
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u64 prc255; |
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u64 prc511; |
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u64 prc1023; |
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u64 prc1522; |
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u64 gprc; |
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u64 bprc; |
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u64 mprc; |
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u64 gptc; |
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u64 gorc; |
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u64 gotc; |
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u64 rnbc; |
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u64 ruc; |
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u64 rfc; |
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u64 roc; |
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u64 rjc; |
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u64 mgprc; |
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u64 mgpdc; |
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u64 mgptc; |
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u64 tor; |
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u64 tot; |
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u64 tpr; |
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u64 tpt; |
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u64 ptc64; |
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u64 ptc127; |
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u64 ptc255; |
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u64 ptc511; |
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u64 ptc1023; |
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u64 ptc1522; |
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u64 mptc; |
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u64 bptc; |
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u64 tsctc; |
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u64 tsctfc; |
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u64 iac; |
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u64 icrxptc; |
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u64 icrxatc; |
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u64 ictxptc; |
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u64 ictxatc; |
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u64 ictxqec; |
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u64 ictxqmtc; |
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u64 icrxdmtc; |
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u64 icrxoc; |
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}; |
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struct e1000_phy_stats { |
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u32 idle_errors; |
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u32 receive_errors; |
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}; |
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struct e1000_host_mng_dhcp_cookie { |
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u32 signature; |
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u8 status; |
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u8 reserved0; |
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u16 vlan_id; |
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u32 reserved1; |
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u16 reserved2; |
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u8 reserved3; |
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u8 checksum; |
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}; |
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/* Host Interface "Rev 1" */ |
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struct e1000_host_command_header { |
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u8 command_id; |
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u8 command_length; |
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u8 command_options; |
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u8 checksum; |
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}; |
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#define E1000_HI_MAX_DATA_LENGTH 252 |
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struct e1000_host_command_info { |
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struct e1000_host_command_header command_header; |
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u8 command_data[E1000_HI_MAX_DATA_LENGTH]; |
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}; |
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/* Host Interface "Rev 2" */ |
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struct e1000_host_mng_command_header { |
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u8 command_id; |
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u8 checksum; |
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u16 reserved1; |
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u16 reserved2; |
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u16 command_length; |
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}; |
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#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 |
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struct e1000_host_mng_command_info { |
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struct e1000_host_mng_command_header command_header; |
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u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; |
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}; |
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#include "mac.h" |
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#include "phy.h" |
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#include "nvm.h" |
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#include "manage.h" |
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/* Function pointers for the MAC. */ |
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struct e1000_mac_operations { |
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s32 (*id_led_init)(struct e1000_hw *); |
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s32 (*blink_led)(struct e1000_hw *); |
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bool (*check_mng_mode)(struct e1000_hw *); |
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s32 (*check_for_link)(struct e1000_hw *); |
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s32 (*cleanup_led)(struct e1000_hw *); |
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void (*clear_hw_cntrs)(struct e1000_hw *); |
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void (*clear_vfta)(struct e1000_hw *); |
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s32 (*get_bus_info)(struct e1000_hw *); |
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void (*set_lan_id)(struct e1000_hw *); |
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s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); |
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s32 (*led_on)(struct e1000_hw *); |
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s32 (*led_off)(struct e1000_hw *); |
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void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); |
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s32 (*reset_hw)(struct e1000_hw *); |
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s32 (*init_hw)(struct e1000_hw *); |
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s32 (*setup_link)(struct e1000_hw *); |
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s32 (*setup_physical_interface)(struct e1000_hw *); |
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s32 (*setup_led)(struct e1000_hw *); |
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void (*write_vfta)(struct e1000_hw *, u32, u32); |
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void (*config_collision_dist)(struct e1000_hw *); |
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int (*rar_set)(struct e1000_hw *, u8 *, u32); |
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s32 (*read_mac_addr)(struct e1000_hw *); |
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u32 (*rar_get_count)(struct e1000_hw *); |
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}; |
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/* When to use various PHY register access functions: |
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* |
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* Func Caller |
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* Function Does Does When to use |
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* ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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* X_reg L,P,A n/a for simple PHY reg accesses |
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* X_reg_locked P,A L for multiple accesses of different regs |
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* on different pages |
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* X_reg_page A L,P for multiple accesses of different regs |
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* on the same page |
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* |
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* Where X=[read|write], L=locking, P=sets page, A=register access |
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* |
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*/ |
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struct e1000_phy_operations { |
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s32 (*acquire)(struct e1000_hw *); |
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s32 (*cfg_on_link_up)(struct e1000_hw *); |
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s32 (*check_polarity)(struct e1000_hw *); |
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s32 (*check_reset_block)(struct e1000_hw *); |
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s32 (*commit)(struct e1000_hw *); |
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s32 (*force_speed_duplex)(struct e1000_hw *); |
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s32 (*get_cfg_done)(struct e1000_hw *hw); |
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s32 (*get_cable_length)(struct e1000_hw *); |
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s32 (*get_info)(struct e1000_hw *); |
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s32 (*set_page)(struct e1000_hw *, u16); |
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s32 (*read_reg)(struct e1000_hw *, u32, u16 *); |
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s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); |
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s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); |
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void (*release)(struct e1000_hw *); |
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s32 (*reset)(struct e1000_hw *); |
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s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); |
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s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); |
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s32 (*write_reg)(struct e1000_hw *, u32, u16); |
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s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); |
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s32 (*write_reg_page)(struct e1000_hw *, u32, u16); |
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void (*power_up)(struct e1000_hw *); |
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void (*power_down)(struct e1000_hw *); |
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}; |
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/* Function pointers for the NVM. */ |
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struct e1000_nvm_operations { |
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s32 (*acquire)(struct e1000_hw *); |
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s32 (*read)(struct e1000_hw *, u16, u16, u16 *); |
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void (*release)(struct e1000_hw *); |
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void (*reload)(struct e1000_hw *); |
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s32 (*update)(struct e1000_hw *); |
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s32 (*valid_led_default)(struct e1000_hw *, u16 *); |
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s32 (*validate)(struct e1000_hw *); |
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s32 (*write)(struct e1000_hw *, u16, u16, u16 *); |
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}; |
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struct e1000_mac_info { |
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struct e1000_mac_operations ops; |
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u8 addr[ETH_ALEN]; |
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u8 perm_addr[ETH_ALEN]; |
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enum e1000_mac_type type; |
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|
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u32 collision_delta; |
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u32 ledctl_default; |
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u32 ledctl_mode1; |
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u32 ledctl_mode2; |
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u32 mc_filter_type; |
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u32 tx_packet_delta; |
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u32 txcw; |
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|
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u16 current_ifs_val; |
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u16 ifs_max_val; |
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u16 ifs_min_val; |
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u16 ifs_ratio; |
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u16 ifs_step_size; |
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u16 mta_reg_count; |
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|
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/* Maximum size of the MTA register table in all supported adapters */ |
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#define MAX_MTA_REG 128 |
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u32 mta_shadow[MAX_MTA_REG]; |
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u16 rar_entry_count; |
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|
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u8 forced_speed_duplex; |
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|
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bool adaptive_ifs; |
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bool has_fwsm; |
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bool arc_subsystem_valid; |
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bool autoneg; |
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bool autoneg_failed; |
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bool get_link_status; |
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bool in_ifs_mode; |
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bool serdes_has_link; |
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bool tx_pkt_filtering; |
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enum e1000_serdes_link_state serdes_link_state; |
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}; |
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|
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struct e1000_phy_info { |
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struct e1000_phy_operations ops; |
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|
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enum e1000_phy_type type; |
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|
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enum e1000_1000t_rx_status local_rx; |
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enum e1000_1000t_rx_status remote_rx; |
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enum e1000_ms_type ms_type; |
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enum e1000_ms_type original_ms_type; |
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enum e1000_rev_polarity cable_polarity; |
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enum e1000_smart_speed smart_speed; |
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|
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u32 addr; |
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u32 id; |
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u32 reset_delay_us; /* in usec */ |
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u32 revision; |
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|
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enum e1000_media_type media_type; |
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|
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u16 autoneg_advertised; |
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u16 autoneg_mask; |
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u16 cable_length; |
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u16 max_cable_length; |
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u16 min_cable_length; |
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|
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u8 mdix; |
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|
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bool disable_polarity_correction; |
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bool is_mdix; |
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bool polarity_correction; |
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bool speed_downgraded; |
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bool autoneg_wait_to_complete; |
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}; |
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|
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struct e1000_nvm_info { |
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struct e1000_nvm_operations ops; |
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|
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enum e1000_nvm_type type; |
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enum e1000_nvm_override override; |
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|
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u32 flash_bank_size; |
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u32 flash_base_addr; |
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|
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u16 word_size; |
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u16 delay_usec; |
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u16 address_bits; |
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u16 opcode_bits; |
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u16 page_size; |
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}; |
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|
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struct e1000_bus_info { |
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enum e1000_bus_width width; |
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|
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u16 func; |
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}; |
|
|
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struct e1000_fc_info { |
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u32 high_water; /* Flow control high-water mark */ |
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u32 low_water; /* Flow control low-water mark */ |
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u16 pause_time; /* Flow control pause timer */ |
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u16 refresh_time; /* Flow control refresh timer */ |
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bool send_xon; /* Flow control send XON */ |
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bool strict_ieee; /* Strict IEEE mode */ |
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enum e1000_fc_mode current_mode; /* FC mode in effect */ |
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enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ |
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}; |
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|
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struct e1000_dev_spec_82571 { |
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bool laa_is_present; |
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u32 smb_counter; |
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}; |
|
|
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struct e1000_dev_spec_80003es2lan { |
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bool mdic_wa_enable; |
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}; |
|
|
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struct e1000_shadow_ram { |
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u16 value; |
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bool modified; |
|
}; |
|
|
|
#define E1000_ICH8_SHADOW_RAM_WORDS 2048 |
|
|
|
/* I218 PHY Ultra Low Power (ULP) states */ |
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enum e1000_ulp_state { |
|
e1000_ulp_state_unknown, |
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e1000_ulp_state_off, |
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e1000_ulp_state_on, |
|
}; |
|
|
|
struct e1000_dev_spec_ich8lan { |
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bool kmrn_lock_loss_workaround_enabled; |
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struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS]; |
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bool nvm_k1_enabled; |
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bool eee_disable; |
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u16 eee_lp_ability; |
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enum e1000_ulp_state ulp_state; |
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}; |
|
|
|
struct e1000_hw { |
|
struct e1000_adapter *adapter; |
|
|
|
void __iomem *hw_addr; |
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void __iomem *flash_address; |
|
|
|
struct e1000_mac_info mac; |
|
struct e1000_fc_info fc; |
|
struct e1000_phy_info phy; |
|
struct e1000_nvm_info nvm; |
|
struct e1000_bus_info bus; |
|
struct e1000_host_mng_dhcp_cookie mng_cookie; |
|
|
|
union { |
|
struct e1000_dev_spec_82571 e82571; |
|
struct e1000_dev_spec_80003es2lan e80003es2lan; |
|
struct e1000_dev_spec_ich8lan ich8lan; |
|
} dev_spec; |
|
}; |
|
|
|
#include "82571.h" |
|
#include "80003es2lan.h" |
|
#include "ich8lan.h" |
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|
|
#endif
|
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