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591 lines
17 KiB
591 lines
17 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* Copyright(c) 1999 - 2018 Intel Corporation. */ |
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/* Linux PRO/1000 Ethernet Driver main header file */ |
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#ifndef _E1000_H_ |
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#define _E1000_H_ |
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#include <linux/bitops.h> |
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#include <linux/types.h> |
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#include <linux/timer.h> |
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#include <linux/workqueue.h> |
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#include <linux/io.h> |
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#include <linux/netdevice.h> |
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#include <linux/pci.h> |
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#include <linux/crc32.h> |
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#include <linux/if_vlan.h> |
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#include <linux/timecounter.h> |
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#include <linux/net_tstamp.h> |
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#include <linux/ptp_clock_kernel.h> |
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#include <linux/ptp_classify.h> |
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#include <linux/mii.h> |
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#include <linux/mdio.h> |
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#include <linux/pm_qos.h> |
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#include "hw.h" |
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struct e1000_info; |
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#define e_dbg(format, arg...) \ |
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netdev_dbg(hw->adapter->netdev, format, ## arg) |
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#define e_err(format, arg...) \ |
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netdev_err(adapter->netdev, format, ## arg) |
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#define e_info(format, arg...) \ |
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netdev_info(adapter->netdev, format, ## arg) |
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#define e_warn(format, arg...) \ |
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netdev_warn(adapter->netdev, format, ## arg) |
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#define e_notice(format, arg...) \ |
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netdev_notice(adapter->netdev, format, ## arg) |
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/* Interrupt modes, as used by the IntMode parameter */ |
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#define E1000E_INT_MODE_LEGACY 0 |
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#define E1000E_INT_MODE_MSI 1 |
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#define E1000E_INT_MODE_MSIX 2 |
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/* Tx/Rx descriptor defines */ |
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#define E1000_DEFAULT_TXD 256 |
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#define E1000_MAX_TXD 4096 |
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#define E1000_MIN_TXD 64 |
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#define E1000_DEFAULT_RXD 256 |
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#define E1000_MAX_RXD 4096 |
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#define E1000_MIN_RXD 64 |
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#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */ |
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#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */ |
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#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ |
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/* How many Tx Descriptors do we need to call netif_wake_queue ? */ |
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/* How many Rx Buffers do we bundle into one write to the hardware ? */ |
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#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ |
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#define AUTO_ALL_MODES 0 |
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#define E1000_EEPROM_APME 0x0400 |
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#define E1000_MNG_VLAN_NONE (-1) |
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#define DEFAULT_JUMBO 9234 |
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/* Time to wait before putting the device into D3 if there's no link (in ms). */ |
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#define LINK_TIMEOUT 100 |
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/* Count for polling __E1000_RESET condition every 10-20msec. |
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* Experimentation has shown the reset can take approximately 210msec. |
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*/ |
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#define E1000_CHECK_RESET_COUNT 25 |
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#define PCICFG_DESC_RING_STATUS 0xe4 |
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#define FLUSH_DESC_REQUIRED 0x100 |
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/* in the case of WTHRESH, it appears at least the 82571/2 hardware |
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* writes back 4 descriptors when WTHRESH=5, and 3 descriptors when |
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* WTHRESH=4, so a setting of 5 gives the most efficient bus |
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* utilization but to avoid possible Tx stalls, set it to 1 |
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*/ |
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#define E1000_TXDCTL_DMA_BURST_ENABLE \ |
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(E1000_TXDCTL_GRAN | /* set descriptor granularity */ \ |
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E1000_TXDCTL_COUNT_DESC | \ |
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(1u << 16) | /* wthresh must be +1 more than desired */\ |
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(1u << 8) | /* hthresh */ \ |
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0x1f) /* pthresh */ |
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#define E1000_RXDCTL_DMA_BURST_ENABLE \ |
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(0x01000000 | /* set descriptor granularity */ \ |
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(4u << 16) | /* set writeback threshold */ \ |
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(4u << 8) | /* set prefetch threshold */ \ |
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0x20) /* set hthresh */ |
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#define E1000_TIDV_FPD BIT(31) |
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#define E1000_RDTR_FPD BIT(31) |
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enum e1000_boards { |
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board_82571, |
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board_82572, |
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board_82573, |
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board_82574, |
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board_82583, |
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board_80003es2lan, |
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board_ich8lan, |
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board_ich9lan, |
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board_ich10lan, |
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board_pchlan, |
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board_pch2lan, |
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board_pch_lpt, |
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board_pch_spt, |
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board_pch_cnp |
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}; |
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struct e1000_ps_page { |
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struct page *page; |
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u64 dma; /* must be u64 - written to hw */ |
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}; |
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/* wrappers around a pointer to a socket buffer, |
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* so a DMA handle can be stored along with the buffer |
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*/ |
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struct e1000_buffer { |
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dma_addr_t dma; |
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struct sk_buff *skb; |
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union { |
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/* Tx */ |
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struct { |
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unsigned long time_stamp; |
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u16 length; |
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u16 next_to_watch; |
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unsigned int segs; |
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unsigned int bytecount; |
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u16 mapped_as_page; |
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}; |
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/* Rx */ |
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struct { |
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/* arrays of page information for packet split */ |
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struct e1000_ps_page *ps_pages; |
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struct page *page; |
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}; |
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}; |
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}; |
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struct e1000_ring { |
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struct e1000_adapter *adapter; /* back pointer to adapter */ |
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void *desc; /* pointer to ring memory */ |
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dma_addr_t dma; /* phys address of ring */ |
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unsigned int size; /* length of ring in bytes */ |
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unsigned int count; /* number of desc. in ring */ |
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u16 next_to_use; |
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u16 next_to_clean; |
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void __iomem *head; |
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void __iomem *tail; |
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/* array of buffer information structs */ |
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struct e1000_buffer *buffer_info; |
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char name[IFNAMSIZ + 5]; |
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u32 ims_val; |
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u32 itr_val; |
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void __iomem *itr_register; |
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int set_itr; |
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struct sk_buff *rx_skb_top; |
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}; |
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/* PHY register snapshot values */ |
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struct e1000_phy_regs { |
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u16 bmcr; /* basic mode control register */ |
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u16 bmsr; /* basic mode status register */ |
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u16 advertise; /* auto-negotiation advertisement */ |
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u16 lpa; /* link partner ability register */ |
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u16 expansion; /* auto-negotiation expansion reg */ |
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u16 ctrl1000; /* 1000BASE-T control register */ |
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u16 stat1000; /* 1000BASE-T status register */ |
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u16 estatus; /* extended status register */ |
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}; |
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/* board specific private data structure */ |
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struct e1000_adapter { |
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struct timer_list watchdog_timer; |
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struct timer_list phy_info_timer; |
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struct timer_list blink_timer; |
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struct work_struct reset_task; |
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struct work_struct watchdog_task; |
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const struct e1000_info *ei; |
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unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
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u32 bd_number; |
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u32 rx_buffer_len; |
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u16 mng_vlan_id; |
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u16 link_speed; |
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u16 link_duplex; |
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u16 eeprom_vers; |
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/* track device up/down/testing state */ |
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unsigned long state; |
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/* Interrupt Throttle Rate */ |
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u32 itr; |
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u32 itr_setting; |
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u16 tx_itr; |
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u16 rx_itr; |
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/* Tx - one ring per active queue */ |
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struct e1000_ring *tx_ring ____cacheline_aligned_in_smp; |
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u32 tx_fifo_limit; |
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struct napi_struct napi; |
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unsigned int uncorr_errors; /* uncorrectable ECC errors */ |
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unsigned int corr_errors; /* correctable ECC errors */ |
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unsigned int restart_queue; |
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u32 txd_cmd; |
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bool detect_tx_hung; |
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bool tx_hang_recheck; |
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u8 tx_timeout_factor; |
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u32 tx_int_delay; |
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u32 tx_abs_int_delay; |
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unsigned int total_tx_bytes; |
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unsigned int total_tx_packets; |
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unsigned int total_rx_bytes; |
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unsigned int total_rx_packets; |
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/* Tx stats */ |
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u64 tpt_old; |
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u64 colc_old; |
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u32 gotc; |
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u64 gotc_old; |
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u32 tx_timeout_count; |
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u32 tx_fifo_head; |
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u32 tx_head_addr; |
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u32 tx_fifo_size; |
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u32 tx_dma_failed; |
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u32 tx_hwtstamp_timeouts; |
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u32 tx_hwtstamp_skipped; |
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/* Rx */ |
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bool (*clean_rx)(struct e1000_ring *ring, int *work_done, |
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int work_to_do) ____cacheline_aligned_in_smp; |
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void (*alloc_rx_buf)(struct e1000_ring *ring, int cleaned_count, |
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gfp_t gfp); |
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struct e1000_ring *rx_ring; |
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u32 rx_int_delay; |
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u32 rx_abs_int_delay; |
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/* Rx stats */ |
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u64 hw_csum_err; |
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u64 hw_csum_good; |
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u64 rx_hdr_split; |
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u32 gorc; |
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u64 gorc_old; |
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u32 alloc_rx_buff_failed; |
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u32 rx_dma_failed; |
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u32 rx_hwtstamp_cleared; |
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unsigned int rx_ps_pages; |
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u16 rx_ps_bsize0; |
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u32 max_frame_size; |
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u32 min_frame_size; |
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/* OS defined structs */ |
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struct net_device *netdev; |
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struct pci_dev *pdev; |
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/* structs defined in e1000_hw.h */ |
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struct e1000_hw hw; |
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spinlock_t stats64_lock; /* protects statistics counters */ |
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struct e1000_hw_stats stats; |
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struct e1000_phy_info phy_info; |
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struct e1000_phy_stats phy_stats; |
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/* Snapshot of PHY registers */ |
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struct e1000_phy_regs phy_regs; |
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struct e1000_ring test_tx_ring; |
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struct e1000_ring test_rx_ring; |
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u32 test_icr; |
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u32 msg_enable; |
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unsigned int num_vectors; |
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struct msix_entry *msix_entries; |
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int int_mode; |
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u32 eiac_mask; |
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u32 eeprom_wol; |
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u32 wol; |
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u32 pba; |
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u32 max_hw_frame_size; |
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bool fc_autoneg; |
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unsigned int flags; |
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unsigned int flags2; |
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struct work_struct downshift_task; |
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struct work_struct update_phy_task; |
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struct work_struct print_hang_task; |
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int phy_hang_count; |
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u16 tx_ring_count; |
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u16 rx_ring_count; |
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struct hwtstamp_config hwtstamp_config; |
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struct delayed_work systim_overflow_work; |
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struct sk_buff *tx_hwtstamp_skb; |
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unsigned long tx_hwtstamp_start; |
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struct work_struct tx_hwtstamp_work; |
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spinlock_t systim_lock; /* protects SYSTIML/H regsters */ |
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struct cyclecounter cc; |
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struct timecounter tc; |
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struct ptp_clock *ptp_clock; |
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struct ptp_clock_info ptp_clock_info; |
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struct pm_qos_request pm_qos_req; |
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s32 ptp_delta; |
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u16 eee_advert; |
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}; |
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struct e1000_info { |
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enum e1000_mac_type mac; |
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unsigned int flags; |
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unsigned int flags2; |
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u32 pba; |
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u32 max_hw_frame_size; |
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s32 (*get_variants)(struct e1000_adapter *); |
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const struct e1000_mac_operations *mac_ops; |
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const struct e1000_phy_operations *phy_ops; |
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const struct e1000_nvm_operations *nvm_ops; |
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}; |
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s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca); |
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/* The system time is maintained by a 64-bit counter comprised of the 32-bit |
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* SYSTIMH and SYSTIML registers. How the counter increments (and therefore |
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* its resolution) is based on the contents of the TIMINCA register - it |
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* increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0). |
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* For the best accuracy, the incperiod should be as small as possible. The |
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* incvalue is scaled by a factor as large as possible (while still fitting |
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* in bits 23:0) so that relatively small clock corrections can be made. |
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* |
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* As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of |
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* INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n) |
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* bits to count nanoseconds leaving the rest for fractional nonseconds. |
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*/ |
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#define INCVALUE_96MHZ 125 |
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#define INCVALUE_SHIFT_96MHZ 17 |
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#define INCPERIOD_SHIFT_96MHZ 2 |
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#define INCPERIOD_96MHZ (12 >> INCPERIOD_SHIFT_96MHZ) |
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#define INCVALUE_25MHZ 40 |
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#define INCVALUE_SHIFT_25MHZ 18 |
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#define INCPERIOD_25MHZ 1 |
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#define INCVALUE_24MHZ 125 |
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#define INCVALUE_SHIFT_24MHZ 14 |
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#define INCPERIOD_24MHZ 3 |
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#define INCVALUE_38400KHZ 26 |
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#define INCVALUE_SHIFT_38400KHZ 19 |
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#define INCPERIOD_38400KHZ 1 |
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/* Another drawback of scaling the incvalue by a large factor is the |
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* 64-bit SYSTIM register overflows more quickly. This is dealt with |
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* by simply reading the clock before it overflows. |
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* |
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* Clock ns bits Overflows after |
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* ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~ |
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* 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs |
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* 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours |
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*/ |
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#define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4) |
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#define E1000_MAX_82574_SYSTIM_REREADS 50 |
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#define E1000_82574_SYSTIM_EPSILON (1ULL << 35ULL) |
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/* hardware capability, feature, and workaround flags */ |
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#define FLAG_HAS_AMT BIT(0) |
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#define FLAG_HAS_FLASH BIT(1) |
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#define FLAG_HAS_HW_VLAN_FILTER BIT(2) |
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#define FLAG_HAS_WOL BIT(3) |
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/* reserved BIT(4) */ |
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#define FLAG_HAS_CTRLEXT_ON_LOAD BIT(5) |
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#define FLAG_HAS_SWSM_ON_LOAD BIT(6) |
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#define FLAG_HAS_JUMBO_FRAMES BIT(7) |
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#define FLAG_READ_ONLY_NVM BIT(8) |
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#define FLAG_IS_ICH BIT(9) |
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#define FLAG_HAS_MSIX BIT(10) |
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#define FLAG_HAS_SMART_POWER_DOWN BIT(11) |
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#define FLAG_IS_QUAD_PORT_A BIT(12) |
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#define FLAG_IS_QUAD_PORT BIT(13) |
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#define FLAG_HAS_HW_TIMESTAMP BIT(14) |
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#define FLAG_APME_IN_WUC BIT(15) |
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#define FLAG_APME_IN_CTRL3 BIT(16) |
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#define FLAG_APME_CHECK_PORT_B BIT(17) |
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#define FLAG_DISABLE_FC_PAUSE_TIME BIT(18) |
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#define FLAG_NO_WAKE_UCAST BIT(19) |
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#define FLAG_MNG_PT_ENABLED BIT(20) |
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#define FLAG_RESET_OVERWRITES_LAA BIT(21) |
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#define FLAG_TARC_SPEED_MODE_BIT BIT(22) |
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#define FLAG_TARC_SET_BIT_ZERO BIT(23) |
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#define FLAG_RX_NEEDS_RESTART BIT(24) |
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#define FLAG_LSC_GIG_SPEED_DROP BIT(25) |
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#define FLAG_SMART_POWER_DOWN BIT(26) |
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#define FLAG_MSI_ENABLED BIT(27) |
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/* reserved BIT(28) */ |
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#define FLAG_TSO_FORCE BIT(29) |
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#define FLAG_RESTART_NOW BIT(30) |
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#define FLAG_MSI_TEST_FAILED BIT(31) |
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#define FLAG2_CRC_STRIPPING BIT(0) |
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#define FLAG2_HAS_PHY_WAKEUP BIT(1) |
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#define FLAG2_IS_DISCARDING BIT(2) |
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#define FLAG2_DISABLE_ASPM_L1 BIT(3) |
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#define FLAG2_HAS_PHY_STATS BIT(4) |
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#define FLAG2_HAS_EEE BIT(5) |
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#define FLAG2_DMA_BURST BIT(6) |
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#define FLAG2_DISABLE_ASPM_L0S BIT(7) |
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#define FLAG2_DISABLE_AIM BIT(8) |
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#define FLAG2_CHECK_PHY_HANG BIT(9) |
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#define FLAG2_NO_DISABLE_RX BIT(10) |
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#define FLAG2_PCIM2PCI_ARBITER_WA BIT(11) |
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#define FLAG2_DFLT_CRC_STRIPPING BIT(12) |
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#define FLAG2_CHECK_RX_HWTSTAMP BIT(13) |
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#define FLAG2_CHECK_SYSTIM_OVERFLOW BIT(14) |
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#define FLAG2_ENABLE_S0IX_FLOWS BIT(15) |
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#define E1000_RX_DESC_PS(R, i) \ |
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(&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) |
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#define E1000_RX_DESC_EXT(R, i) \ |
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(&(((union e1000_rx_desc_extended *)((R).desc))[i])) |
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#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) |
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#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) |
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#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc) |
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enum e1000_state_t { |
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__E1000_TESTING, |
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__E1000_RESETTING, |
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__E1000_ACCESS_SHARED_RESOURCE, |
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__E1000_DOWN |
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}; |
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enum latency_range { |
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lowest_latency = 0, |
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low_latency = 1, |
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bulk_latency = 2, |
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latency_invalid = 255 |
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}; |
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extern char e1000e_driver_name[]; |
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void e1000e_check_options(struct e1000_adapter *adapter); |
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void e1000e_set_ethtool_ops(struct net_device *netdev); |
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int e1000e_open(struct net_device *netdev); |
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int e1000e_close(struct net_device *netdev); |
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void e1000e_up(struct e1000_adapter *adapter); |
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void e1000e_down(struct e1000_adapter *adapter, bool reset); |
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void e1000e_reinit_locked(struct e1000_adapter *adapter); |
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void e1000e_reset(struct e1000_adapter *adapter); |
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void e1000e_power_up_phy(struct e1000_adapter *adapter); |
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int e1000e_setup_rx_resources(struct e1000_ring *ring); |
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int e1000e_setup_tx_resources(struct e1000_ring *ring); |
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void e1000e_free_rx_resources(struct e1000_ring *ring); |
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void e1000e_free_tx_resources(struct e1000_ring *ring); |
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void e1000e_get_stats64(struct net_device *netdev, |
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struct rtnl_link_stats64 *stats); |
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void e1000e_set_interrupt_capability(struct e1000_adapter *adapter); |
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void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter); |
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void e1000e_get_hw_control(struct e1000_adapter *adapter); |
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void e1000e_release_hw_control(struct e1000_adapter *adapter); |
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void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr); |
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extern unsigned int copybreak; |
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extern const struct e1000_info e1000_82571_info; |
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extern const struct e1000_info e1000_82572_info; |
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extern const struct e1000_info e1000_82573_info; |
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extern const struct e1000_info e1000_82574_info; |
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extern const struct e1000_info e1000_82583_info; |
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extern const struct e1000_info e1000_ich8_info; |
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extern const struct e1000_info e1000_ich9_info; |
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extern const struct e1000_info e1000_ich10_info; |
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extern const struct e1000_info e1000_pch_info; |
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extern const struct e1000_info e1000_pch2_info; |
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extern const struct e1000_info e1000_pch_lpt_info; |
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extern const struct e1000_info e1000_pch_spt_info; |
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extern const struct e1000_info e1000_pch_cnp_info; |
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extern const struct e1000_info e1000_es2_info; |
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void e1000e_ptp_init(struct e1000_adapter *adapter); |
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void e1000e_ptp_remove(struct e1000_adapter *adapter); |
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u64 e1000e_read_systim(struct e1000_adapter *adapter, |
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struct ptp_system_timestamp *sts); |
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static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) |
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{ |
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return hw->phy.ops.reset(hw); |
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} |
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static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data) |
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{ |
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return hw->phy.ops.read_reg(hw, offset, data); |
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} |
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static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
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{ |
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return hw->phy.ops.read_reg_locked(hw, offset, data); |
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} |
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static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data) |
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{ |
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return hw->phy.ops.write_reg(hw, offset, data); |
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} |
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static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data) |
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{ |
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return hw->phy.ops.write_reg_locked(hw, offset, data); |
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} |
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void e1000e_reload_nvm_generic(struct e1000_hw *hw); |
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static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw) |
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{ |
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if (hw->mac.ops.read_mac_addr) |
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return hw->mac.ops.read_mac_addr(hw); |
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return e1000_read_mac_addr_generic(hw); |
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} |
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static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw) |
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{ |
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return hw->nvm.ops.validate(hw); |
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} |
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static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw) |
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{ |
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return hw->nvm.ops.update(hw); |
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} |
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static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, |
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u16 *data) |
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{ |
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return hw->nvm.ops.read(hw, offset, words, data); |
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} |
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static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, |
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u16 *data) |
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{ |
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return hw->nvm.ops.write(hw, offset, words, data); |
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} |
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static inline s32 e1000_get_phy_info(struct e1000_hw *hw) |
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{ |
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return hw->phy.ops.get_info(hw); |
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} |
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static inline u32 __er32(struct e1000_hw *hw, unsigned long reg) |
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{ |
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return readl(hw->hw_addr + reg); |
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} |
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#define er32(reg) __er32(hw, E1000_##reg) |
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void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val); |
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#define ew32(reg, val) __ew32(hw, E1000_##reg, (val)) |
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#define e1e_flush() er32(STATUS) |
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#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ |
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(__ew32((a), (reg + ((offset) << 2)), (value))) |
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#define E1000_READ_REG_ARRAY(a, reg, offset) \ |
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(readl((a)->hw_addr + reg + ((offset) << 2))) |
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#endif /* _E1000_H_ */
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