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574 lines
14 KiB
574 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (c) 2014-2015 Hisilicon Limited. |
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*/ |
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|
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#include <linux/acpi.h> |
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#include <linux/errno.h> |
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#include <linux/etherdevice.h> |
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#include <linux/init.h> |
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#include <linux/kernel.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/module.h> |
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#include <linux/mutex.h> |
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#include <linux/netdevice.h> |
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#include <linux/of_address.h> |
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#include <linux/of.h> |
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#include <linux/of_mdio.h> |
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#include <linux/of_platform.h> |
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#include <linux/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#define MDIO_DRV_NAME "Hi-HNS_MDIO" |
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#define MDIO_BUS_NAME "Hisilicon MII Bus" |
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#define MDIO_TIMEOUT 1000000 |
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struct hns_mdio_sc_reg { |
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u16 mdio_clk_en; |
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u16 mdio_clk_dis; |
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u16 mdio_reset_req; |
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u16 mdio_reset_dreq; |
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u16 mdio_clk_st; |
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u16 mdio_reset_st; |
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}; |
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struct hns_mdio_device { |
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u8 __iomem *vbase; /* mdio reg base address */ |
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struct regmap *subctrl_vbase; |
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struct hns_mdio_sc_reg sc_reg; |
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}; |
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/* mdio reg */ |
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#define MDIO_COMMAND_REG 0x0 |
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#define MDIO_ADDR_REG 0x4 |
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#define MDIO_WDATA_REG 0x8 |
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#define MDIO_RDATA_REG 0xc |
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#define MDIO_STA_REG 0x10 |
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/* cfg phy bit map */ |
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#define MDIO_CMD_DEVAD_M 0x1f |
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#define MDIO_CMD_DEVAD_S 0 |
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#define MDIO_CMD_PRTAD_M 0x1f |
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#define MDIO_CMD_PRTAD_S 5 |
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#define MDIO_CMD_OP_S 10 |
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#define MDIO_CMD_ST_S 12 |
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#define MDIO_CMD_START_B 14 |
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#define MDIO_ADDR_DATA_M 0xffff |
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#define MDIO_ADDR_DATA_S 0 |
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#define MDIO_WDATA_DATA_M 0xffff |
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#define MDIO_WDATA_DATA_S 0 |
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#define MDIO_RDATA_DATA_M 0xffff |
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#define MDIO_RDATA_DATA_S 0 |
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#define MDIO_STATE_STA_B 0 |
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enum mdio_st_clause { |
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MDIO_ST_CLAUSE_45 = 0, |
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MDIO_ST_CLAUSE_22 |
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}; |
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enum mdio_c22_op_seq { |
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MDIO_C22_WRITE = 1, |
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MDIO_C22_READ = 2 |
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}; |
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enum mdio_c45_op_seq { |
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MDIO_C45_WRITE_ADDR = 0, |
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MDIO_C45_WRITE_DATA, |
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MDIO_C45_READ_INCREMENT, |
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MDIO_C45_READ |
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}; |
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/* peri subctrl reg */ |
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#define MDIO_SC_CLK_EN 0x338 |
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#define MDIO_SC_CLK_DIS 0x33C |
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#define MDIO_SC_RESET_REQ 0xA38 |
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#define MDIO_SC_RESET_DREQ 0xA3C |
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#define MDIO_SC_CLK_ST 0x531C |
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#define MDIO_SC_RESET_ST 0x5A1C |
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static void mdio_write_reg(u8 __iomem *base, u32 reg, u32 value) |
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{ |
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writel_relaxed(value, base + reg); |
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} |
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#define MDIO_WRITE_REG(a, reg, value) \ |
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mdio_write_reg((a)->vbase, (reg), (value)) |
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static u32 mdio_read_reg(u8 __iomem *base, u32 reg) |
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{ |
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return readl_relaxed(base + reg); |
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} |
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#define mdio_set_field(origin, mask, shift, val) \ |
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do { \ |
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(origin) &= (~((mask) << (shift))); \ |
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(origin) |= (((val) & (mask)) << (shift)); \ |
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} while (0) |
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#define mdio_get_field(origin, mask, shift) (((origin) >> (shift)) & (mask)) |
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static void mdio_set_reg_field(u8 __iomem *base, u32 reg, u32 mask, u32 shift, |
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u32 val) |
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{ |
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u32 origin = mdio_read_reg(base, reg); |
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mdio_set_field(origin, mask, shift, val); |
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mdio_write_reg(base, reg, origin); |
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} |
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#define MDIO_SET_REG_FIELD(dev, reg, mask, shift, val) \ |
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mdio_set_reg_field((dev)->vbase, (reg), (mask), (shift), (val)) |
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static u32 mdio_get_reg_field(u8 __iomem *base, u32 reg, u32 mask, u32 shift) |
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{ |
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u32 origin; |
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origin = mdio_read_reg(base, reg); |
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return mdio_get_field(origin, mask, shift); |
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} |
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#define MDIO_GET_REG_FIELD(dev, reg, mask, shift) \ |
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mdio_get_reg_field((dev)->vbase, (reg), (mask), (shift)) |
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#define MDIO_GET_REG_BIT(dev, reg, bit) \ |
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mdio_get_reg_field((dev)->vbase, (reg), 0x1ull, (bit)) |
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#define MDIO_CHECK_SET_ST 1 |
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#define MDIO_CHECK_CLR_ST 0 |
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static int mdio_sc_cfg_reg_write(struct hns_mdio_device *mdio_dev, |
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u32 cfg_reg, u32 set_val, |
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u32 st_reg, u32 st_msk, u8 check_st) |
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{ |
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u32 time_cnt; |
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u32 reg_value; |
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int ret; |
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regmap_write(mdio_dev->subctrl_vbase, cfg_reg, set_val); |
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for (time_cnt = MDIO_TIMEOUT; time_cnt; time_cnt--) { |
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ret = regmap_read(mdio_dev->subctrl_vbase, st_reg, ®_value); |
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if (ret) |
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return ret; |
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reg_value &= st_msk; |
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if ((!!check_st) == (!!reg_value)) |
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break; |
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} |
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if ((!!check_st) != (!!reg_value)) |
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return -EBUSY; |
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return 0; |
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} |
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static int hns_mdio_wait_ready(struct mii_bus *bus) |
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{ |
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struct hns_mdio_device *mdio_dev = bus->priv; |
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u32 cmd_reg_value; |
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int i; |
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/* waitting for MDIO_COMMAND_REG 's mdio_start==0 */ |
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/* after that can do read or write*/ |
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for (i = 0; i < MDIO_TIMEOUT; i++) { |
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cmd_reg_value = MDIO_GET_REG_BIT(mdio_dev, |
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MDIO_COMMAND_REG, |
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MDIO_CMD_START_B); |
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if (!cmd_reg_value) |
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break; |
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} |
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if ((i == MDIO_TIMEOUT) && cmd_reg_value) |
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return -ETIMEDOUT; |
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return 0; |
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} |
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static void hns_mdio_cmd_write(struct hns_mdio_device *mdio_dev, |
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u8 is_c45, u8 op, u8 phy_id, u16 cmd) |
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{ |
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u32 cmd_reg_value; |
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u8 st = is_c45 ? MDIO_ST_CLAUSE_45 : MDIO_ST_CLAUSE_22; |
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cmd_reg_value = st << MDIO_CMD_ST_S; |
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cmd_reg_value |= op << MDIO_CMD_OP_S; |
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cmd_reg_value |= |
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(phy_id & MDIO_CMD_PRTAD_M) << MDIO_CMD_PRTAD_S; |
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cmd_reg_value |= (cmd & MDIO_CMD_DEVAD_M) << MDIO_CMD_DEVAD_S; |
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cmd_reg_value |= 1 << MDIO_CMD_START_B; |
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MDIO_WRITE_REG(mdio_dev, MDIO_COMMAND_REG, cmd_reg_value); |
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} |
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/** |
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* hns_mdio_write - access phy register |
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* @bus: mdio bus |
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* @phy_id: phy id |
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* @regnum: register num |
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* @data: register value |
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* |
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* Return 0 on success, negative on failure |
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*/ |
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static int hns_mdio_write(struct mii_bus *bus, |
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int phy_id, int regnum, u16 data) |
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{ |
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int ret; |
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struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv; |
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u8 devad = ((regnum >> 16) & 0x1f); |
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u8 is_c45 = !!(regnum & MII_ADDR_C45); |
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u16 reg = (u16)(regnum & 0xffff); |
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u8 op; |
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u16 cmd_reg_cfg; |
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dev_dbg(&bus->dev, "mdio write %s,base is %p\n", |
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bus->id, mdio_dev->vbase); |
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dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x, write data=%d\n", |
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phy_id, is_c45, devad, reg, data); |
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/* wait for ready */ |
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ret = hns_mdio_wait_ready(bus); |
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if (ret) { |
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dev_err(&bus->dev, "MDIO bus is busy\n"); |
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return ret; |
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} |
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if (!is_c45) { |
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cmd_reg_cfg = reg; |
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op = MDIO_C22_WRITE; |
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} else { |
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/* config the cmd-reg to write addr*/ |
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MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M, |
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MDIO_ADDR_DATA_S, reg); |
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hns_mdio_cmd_write(mdio_dev, is_c45, |
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MDIO_C45_WRITE_ADDR, phy_id, devad); |
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/* check for read or write opt is finished */ |
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ret = hns_mdio_wait_ready(bus); |
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if (ret) { |
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dev_err(&bus->dev, "MDIO bus is busy\n"); |
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return ret; |
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} |
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/* config the data needed writing */ |
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cmd_reg_cfg = devad; |
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op = MDIO_C45_WRITE_DATA; |
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} |
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MDIO_SET_REG_FIELD(mdio_dev, MDIO_WDATA_REG, MDIO_WDATA_DATA_M, |
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MDIO_WDATA_DATA_S, data); |
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hns_mdio_cmd_write(mdio_dev, is_c45, op, phy_id, cmd_reg_cfg); |
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return 0; |
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} |
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/** |
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* hns_mdio_read - access phy register |
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* @bus: mdio bus |
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* @phy_id: phy id |
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* @regnum: register num |
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* |
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* Return phy register value |
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*/ |
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static int hns_mdio_read(struct mii_bus *bus, int phy_id, int regnum) |
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{ |
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int ret; |
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u16 reg_val = 0; |
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u8 devad = ((regnum >> 16) & 0x1f); |
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u8 is_c45 = !!(regnum & MII_ADDR_C45); |
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u16 reg = (u16)(regnum & 0xffff); |
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struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv; |
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dev_dbg(&bus->dev, "mdio read %s,base is %p\n", |
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bus->id, mdio_dev->vbase); |
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dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x!\n", |
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phy_id, is_c45, devad, reg); |
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/* Step 1: wait for ready */ |
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ret = hns_mdio_wait_ready(bus); |
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if (ret) { |
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dev_err(&bus->dev, "MDIO bus is busy\n"); |
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return ret; |
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} |
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if (!is_c45) { |
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hns_mdio_cmd_write(mdio_dev, is_c45, |
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MDIO_C22_READ, phy_id, reg); |
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} else { |
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MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M, |
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MDIO_ADDR_DATA_S, reg); |
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/* Step 2; config the cmd-reg to write addr*/ |
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hns_mdio_cmd_write(mdio_dev, is_c45, |
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MDIO_C45_WRITE_ADDR, phy_id, devad); |
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/* Step 3: check for read or write opt is finished */ |
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ret = hns_mdio_wait_ready(bus); |
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if (ret) { |
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dev_err(&bus->dev, "MDIO bus is busy\n"); |
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return ret; |
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} |
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hns_mdio_cmd_write(mdio_dev, is_c45, |
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MDIO_C45_READ, phy_id, devad); |
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} |
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/* Step 5: waitting for MDIO_COMMAND_REG 's mdio_start==0,*/ |
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/* check for read or write opt is finished */ |
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ret = hns_mdio_wait_ready(bus); |
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if (ret) { |
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dev_err(&bus->dev, "MDIO bus is busy\n"); |
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return ret; |
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} |
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reg_val = MDIO_GET_REG_BIT(mdio_dev, MDIO_STA_REG, MDIO_STATE_STA_B); |
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if (reg_val) { |
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dev_err(&bus->dev, " ERROR! MDIO Read failed!\n"); |
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return -EBUSY; |
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} |
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/* Step 6; get out data*/ |
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reg_val = (u16)MDIO_GET_REG_FIELD(mdio_dev, MDIO_RDATA_REG, |
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MDIO_RDATA_DATA_M, MDIO_RDATA_DATA_S); |
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return reg_val; |
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} |
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/** |
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* hns_mdio_reset - reset mdio bus |
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* @bus: mdio bus |
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* |
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* Return 0 on success, negative on failure |
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*/ |
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static int hns_mdio_reset(struct mii_bus *bus) |
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{ |
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struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv; |
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const struct hns_mdio_sc_reg *sc_reg; |
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int ret; |
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if (dev_of_node(bus->parent)) { |
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if (!mdio_dev->subctrl_vbase) { |
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dev_err(&bus->dev, "mdio sys ctl reg has not maped\n"); |
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return -ENODEV; |
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} |
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sc_reg = &mdio_dev->sc_reg; |
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/* 1. reset req, and read reset st check */ |
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ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_req, |
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0x1, sc_reg->mdio_reset_st, 0x1, |
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MDIO_CHECK_SET_ST); |
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if (ret) { |
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dev_err(&bus->dev, "MDIO reset fail\n"); |
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return ret; |
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} |
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/* 2. dis clk, and read clk st check */ |
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ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_dis, |
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0x1, sc_reg->mdio_clk_st, 0x1, |
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MDIO_CHECK_CLR_ST); |
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if (ret) { |
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dev_err(&bus->dev, "MDIO dis clk fail\n"); |
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return ret; |
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} |
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/* 3. reset dreq, and read reset st check */ |
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ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_dreq, |
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0x1, sc_reg->mdio_reset_st, 0x1, |
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MDIO_CHECK_CLR_ST); |
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if (ret) { |
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dev_err(&bus->dev, "MDIO dis clk fail\n"); |
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return ret; |
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} |
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/* 4. en clk, and read clk st check */ |
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ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_en, |
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0x1, sc_reg->mdio_clk_st, 0x1, |
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MDIO_CHECK_SET_ST); |
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if (ret) |
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dev_err(&bus->dev, "MDIO en clk fail\n"); |
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} else if (is_acpi_node(bus->parent->fwnode)) { |
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acpi_status s; |
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s = acpi_evaluate_object(ACPI_HANDLE(bus->parent), |
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"_RST", NULL, NULL); |
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if (ACPI_FAILURE(s)) { |
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dev_err(&bus->dev, "Reset failed, return:%#x\n", s); |
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ret = -EBUSY; |
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} else { |
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ret = 0; |
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} |
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} else { |
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dev_err(&bus->dev, "Can not get cfg data from DT or ACPI\n"); |
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ret = -ENXIO; |
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} |
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return ret; |
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} |
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/** |
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* hns_mdio_probe - probe mdio device |
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* @pdev: mdio platform device |
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* |
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* Return 0 on success, negative on failure |
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*/ |
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static int hns_mdio_probe(struct platform_device *pdev) |
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{ |
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struct hns_mdio_device *mdio_dev; |
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struct mii_bus *new_bus; |
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int ret = -ENODEV; |
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if (!pdev) { |
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dev_err(NULL, "pdev is NULL!\r\n"); |
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return -ENODEV; |
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} |
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mdio_dev = devm_kzalloc(&pdev->dev, sizeof(*mdio_dev), GFP_KERNEL); |
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if (!mdio_dev) |
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return -ENOMEM; |
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new_bus = devm_mdiobus_alloc(&pdev->dev); |
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if (!new_bus) { |
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dev_err(&pdev->dev, "mdiobus_alloc fail!\n"); |
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return -ENOMEM; |
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} |
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new_bus->name = MDIO_BUS_NAME; |
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new_bus->read = hns_mdio_read; |
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new_bus->write = hns_mdio_write; |
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new_bus->reset = hns_mdio_reset; |
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new_bus->priv = mdio_dev; |
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new_bus->parent = &pdev->dev; |
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mdio_dev->vbase = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(mdio_dev->vbase)) { |
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ret = PTR_ERR(mdio_dev->vbase); |
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return ret; |
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} |
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platform_set_drvdata(pdev, new_bus); |
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snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%s", "Mii", |
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dev_name(&pdev->dev)); |
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if (dev_of_node(&pdev->dev)) { |
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struct of_phandle_args reg_args; |
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ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, |
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"subctrl-vbase", |
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4, |
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0, |
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®_args); |
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if (!ret) { |
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mdio_dev->subctrl_vbase = |
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syscon_node_to_regmap(reg_args.np); |
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if (IS_ERR(mdio_dev->subctrl_vbase)) { |
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dev_warn(&pdev->dev, "syscon_node_to_regmap error\n"); |
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mdio_dev->subctrl_vbase = NULL; |
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} else { |
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if (reg_args.args_count == 4) { |
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mdio_dev->sc_reg.mdio_clk_en = |
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(u16)reg_args.args[0]; |
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mdio_dev->sc_reg.mdio_clk_dis = |
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(u16)reg_args.args[0] + 4; |
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mdio_dev->sc_reg.mdio_reset_req = |
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(u16)reg_args.args[1]; |
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mdio_dev->sc_reg.mdio_reset_dreq = |
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(u16)reg_args.args[1] + 4; |
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mdio_dev->sc_reg.mdio_clk_st = |
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(u16)reg_args.args[2]; |
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mdio_dev->sc_reg.mdio_reset_st = |
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(u16)reg_args.args[3]; |
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} else { |
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/* for compatible */ |
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mdio_dev->sc_reg.mdio_clk_en = |
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MDIO_SC_CLK_EN; |
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mdio_dev->sc_reg.mdio_clk_dis = |
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MDIO_SC_CLK_DIS; |
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mdio_dev->sc_reg.mdio_reset_req = |
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MDIO_SC_RESET_REQ; |
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mdio_dev->sc_reg.mdio_reset_dreq = |
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MDIO_SC_RESET_DREQ; |
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mdio_dev->sc_reg.mdio_clk_st = |
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MDIO_SC_CLK_ST; |
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mdio_dev->sc_reg.mdio_reset_st = |
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MDIO_SC_RESET_ST; |
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} |
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} |
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} else { |
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dev_warn(&pdev->dev, "find syscon ret = %#x\n", ret); |
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mdio_dev->subctrl_vbase = NULL; |
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} |
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ret = of_mdiobus_register(new_bus, pdev->dev.of_node); |
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} else if (is_acpi_node(pdev->dev.fwnode)) { |
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/* Clear all the IRQ properties */ |
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memset(new_bus->irq, PHY_POLL, 4 * PHY_MAX_ADDR); |
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|
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/* Mask out all PHYs from auto probing. */ |
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new_bus->phy_mask = ~0; |
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/* Register the MDIO bus */ |
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ret = mdiobus_register(new_bus); |
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} else { |
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dev_err(&pdev->dev, "Can not get cfg data from DT or ACPI\n"); |
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ret = -ENXIO; |
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} |
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if (ret) { |
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dev_err(&pdev->dev, "Cannot register as MDIO bus!\n"); |
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platform_set_drvdata(pdev, NULL); |
|
return ret; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* hns_mdio_remove - remove mdio device |
|
* @pdev: mdio platform device |
|
* |
|
* Return 0 on success, negative on failure |
|
*/ |
|
static int hns_mdio_remove(struct platform_device *pdev) |
|
{ |
|
struct mii_bus *bus; |
|
|
|
bus = platform_get_drvdata(pdev); |
|
|
|
mdiobus_unregister(bus); |
|
platform_set_drvdata(pdev, NULL); |
|
return 0; |
|
} |
|
|
|
static const struct of_device_id hns_mdio_match[] = { |
|
{.compatible = "hisilicon,mdio"}, |
|
{.compatible = "hisilicon,hns-mdio"}, |
|
{} |
|
}; |
|
MODULE_DEVICE_TABLE(of, hns_mdio_match); |
|
|
|
static const struct acpi_device_id hns_mdio_acpi_match[] = { |
|
{ "HISI0141", 0 }, |
|
{ }, |
|
}; |
|
MODULE_DEVICE_TABLE(acpi, hns_mdio_acpi_match); |
|
|
|
static struct platform_driver hns_mdio_driver = { |
|
.probe = hns_mdio_probe, |
|
.remove = hns_mdio_remove, |
|
.driver = { |
|
.name = MDIO_DRV_NAME, |
|
.of_match_table = hns_mdio_match, |
|
.acpi_match_table = ACPI_PTR(hns_mdio_acpi_match), |
|
}, |
|
}; |
|
|
|
module_platform_driver(hns_mdio_driver); |
|
|
|
MODULE_LICENSE("GPL"); |
|
MODULE_AUTHOR("Huawei Tech. Co., Ltd."); |
|
MODULE_DESCRIPTION("Hisilicon HNS MDIO driver"); |
|
MODULE_ALIAS("platform:" MDIO_DRV_NAME);
|
|
|