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1962 lines
54 KiB
1962 lines
54 KiB
/* |
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Written 1998-2000 by Donald Becker. |
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This software may be used and distributed according to the terms of |
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the GNU General Public License (GPL), incorporated herein by reference. |
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Drivers based on or derived from this code fall under the GPL and must |
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retain the authorship, copyright and license notice. This file is not |
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a complete program and may only be used when the entire operating |
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system is licensed under the GPL. |
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The author may be reached as [email protected], or C/O |
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Scyld Computing Corporation |
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410 Severn Ave., Suite 210 |
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Annapolis MD 21403 |
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Support information and updates available at |
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http://www.scyld.com/network/pci-skeleton.html |
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Linux kernel updates: |
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Version 2.51, Nov 17, 2001 (jgarzik): |
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- Add ethtool support |
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- Replace some MII-related magic numbers with constants |
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*/ |
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#define DRV_NAME "fealnx" |
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static int debug; /* 1-> print debug message */ |
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static int max_interrupt_work = 20; |
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/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */ |
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static int multicast_filter_limit = 32; |
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/* Set the copy breakpoint for the copy-only-tiny-frames scheme. */ |
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/* Setting to > 1518 effectively disables this feature. */ |
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static int rx_copybreak; |
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/* Used to pass the media type, etc. */ |
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/* Both 'options[]' and 'full_duplex[]' should exist for driver */ |
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/* interoperability. */ |
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/* The media type is usually passed in 'options[]'. */ |
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#define MAX_UNITS 8 /* More are supported, limit only on options */ |
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static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; |
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static int full_duplex[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; |
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/* Operational parameters that are set at compile time. */ |
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/* Keep the ring sizes a power of two for compile efficiency. */ |
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/* The compiler will convert <unsigned>'%'<2^N> into a bit mask. */ |
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/* Making the Tx ring too large decreases the effectiveness of channel */ |
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/* bonding and packet priority. */ |
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/* There are no ill effects from too-large receive rings. */ |
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// 88-12-9 modify, |
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// #define TX_RING_SIZE 16 |
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// #define RX_RING_SIZE 32 |
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#define TX_RING_SIZE 6 |
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#define RX_RING_SIZE 12 |
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#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct fealnx_desc) |
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#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct fealnx_desc) |
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/* Operational parameters that usually are not changed. */ |
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/* Time in jiffies before concluding the transmitter is hung. */ |
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#define TX_TIMEOUT (2*HZ) |
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#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */ |
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/* Include files, designed to support most kernel versions 2.0.0 and later. */ |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/string.h> |
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#include <linux/timer.h> |
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#include <linux/errno.h> |
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#include <linux/ioport.h> |
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#include <linux/interrupt.h> |
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#include <linux/pci.h> |
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#include <linux/netdevice.h> |
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#include <linux/etherdevice.h> |
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#include <linux/skbuff.h> |
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#include <linux/init.h> |
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#include <linux/mii.h> |
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#include <linux/ethtool.h> |
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#include <linux/crc32.h> |
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#include <linux/delay.h> |
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#include <linux/bitops.h> |
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#include <asm/processor.h> /* Processor type for cache alignment. */ |
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#include <asm/io.h> |
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#include <linux/uaccess.h> |
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#include <asm/byteorder.h> |
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/* This driver was written to use PCI memory space, however some x86 systems |
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work only with I/O space accesses. */ |
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#ifndef __alpha__ |
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#define USE_IO_OPS |
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#endif |
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/* Kernel compatibility defines, some common to David Hinds' PCMCIA package. */ |
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/* This is only in the support-all-kernels source code. */ |
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#define RUN_AT(x) (jiffies + (x)) |
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MODULE_AUTHOR("Myson or whoever"); |
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MODULE_DESCRIPTION("Myson MTD-8xx 100/10M Ethernet PCI Adapter Driver"); |
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MODULE_LICENSE("GPL"); |
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module_param(max_interrupt_work, int, 0); |
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module_param(debug, int, 0); |
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module_param(rx_copybreak, int, 0); |
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module_param(multicast_filter_limit, int, 0); |
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module_param_array(options, int, NULL, 0); |
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module_param_array(full_duplex, int, NULL, 0); |
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MODULE_PARM_DESC(max_interrupt_work, "fealnx maximum events handled per interrupt"); |
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MODULE_PARM_DESC(debug, "fealnx enable debugging (0-1)"); |
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MODULE_PARM_DESC(rx_copybreak, "fealnx copy breakpoint for copy-only-tiny-frames"); |
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MODULE_PARM_DESC(multicast_filter_limit, "fealnx maximum number of filtered multicast addresses"); |
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MODULE_PARM_DESC(options, "fealnx: Bits 0-3: media type, bit 17: full duplex"); |
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MODULE_PARM_DESC(full_duplex, "fealnx full duplex setting(s) (1)"); |
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enum { |
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MIN_REGION_SIZE = 136, |
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}; |
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/* A chip capabilities table, matching the entries in pci_tbl[] above. */ |
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enum chip_capability_flags { |
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HAS_MII_XCVR, |
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HAS_CHIP_XCVR, |
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}; |
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/* 89/6/13 add, */ |
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/* for different PHY */ |
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enum phy_type_flags { |
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MysonPHY = 1, |
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AhdocPHY = 2, |
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SeeqPHY = 3, |
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MarvellPHY = 4, |
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Myson981 = 5, |
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LevelOnePHY = 6, |
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OtherPHY = 10, |
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}; |
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struct chip_info { |
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char *chip_name; |
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int flags; |
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}; |
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static const struct chip_info skel_netdrv_tbl[] = { |
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{ "100/10M Ethernet PCI Adapter", HAS_MII_XCVR }, |
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{ "100/10M Ethernet PCI Adapter", HAS_CHIP_XCVR }, |
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{ "1000/100/10M Ethernet PCI Adapter", HAS_MII_XCVR }, |
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}; |
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/* Offsets to the Command and Status Registers. */ |
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enum fealnx_offsets { |
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PAR0 = 0x0, /* physical address 0-3 */ |
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PAR1 = 0x04, /* physical address 4-5 */ |
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MAR0 = 0x08, /* multicast address 0-3 */ |
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MAR1 = 0x0C, /* multicast address 4-7 */ |
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FAR0 = 0x10, /* flow-control address 0-3 */ |
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FAR1 = 0x14, /* flow-control address 4-5 */ |
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TCRRCR = 0x18, /* receive & transmit configuration */ |
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BCR = 0x1C, /* bus command */ |
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TXPDR = 0x20, /* transmit polling demand */ |
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RXPDR = 0x24, /* receive polling demand */ |
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RXCWP = 0x28, /* receive current word pointer */ |
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TXLBA = 0x2C, /* transmit list base address */ |
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RXLBA = 0x30, /* receive list base address */ |
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ISR = 0x34, /* interrupt status */ |
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IMR = 0x38, /* interrupt mask */ |
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FTH = 0x3C, /* flow control high/low threshold */ |
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MANAGEMENT = 0x40, /* bootrom/eeprom and mii management */ |
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TALLY = 0x44, /* tally counters for crc and mpa */ |
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TSR = 0x48, /* tally counter for transmit status */ |
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BMCRSR = 0x4c, /* basic mode control and status */ |
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PHYIDENTIFIER = 0x50, /* phy identifier */ |
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ANARANLPAR = 0x54, /* auto-negotiation advertisement and link |
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partner ability */ |
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ANEROCR = 0x58, /* auto-negotiation expansion and pci conf. */ |
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BPREMRPSR = 0x5c, /* bypass & receive error mask and phy status */ |
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}; |
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/* Bits in the interrupt status/enable registers. */ |
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/* The bits in the Intr Status/Enable registers, mostly interrupt sources. */ |
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enum intr_status_bits { |
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RFCON = 0x00020000, /* receive flow control xon packet */ |
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RFCOFF = 0x00010000, /* receive flow control xoff packet */ |
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LSCStatus = 0x00008000, /* link status change */ |
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ANCStatus = 0x00004000, /* autonegotiation completed */ |
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FBE = 0x00002000, /* fatal bus error */ |
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FBEMask = 0x00001800, /* mask bit12-11 */ |
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ParityErr = 0x00000000, /* parity error */ |
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TargetErr = 0x00001000, /* target abort */ |
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MasterErr = 0x00000800, /* master error */ |
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TUNF = 0x00000400, /* transmit underflow */ |
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ROVF = 0x00000200, /* receive overflow */ |
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ETI = 0x00000100, /* transmit early int */ |
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ERI = 0x00000080, /* receive early int */ |
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CNTOVF = 0x00000040, /* counter overflow */ |
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RBU = 0x00000020, /* receive buffer unavailable */ |
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TBU = 0x00000010, /* transmit buffer unavilable */ |
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TI = 0x00000008, /* transmit interrupt */ |
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RI = 0x00000004, /* receive interrupt */ |
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RxErr = 0x00000002, /* receive error */ |
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}; |
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/* Bits in the NetworkConfig register, W for writing, R for reading */ |
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/* FIXME: some names are invented by me. Marked with (name?) */ |
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/* If you have docs and know bit names, please fix 'em */ |
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enum rx_mode_bits { |
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CR_W_ENH = 0x02000000, /* enhanced mode (name?) */ |
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CR_W_FD = 0x00100000, /* full duplex */ |
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CR_W_PS10 = 0x00080000, /* 10 mbit */ |
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CR_W_TXEN = 0x00040000, /* tx enable (name?) */ |
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CR_W_PS1000 = 0x00010000, /* 1000 mbit */ |
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/* CR_W_RXBURSTMASK= 0x00000e00, Im unsure about this */ |
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CR_W_RXMODEMASK = 0x000000e0, |
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CR_W_PROM = 0x00000080, /* promiscuous mode */ |
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CR_W_AB = 0x00000040, /* accept broadcast */ |
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CR_W_AM = 0x00000020, /* accept mutlicast */ |
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CR_W_ARP = 0x00000008, /* receive runt pkt */ |
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CR_W_ALP = 0x00000004, /* receive long pkt */ |
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CR_W_SEP = 0x00000002, /* receive error pkt */ |
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CR_W_RXEN = 0x00000001, /* rx enable (unicast?) (name?) */ |
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CR_R_TXSTOP = 0x04000000, /* tx stopped (name?) */ |
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CR_R_FD = 0x00100000, /* full duplex detected */ |
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CR_R_PS10 = 0x00080000, /* 10 mbit detected */ |
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CR_R_RXSTOP = 0x00008000, /* rx stopped (name?) */ |
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}; |
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/* The Tulip Rx and Tx buffer descriptors. */ |
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struct fealnx_desc { |
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s32 status; |
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s32 control; |
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u32 buffer; |
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u32 next_desc; |
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struct fealnx_desc *next_desc_logical; |
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struct sk_buff *skbuff; |
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u32 reserved1; |
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u32 reserved2; |
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}; |
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/* Bits in network_desc.status */ |
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enum rx_desc_status_bits { |
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RXOWN = 0x80000000, /* own bit */ |
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FLNGMASK = 0x0fff0000, /* frame length */ |
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FLNGShift = 16, |
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MARSTATUS = 0x00004000, /* multicast address received */ |
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BARSTATUS = 0x00002000, /* broadcast address received */ |
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PHYSTATUS = 0x00001000, /* physical address received */ |
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RXFSD = 0x00000800, /* first descriptor */ |
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RXLSD = 0x00000400, /* last descriptor */ |
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ErrorSummary = 0x80, /* error summary */ |
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RUNTPKT = 0x40, /* runt packet received */ |
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LONGPKT = 0x20, /* long packet received */ |
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FAE = 0x10, /* frame align error */ |
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CRC = 0x08, /* crc error */ |
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RXER = 0x04, /* receive error */ |
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}; |
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enum rx_desc_control_bits { |
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RXIC = 0x00800000, /* interrupt control */ |
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RBSShift = 0, |
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}; |
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enum tx_desc_status_bits { |
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TXOWN = 0x80000000, /* own bit */ |
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JABTO = 0x00004000, /* jabber timeout */ |
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CSL = 0x00002000, /* carrier sense lost */ |
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LC = 0x00001000, /* late collision */ |
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EC = 0x00000800, /* excessive collision */ |
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UDF = 0x00000400, /* fifo underflow */ |
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DFR = 0x00000200, /* deferred */ |
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HF = 0x00000100, /* heartbeat fail */ |
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NCRMask = 0x000000ff, /* collision retry count */ |
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NCRShift = 0, |
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}; |
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enum tx_desc_control_bits { |
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TXIC = 0x80000000, /* interrupt control */ |
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ETIControl = 0x40000000, /* early transmit interrupt */ |
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TXLD = 0x20000000, /* last descriptor */ |
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TXFD = 0x10000000, /* first descriptor */ |
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CRCEnable = 0x08000000, /* crc control */ |
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PADEnable = 0x04000000, /* padding control */ |
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RetryTxLC = 0x02000000, /* retry late collision */ |
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PKTSMask = 0x3ff800, /* packet size bit21-11 */ |
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PKTSShift = 11, |
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TBSMask = 0x000007ff, /* transmit buffer bit 10-0 */ |
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TBSShift = 0, |
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}; |
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/* BootROM/EEPROM/MII Management Register */ |
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#define MASK_MIIR_MII_READ 0x00000000 |
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#define MASK_MIIR_MII_WRITE 0x00000008 |
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#define MASK_MIIR_MII_MDO 0x00000004 |
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#define MASK_MIIR_MII_MDI 0x00000002 |
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#define MASK_MIIR_MII_MDC 0x00000001 |
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/* ST+OP+PHYAD+REGAD+TA */ |
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#define OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */ |
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#define OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */ |
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/* ------------------------------------------------------------------------- */ |
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/* Constants for Myson PHY */ |
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/* ------------------------------------------------------------------------- */ |
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#define MysonPHYID 0xd0000302 |
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/* 89-7-27 add, (begin) */ |
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#define MysonPHYID0 0x0302 |
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#define StatusRegister 18 |
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#define SPEED100 0x0400 // bit10 |
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#define FULLMODE 0x0800 // bit11 |
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/* 89-7-27 add, (end) */ |
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/* ------------------------------------------------------------------------- */ |
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/* Constants for Seeq 80225 PHY */ |
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/* ------------------------------------------------------------------------- */ |
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#define SeeqPHYID0 0x0016 |
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#define MIIRegister18 18 |
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#define SPD_DET_100 0x80 |
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#define DPLX_DET_FULL 0x40 |
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/* ------------------------------------------------------------------------- */ |
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/* Constants for Ahdoc 101 PHY */ |
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/* ------------------------------------------------------------------------- */ |
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#define AhdocPHYID0 0x0022 |
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#define DiagnosticReg 18 |
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#define DPLX_FULL 0x0800 |
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#define Speed_100 0x0400 |
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/* 89/6/13 add, */ |
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/* -------------------------------------------------------------------------- */ |
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/* Constants */ |
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/* -------------------------------------------------------------------------- */ |
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#define MarvellPHYID0 0x0141 |
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#define LevelOnePHYID0 0x0013 |
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#define MII1000BaseTControlReg 9 |
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#define MII1000BaseTStatusReg 10 |
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#define SpecificReg 17 |
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/* for 1000BaseT Control Register */ |
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#define PHYAbletoPerform1000FullDuplex 0x0200 |
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#define PHYAbletoPerform1000HalfDuplex 0x0100 |
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#define PHY1000AbilityMask 0x300 |
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// for phy specific status register, marvell phy. |
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#define SpeedMask 0x0c000 |
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#define Speed_1000M 0x08000 |
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#define Speed_100M 0x4000 |
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#define Speed_10M 0 |
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#define Full_Duplex 0x2000 |
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// 89/12/29 add, for phy specific status register, levelone phy, (begin) |
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#define LXT1000_100M 0x08000 |
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#define LXT1000_1000M 0x0c000 |
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#define LXT1000_Full 0x200 |
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// 89/12/29 add, for phy specific status register, levelone phy, (end) |
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/* for 3-in-1 case, BMCRSR register */ |
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#define LinkIsUp2 0x00040000 |
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/* for PHY */ |
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#define LinkIsUp 0x0004 |
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struct netdev_private { |
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/* Descriptor rings first for alignment. */ |
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struct fealnx_desc *rx_ring; |
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struct fealnx_desc *tx_ring; |
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dma_addr_t rx_ring_dma; |
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dma_addr_t tx_ring_dma; |
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spinlock_t lock; |
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/* Media monitoring timer. */ |
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struct timer_list timer; |
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/* Reset timer */ |
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struct timer_list reset_timer; |
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int reset_timer_armed; |
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unsigned long crvalue_sv; |
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unsigned long imrvalue_sv; |
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/* Frequently used values: keep some adjacent for cache effect. */ |
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int flags; |
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struct pci_dev *pci_dev; |
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unsigned long crvalue; |
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unsigned long bcrvalue; |
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unsigned long imrvalue; |
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struct fealnx_desc *cur_rx; |
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struct fealnx_desc *lack_rxbuf; |
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int really_rx_count; |
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struct fealnx_desc *cur_tx; |
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struct fealnx_desc *cur_tx_copy; |
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int really_tx_count; |
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int free_tx_count; |
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unsigned int rx_buf_sz; /* Based on MTU+slack. */ |
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/* These values are keep track of the transceiver/media in use. */ |
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unsigned int linkok; |
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unsigned int line_speed; |
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unsigned int duplexmode; |
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unsigned int default_port:4; /* Last dev->if_port value. */ |
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unsigned int PHYType; |
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/* MII transceiver section. */ |
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int mii_cnt; /* MII device addresses. */ |
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unsigned char phys[2]; /* MII device addresses. */ |
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struct mii_if_info mii; |
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void __iomem *mem; |
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}; |
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static int mdio_read(struct net_device *dev, int phy_id, int location); |
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static void mdio_write(struct net_device *dev, int phy_id, int location, int value); |
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static int netdev_open(struct net_device *dev); |
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static void getlinktype(struct net_device *dev); |
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static void getlinkstatus(struct net_device *dev); |
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static void netdev_timer(struct timer_list *t); |
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static void reset_timer(struct timer_list *t); |
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static void fealnx_tx_timeout(struct net_device *dev, unsigned int txqueue); |
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static void init_ring(struct net_device *dev); |
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static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev); |
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static irqreturn_t intr_handler(int irq, void *dev_instance); |
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static int netdev_rx(struct net_device *dev); |
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static void set_rx_mode(struct net_device *dev); |
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static void __set_rx_mode(struct net_device *dev); |
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static struct net_device_stats *get_stats(struct net_device *dev); |
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static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
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static const struct ethtool_ops netdev_ethtool_ops; |
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static int netdev_close(struct net_device *dev); |
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static void reset_rx_descriptors(struct net_device *dev); |
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static void reset_tx_descriptors(struct net_device *dev); |
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static void stop_nic_rx(void __iomem *ioaddr, long crvalue) |
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{ |
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int delay = 0x1000; |
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iowrite32(crvalue & ~(CR_W_RXEN), ioaddr + TCRRCR); |
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while (--delay) { |
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if ( (ioread32(ioaddr + TCRRCR) & CR_R_RXSTOP) == CR_R_RXSTOP) |
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break; |
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} |
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} |
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static void stop_nic_rxtx(void __iomem *ioaddr, long crvalue) |
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{ |
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int delay = 0x1000; |
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iowrite32(crvalue & ~(CR_W_RXEN+CR_W_TXEN), ioaddr + TCRRCR); |
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while (--delay) { |
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if ( (ioread32(ioaddr + TCRRCR) & (CR_R_RXSTOP+CR_R_TXSTOP)) |
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== (CR_R_RXSTOP+CR_R_TXSTOP) ) |
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break; |
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} |
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} |
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static const struct net_device_ops netdev_ops = { |
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.ndo_open = netdev_open, |
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.ndo_stop = netdev_close, |
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.ndo_start_xmit = start_tx, |
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.ndo_get_stats = get_stats, |
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.ndo_set_rx_mode = set_rx_mode, |
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.ndo_do_ioctl = mii_ioctl, |
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.ndo_tx_timeout = fealnx_tx_timeout, |
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.ndo_set_mac_address = eth_mac_addr, |
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.ndo_validate_addr = eth_validate_addr, |
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}; |
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static int fealnx_init_one(struct pci_dev *pdev, |
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const struct pci_device_id *ent) |
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{ |
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struct netdev_private *np; |
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int i, option, err, irq; |
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static int card_idx = -1; |
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char boardname[12]; |
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void __iomem *ioaddr; |
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unsigned long len; |
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unsigned int chip_id = ent->driver_data; |
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struct net_device *dev; |
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void *ring_space; |
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dma_addr_t ring_dma; |
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#ifdef USE_IO_OPS |
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int bar = 0; |
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#else |
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int bar = 1; |
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#endif |
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card_idx++; |
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sprintf(boardname, "fealnx%d", card_idx); |
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option = card_idx < MAX_UNITS ? options[card_idx] : 0; |
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i = pci_enable_device(pdev); |
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if (i) return i; |
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pci_set_master(pdev); |
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len = pci_resource_len(pdev, bar); |
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if (len < MIN_REGION_SIZE) { |
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dev_err(&pdev->dev, |
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"region size %ld too small, aborting\n", len); |
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return -ENODEV; |
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} |
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i = pci_request_regions(pdev, boardname); |
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if (i) |
|
return i; |
|
|
|
irq = pdev->irq; |
|
|
|
ioaddr = pci_iomap(pdev, bar, len); |
|
if (!ioaddr) { |
|
err = -ENOMEM; |
|
goto err_out_res; |
|
} |
|
|
|
dev = alloc_etherdev(sizeof(struct netdev_private)); |
|
if (!dev) { |
|
err = -ENOMEM; |
|
goto err_out_unmap; |
|
} |
|
SET_NETDEV_DEV(dev, &pdev->dev); |
|
|
|
/* read ethernet id */ |
|
for (i = 0; i < 6; ++i) |
|
dev->dev_addr[i] = ioread8(ioaddr + PAR0 + i); |
|
|
|
/* Reset the chip to erase previous misconfiguration. */ |
|
iowrite32(0x00000001, ioaddr + BCR); |
|
|
|
/* Make certain the descriptor lists are aligned. */ |
|
np = netdev_priv(dev); |
|
np->mem = ioaddr; |
|
spin_lock_init(&np->lock); |
|
np->pci_dev = pdev; |
|
np->flags = skel_netdrv_tbl[chip_id].flags; |
|
pci_set_drvdata(pdev, dev); |
|
np->mii.dev = dev; |
|
np->mii.mdio_read = mdio_read; |
|
np->mii.mdio_write = mdio_write; |
|
np->mii.phy_id_mask = 0x1f; |
|
np->mii.reg_num_mask = 0x1f; |
|
|
|
ring_space = dma_alloc_coherent(&pdev->dev, RX_TOTAL_SIZE, &ring_dma, |
|
GFP_KERNEL); |
|
if (!ring_space) { |
|
err = -ENOMEM; |
|
goto err_out_free_dev; |
|
} |
|
np->rx_ring = ring_space; |
|
np->rx_ring_dma = ring_dma; |
|
|
|
ring_space = dma_alloc_coherent(&pdev->dev, TX_TOTAL_SIZE, &ring_dma, |
|
GFP_KERNEL); |
|
if (!ring_space) { |
|
err = -ENOMEM; |
|
goto err_out_free_rx; |
|
} |
|
np->tx_ring = ring_space; |
|
np->tx_ring_dma = ring_dma; |
|
|
|
/* find the connected MII xcvrs */ |
|
if (np->flags == HAS_MII_XCVR) { |
|
int phy, phy_idx = 0; |
|
|
|
for (phy = 1; phy < 32 && phy_idx < ARRAY_SIZE(np->phys); |
|
phy++) { |
|
int mii_status = mdio_read(dev, phy, 1); |
|
|
|
if (mii_status != 0xffff && mii_status != 0x0000) { |
|
np->phys[phy_idx++] = phy; |
|
dev_info(&pdev->dev, |
|
"MII PHY found at address %d, status " |
|
"0x%4.4x.\n", phy, mii_status); |
|
/* get phy type */ |
|
{ |
|
unsigned int data; |
|
|
|
data = mdio_read(dev, np->phys[0], 2); |
|
if (data == SeeqPHYID0) |
|
np->PHYType = SeeqPHY; |
|
else if (data == AhdocPHYID0) |
|
np->PHYType = AhdocPHY; |
|
else if (data == MarvellPHYID0) |
|
np->PHYType = MarvellPHY; |
|
else if (data == MysonPHYID0) |
|
np->PHYType = Myson981; |
|
else if (data == LevelOnePHYID0) |
|
np->PHYType = LevelOnePHY; |
|
else |
|
np->PHYType = OtherPHY; |
|
} |
|
} |
|
} |
|
|
|
np->mii_cnt = phy_idx; |
|
if (phy_idx == 0) |
|
dev_warn(&pdev->dev, |
|
"MII PHY not found -- this device may " |
|
"not operate correctly.\n"); |
|
} else { |
|
np->phys[0] = 32; |
|
/* 89/6/23 add, (begin) */ |
|
/* get phy type */ |
|
if (ioread32(ioaddr + PHYIDENTIFIER) == MysonPHYID) |
|
np->PHYType = MysonPHY; |
|
else |
|
np->PHYType = OtherPHY; |
|
} |
|
np->mii.phy_id = np->phys[0]; |
|
|
|
if (dev->mem_start) |
|
option = dev->mem_start; |
|
|
|
/* The lower four bits are the media type. */ |
|
if (option > 0) { |
|
if (option & 0x200) |
|
np->mii.full_duplex = 1; |
|
np->default_port = option & 15; |
|
} |
|
|
|
if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0) |
|
np->mii.full_duplex = full_duplex[card_idx]; |
|
|
|
if (np->mii.full_duplex) { |
|
dev_info(&pdev->dev, "Media type forced to Full Duplex.\n"); |
|
/* 89/6/13 add, (begin) */ |
|
// if (np->PHYType==MarvellPHY) |
|
if ((np->PHYType == MarvellPHY) || (np->PHYType == LevelOnePHY)) { |
|
unsigned int data; |
|
|
|
data = mdio_read(dev, np->phys[0], 9); |
|
data = (data & 0xfcff) | 0x0200; |
|
mdio_write(dev, np->phys[0], 9, data); |
|
} |
|
/* 89/6/13 add, (end) */ |
|
if (np->flags == HAS_MII_XCVR) |
|
mdio_write(dev, np->phys[0], MII_ADVERTISE, ADVERTISE_FULL); |
|
else |
|
iowrite32(ADVERTISE_FULL, ioaddr + ANARANLPAR); |
|
np->mii.force_media = 1; |
|
} |
|
|
|
dev->netdev_ops = &netdev_ops; |
|
dev->ethtool_ops = &netdev_ethtool_ops; |
|
dev->watchdog_timeo = TX_TIMEOUT; |
|
|
|
err = register_netdev(dev); |
|
if (err) |
|
goto err_out_free_tx; |
|
|
|
printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n", |
|
dev->name, skel_netdrv_tbl[chip_id].chip_name, ioaddr, |
|
dev->dev_addr, irq); |
|
|
|
return 0; |
|
|
|
err_out_free_tx: |
|
dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring, |
|
np->tx_ring_dma); |
|
err_out_free_rx: |
|
dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring, |
|
np->rx_ring_dma); |
|
err_out_free_dev: |
|
free_netdev(dev); |
|
err_out_unmap: |
|
pci_iounmap(pdev, ioaddr); |
|
err_out_res: |
|
pci_release_regions(pdev); |
|
return err; |
|
} |
|
|
|
|
|
static void fealnx_remove_one(struct pci_dev *pdev) |
|
{ |
|
struct net_device *dev = pci_get_drvdata(pdev); |
|
|
|
if (dev) { |
|
struct netdev_private *np = netdev_priv(dev); |
|
|
|
dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring, |
|
np->tx_ring_dma); |
|
dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring, |
|
np->rx_ring_dma); |
|
unregister_netdev(dev); |
|
pci_iounmap(pdev, np->mem); |
|
free_netdev(dev); |
|
pci_release_regions(pdev); |
|
} else |
|
printk(KERN_ERR "fealnx: remove for unknown device\n"); |
|
} |
|
|
|
|
|
static ulong m80x_send_cmd_to_phy(void __iomem *miiport, int opcode, int phyad, int regad) |
|
{ |
|
ulong miir; |
|
int i; |
|
unsigned int mask, data; |
|
|
|
/* enable MII output */ |
|
miir = (ulong) ioread32(miiport); |
|
miir &= 0xfffffff0; |
|
|
|
miir |= MASK_MIIR_MII_WRITE + MASK_MIIR_MII_MDO; |
|
|
|
/* send 32 1's preamble */ |
|
for (i = 0; i < 32; i++) { |
|
/* low MDC; MDO is already high (miir) */ |
|
miir &= ~MASK_MIIR_MII_MDC; |
|
iowrite32(miir, miiport); |
|
|
|
/* high MDC */ |
|
miir |= MASK_MIIR_MII_MDC; |
|
iowrite32(miir, miiport); |
|
} |
|
|
|
/* calculate ST+OP+PHYAD+REGAD+TA */ |
|
data = opcode | (phyad << 7) | (regad << 2); |
|
|
|
/* sent out */ |
|
mask = 0x8000; |
|
while (mask) { |
|
/* low MDC, prepare MDO */ |
|
miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO); |
|
if (mask & data) |
|
miir |= MASK_MIIR_MII_MDO; |
|
|
|
iowrite32(miir, miiport); |
|
/* high MDC */ |
|
miir |= MASK_MIIR_MII_MDC; |
|
iowrite32(miir, miiport); |
|
udelay(30); |
|
|
|
/* next */ |
|
mask >>= 1; |
|
if (mask == 0x2 && opcode == OP_READ) |
|
miir &= ~MASK_MIIR_MII_WRITE; |
|
} |
|
return miir; |
|
} |
|
|
|
|
|
static int mdio_read(struct net_device *dev, int phyad, int regad) |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
void __iomem *miiport = np->mem + MANAGEMENT; |
|
ulong miir; |
|
unsigned int mask, data; |
|
|
|
miir = m80x_send_cmd_to_phy(miiport, OP_READ, phyad, regad); |
|
|
|
/* read data */ |
|
mask = 0x8000; |
|
data = 0; |
|
while (mask) { |
|
/* low MDC */ |
|
miir &= ~MASK_MIIR_MII_MDC; |
|
iowrite32(miir, miiport); |
|
|
|
/* read MDI */ |
|
miir = ioread32(miiport); |
|
if (miir & MASK_MIIR_MII_MDI) |
|
data |= mask; |
|
|
|
/* high MDC, and wait */ |
|
miir |= MASK_MIIR_MII_MDC; |
|
iowrite32(miir, miiport); |
|
udelay(30); |
|
|
|
/* next */ |
|
mask >>= 1; |
|
} |
|
|
|
/* low MDC */ |
|
miir &= ~MASK_MIIR_MII_MDC; |
|
iowrite32(miir, miiport); |
|
|
|
return data & 0xffff; |
|
} |
|
|
|
|
|
static void mdio_write(struct net_device *dev, int phyad, int regad, int data) |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
void __iomem *miiport = np->mem + MANAGEMENT; |
|
ulong miir; |
|
unsigned int mask; |
|
|
|
miir = m80x_send_cmd_to_phy(miiport, OP_WRITE, phyad, regad); |
|
|
|
/* write data */ |
|
mask = 0x8000; |
|
while (mask) { |
|
/* low MDC, prepare MDO */ |
|
miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO); |
|
if (mask & data) |
|
miir |= MASK_MIIR_MII_MDO; |
|
iowrite32(miir, miiport); |
|
|
|
/* high MDC */ |
|
miir |= MASK_MIIR_MII_MDC; |
|
iowrite32(miir, miiport); |
|
|
|
/* next */ |
|
mask >>= 1; |
|
} |
|
|
|
/* low MDC */ |
|
miir &= ~MASK_MIIR_MII_MDC; |
|
iowrite32(miir, miiport); |
|
} |
|
|
|
|
|
static int netdev_open(struct net_device *dev) |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
void __iomem *ioaddr = np->mem; |
|
const int irq = np->pci_dev->irq; |
|
int rc, i; |
|
|
|
iowrite32(0x00000001, ioaddr + BCR); /* Reset */ |
|
|
|
rc = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev); |
|
if (rc) |
|
return -EAGAIN; |
|
|
|
for (i = 0; i < 3; i++) |
|
iowrite16(((unsigned short*)dev->dev_addr)[i], |
|
ioaddr + PAR0 + i*2); |
|
|
|
init_ring(dev); |
|
|
|
iowrite32(np->rx_ring_dma, ioaddr + RXLBA); |
|
iowrite32(np->tx_ring_dma, ioaddr + TXLBA); |
|
|
|
/* Initialize other registers. */ |
|
/* Configure the PCI bus bursts and FIFO thresholds. |
|
486: Set 8 longword burst. |
|
586: no burst limit. |
|
Burst length 5:3 |
|
0 0 0 1 |
|
0 0 1 4 |
|
0 1 0 8 |
|
0 1 1 16 |
|
1 0 0 32 |
|
1 0 1 64 |
|
1 1 0 128 |
|
1 1 1 256 |
|
Wait the specified 50 PCI cycles after a reset by initializing |
|
Tx and Rx queues and the address filter list. |
|
FIXME (Ueimor): optimistic for alpha + posted writes ? */ |
|
|
|
np->bcrvalue = 0x10; /* little-endian, 8 burst length */ |
|
#ifdef __BIG_ENDIAN |
|
np->bcrvalue |= 0x04; /* big-endian */ |
|
#endif |
|
|
|
#if defined(__i386__) && !defined(MODULE) |
|
if (boot_cpu_data.x86 <= 4) |
|
np->crvalue = 0xa00; |
|
else |
|
#endif |
|
np->crvalue = 0xe00; /* rx 128 burst length */ |
|
|
|
|
|
// 89/12/29 add, |
|
// 90/1/16 modify, |
|
// np->imrvalue=FBE|TUNF|CNTOVF|RBU|TI|RI; |
|
np->imrvalue = TUNF | CNTOVF | RBU | TI | RI; |
|
if (np->pci_dev->device == 0x891) { |
|
np->bcrvalue |= 0x200; /* set PROG bit */ |
|
np->crvalue |= CR_W_ENH; /* set enhanced bit */ |
|
np->imrvalue |= ETI; |
|
} |
|
iowrite32(np->bcrvalue, ioaddr + BCR); |
|
|
|
if (dev->if_port == 0) |
|
dev->if_port = np->default_port; |
|
|
|
iowrite32(0, ioaddr + RXPDR); |
|
// 89/9/1 modify, |
|
// np->crvalue = 0x00e40001; /* tx store and forward, tx/rx enable */ |
|
np->crvalue |= 0x00e40001; /* tx store and forward, tx/rx enable */ |
|
np->mii.full_duplex = np->mii.force_media; |
|
getlinkstatus(dev); |
|
if (np->linkok) |
|
getlinktype(dev); |
|
__set_rx_mode(dev); |
|
|
|
netif_start_queue(dev); |
|
|
|
/* Clear and Enable interrupts by setting the interrupt mask. */ |
|
iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR); |
|
iowrite32(np->imrvalue, ioaddr + IMR); |
|
|
|
if (debug) |
|
printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name); |
|
|
|
/* Set the timer to check for link beat. */ |
|
timer_setup(&np->timer, netdev_timer, 0); |
|
np->timer.expires = RUN_AT(3 * HZ); |
|
|
|
/* timer handler */ |
|
add_timer(&np->timer); |
|
|
|
timer_setup(&np->reset_timer, reset_timer, 0); |
|
np->reset_timer_armed = 0; |
|
return rc; |
|
} |
|
|
|
|
|
static void getlinkstatus(struct net_device *dev) |
|
/* function: Routine will read MII Status Register to get link status. */ |
|
/* input : dev... pointer to the adapter block. */ |
|
/* output : none. */ |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
unsigned int i, DelayTime = 0x1000; |
|
|
|
np->linkok = 0; |
|
|
|
if (np->PHYType == MysonPHY) { |
|
for (i = 0; i < DelayTime; ++i) { |
|
if (ioread32(np->mem + BMCRSR) & LinkIsUp2) { |
|
np->linkok = 1; |
|
return; |
|
} |
|
udelay(100); |
|
} |
|
} else { |
|
for (i = 0; i < DelayTime; ++i) { |
|
if (mdio_read(dev, np->phys[0], MII_BMSR) & BMSR_LSTATUS) { |
|
np->linkok = 1; |
|
return; |
|
} |
|
udelay(100); |
|
} |
|
} |
|
} |
|
|
|
|
|
static void getlinktype(struct net_device *dev) |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
|
|
if (np->PHYType == MysonPHY) { /* 3-in-1 case */ |
|
if (ioread32(np->mem + TCRRCR) & CR_R_FD) |
|
np->duplexmode = 2; /* full duplex */ |
|
else |
|
np->duplexmode = 1; /* half duplex */ |
|
if (ioread32(np->mem + TCRRCR) & CR_R_PS10) |
|
np->line_speed = 1; /* 10M */ |
|
else |
|
np->line_speed = 2; /* 100M */ |
|
} else { |
|
if (np->PHYType == SeeqPHY) { /* this PHY is SEEQ 80225 */ |
|
unsigned int data; |
|
|
|
data = mdio_read(dev, np->phys[0], MIIRegister18); |
|
if (data & SPD_DET_100) |
|
np->line_speed = 2; /* 100M */ |
|
else |
|
np->line_speed = 1; /* 10M */ |
|
if (data & DPLX_DET_FULL) |
|
np->duplexmode = 2; /* full duplex mode */ |
|
else |
|
np->duplexmode = 1; /* half duplex mode */ |
|
} else if (np->PHYType == AhdocPHY) { |
|
unsigned int data; |
|
|
|
data = mdio_read(dev, np->phys[0], DiagnosticReg); |
|
if (data & Speed_100) |
|
np->line_speed = 2; /* 100M */ |
|
else |
|
np->line_speed = 1; /* 10M */ |
|
if (data & DPLX_FULL) |
|
np->duplexmode = 2; /* full duplex mode */ |
|
else |
|
np->duplexmode = 1; /* half duplex mode */ |
|
} |
|
/* 89/6/13 add, (begin) */ |
|
else if (np->PHYType == MarvellPHY) { |
|
unsigned int data; |
|
|
|
data = mdio_read(dev, np->phys[0], SpecificReg); |
|
if (data & Full_Duplex) |
|
np->duplexmode = 2; /* full duplex mode */ |
|
else |
|
np->duplexmode = 1; /* half duplex mode */ |
|
data &= SpeedMask; |
|
if (data == Speed_1000M) |
|
np->line_speed = 3; /* 1000M */ |
|
else if (data == Speed_100M) |
|
np->line_speed = 2; /* 100M */ |
|
else |
|
np->line_speed = 1; /* 10M */ |
|
} |
|
/* 89/6/13 add, (end) */ |
|
/* 89/7/27 add, (begin) */ |
|
else if (np->PHYType == Myson981) { |
|
unsigned int data; |
|
|
|
data = mdio_read(dev, np->phys[0], StatusRegister); |
|
|
|
if (data & SPEED100) |
|
np->line_speed = 2; |
|
else |
|
np->line_speed = 1; |
|
|
|
if (data & FULLMODE) |
|
np->duplexmode = 2; |
|
else |
|
np->duplexmode = 1; |
|
} |
|
/* 89/7/27 add, (end) */ |
|
/* 89/12/29 add */ |
|
else if (np->PHYType == LevelOnePHY) { |
|
unsigned int data; |
|
|
|
data = mdio_read(dev, np->phys[0], SpecificReg); |
|
if (data & LXT1000_Full) |
|
np->duplexmode = 2; /* full duplex mode */ |
|
else |
|
np->duplexmode = 1; /* half duplex mode */ |
|
data &= SpeedMask; |
|
if (data == LXT1000_1000M) |
|
np->line_speed = 3; /* 1000M */ |
|
else if (data == LXT1000_100M) |
|
np->line_speed = 2; /* 100M */ |
|
else |
|
np->line_speed = 1; /* 10M */ |
|
} |
|
np->crvalue &= (~CR_W_PS10) & (~CR_W_FD) & (~CR_W_PS1000); |
|
if (np->line_speed == 1) |
|
np->crvalue |= CR_W_PS10; |
|
else if (np->line_speed == 3) |
|
np->crvalue |= CR_W_PS1000; |
|
if (np->duplexmode == 2) |
|
np->crvalue |= CR_W_FD; |
|
} |
|
} |
|
|
|
|
|
/* Take lock before calling this */ |
|
static void allocate_rx_buffers(struct net_device *dev) |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
|
|
/* allocate skb for rx buffers */ |
|
while (np->really_rx_count != RX_RING_SIZE) { |
|
struct sk_buff *skb; |
|
|
|
skb = netdev_alloc_skb(dev, np->rx_buf_sz); |
|
if (skb == NULL) |
|
break; /* Better luck next round. */ |
|
|
|
while (np->lack_rxbuf->skbuff) |
|
np->lack_rxbuf = np->lack_rxbuf->next_desc_logical; |
|
|
|
np->lack_rxbuf->skbuff = skb; |
|
np->lack_rxbuf->buffer = dma_map_single(&np->pci_dev->dev, |
|
skb->data, |
|
np->rx_buf_sz, |
|
DMA_FROM_DEVICE); |
|
np->lack_rxbuf->status = RXOWN; |
|
++np->really_rx_count; |
|
} |
|
} |
|
|
|
|
|
static void netdev_timer(struct timer_list *t) |
|
{ |
|
struct netdev_private *np = from_timer(np, t, timer); |
|
struct net_device *dev = np->mii.dev; |
|
void __iomem *ioaddr = np->mem; |
|
int old_crvalue = np->crvalue; |
|
unsigned int old_linkok = np->linkok; |
|
unsigned long flags; |
|
|
|
if (debug) |
|
printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x " |
|
"config %8.8x.\n", dev->name, ioread32(ioaddr + ISR), |
|
ioread32(ioaddr + TCRRCR)); |
|
|
|
spin_lock_irqsave(&np->lock, flags); |
|
|
|
if (np->flags == HAS_MII_XCVR) { |
|
getlinkstatus(dev); |
|
if ((old_linkok == 0) && (np->linkok == 1)) { /* we need to detect the media type again */ |
|
getlinktype(dev); |
|
if (np->crvalue != old_crvalue) { |
|
stop_nic_rxtx(ioaddr, np->crvalue); |
|
iowrite32(np->crvalue, ioaddr + TCRRCR); |
|
} |
|
} |
|
} |
|
|
|
allocate_rx_buffers(dev); |
|
|
|
spin_unlock_irqrestore(&np->lock, flags); |
|
|
|
np->timer.expires = RUN_AT(10 * HZ); |
|
add_timer(&np->timer); |
|
} |
|
|
|
|
|
/* Take lock before calling */ |
|
/* Reset chip and disable rx, tx and interrupts */ |
|
static void reset_and_disable_rxtx(struct net_device *dev) |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
void __iomem *ioaddr = np->mem; |
|
int delay=51; |
|
|
|
/* Reset the chip's Tx and Rx processes. */ |
|
stop_nic_rxtx(ioaddr, 0); |
|
|
|
/* Disable interrupts by clearing the interrupt mask. */ |
|
iowrite32(0, ioaddr + IMR); |
|
|
|
/* Reset the chip to erase previous misconfiguration. */ |
|
iowrite32(0x00000001, ioaddr + BCR); |
|
|
|
/* Ueimor: wait for 50 PCI cycles (and flush posted writes btw). |
|
We surely wait too long (address+data phase). Who cares? */ |
|
while (--delay) { |
|
ioread32(ioaddr + BCR); |
|
rmb(); |
|
} |
|
} |
|
|
|
|
|
/* Take lock before calling */ |
|
/* Restore chip after reset */ |
|
static void enable_rxtx(struct net_device *dev) |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
void __iomem *ioaddr = np->mem; |
|
|
|
reset_rx_descriptors(dev); |
|
|
|
iowrite32(np->tx_ring_dma + ((char*)np->cur_tx - (char*)np->tx_ring), |
|
ioaddr + TXLBA); |
|
iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring), |
|
ioaddr + RXLBA); |
|
|
|
iowrite32(np->bcrvalue, ioaddr + BCR); |
|
|
|
iowrite32(0, ioaddr + RXPDR); |
|
__set_rx_mode(dev); /* changes np->crvalue, writes it into TCRRCR */ |
|
|
|
/* Clear and Enable interrupts by setting the interrupt mask. */ |
|
iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR); |
|
iowrite32(np->imrvalue, ioaddr + IMR); |
|
|
|
iowrite32(0, ioaddr + TXPDR); |
|
} |
|
|
|
|
|
static void reset_timer(struct timer_list *t) |
|
{ |
|
struct netdev_private *np = from_timer(np, t, reset_timer); |
|
struct net_device *dev = np->mii.dev; |
|
unsigned long flags; |
|
|
|
printk(KERN_WARNING "%s: resetting tx and rx machinery\n", dev->name); |
|
|
|
spin_lock_irqsave(&np->lock, flags); |
|
np->crvalue = np->crvalue_sv; |
|
np->imrvalue = np->imrvalue_sv; |
|
|
|
reset_and_disable_rxtx(dev); |
|
/* works for me without this: |
|
reset_tx_descriptors(dev); */ |
|
enable_rxtx(dev); |
|
netif_start_queue(dev); /* FIXME: or netif_wake_queue(dev); ? */ |
|
|
|
np->reset_timer_armed = 0; |
|
|
|
spin_unlock_irqrestore(&np->lock, flags); |
|
} |
|
|
|
|
|
static void fealnx_tx_timeout(struct net_device *dev, unsigned int txqueue) |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
void __iomem *ioaddr = np->mem; |
|
unsigned long flags; |
|
int i; |
|
|
|
printk(KERN_WARNING |
|
"%s: Transmit timed out, status %8.8x, resetting...\n", |
|
dev->name, ioread32(ioaddr + ISR)); |
|
|
|
{ |
|
printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring); |
|
for (i = 0; i < RX_RING_SIZE; i++) |
|
printk(KERN_CONT " %8.8x", |
|
(unsigned int) np->rx_ring[i].status); |
|
printk(KERN_CONT "\n"); |
|
printk(KERN_DEBUG " Tx ring %p: ", np->tx_ring); |
|
for (i = 0; i < TX_RING_SIZE; i++) |
|
printk(KERN_CONT " %4.4x", np->tx_ring[i].status); |
|
printk(KERN_CONT "\n"); |
|
} |
|
|
|
spin_lock_irqsave(&np->lock, flags); |
|
|
|
reset_and_disable_rxtx(dev); |
|
reset_tx_descriptors(dev); |
|
enable_rxtx(dev); |
|
|
|
spin_unlock_irqrestore(&np->lock, flags); |
|
|
|
netif_trans_update(dev); /* prevent tx timeout */ |
|
dev->stats.tx_errors++; |
|
netif_wake_queue(dev); /* or .._start_.. ?? */ |
|
} |
|
|
|
|
|
/* Initialize the Rx and Tx rings, along with various 'dev' bits. */ |
|
static void init_ring(struct net_device *dev) |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
int i; |
|
|
|
/* initialize rx variables */ |
|
np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32); |
|
np->cur_rx = &np->rx_ring[0]; |
|
np->lack_rxbuf = np->rx_ring; |
|
np->really_rx_count = 0; |
|
|
|
/* initial rx descriptors. */ |
|
for (i = 0; i < RX_RING_SIZE; i++) { |
|
np->rx_ring[i].status = 0; |
|
np->rx_ring[i].control = np->rx_buf_sz << RBSShift; |
|
np->rx_ring[i].next_desc = np->rx_ring_dma + |
|
(i + 1)*sizeof(struct fealnx_desc); |
|
np->rx_ring[i].next_desc_logical = &np->rx_ring[i + 1]; |
|
np->rx_ring[i].skbuff = NULL; |
|
} |
|
|
|
/* for the last rx descriptor */ |
|
np->rx_ring[i - 1].next_desc = np->rx_ring_dma; |
|
np->rx_ring[i - 1].next_desc_logical = np->rx_ring; |
|
|
|
/* allocate skb for rx buffers */ |
|
for (i = 0; i < RX_RING_SIZE; i++) { |
|
struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz); |
|
|
|
if (skb == NULL) { |
|
np->lack_rxbuf = &np->rx_ring[i]; |
|
break; |
|
} |
|
|
|
++np->really_rx_count; |
|
np->rx_ring[i].skbuff = skb; |
|
np->rx_ring[i].buffer = dma_map_single(&np->pci_dev->dev, |
|
skb->data, |
|
np->rx_buf_sz, |
|
DMA_FROM_DEVICE); |
|
np->rx_ring[i].status = RXOWN; |
|
np->rx_ring[i].control |= RXIC; |
|
} |
|
|
|
/* initialize tx variables */ |
|
np->cur_tx = &np->tx_ring[0]; |
|
np->cur_tx_copy = &np->tx_ring[0]; |
|
np->really_tx_count = 0; |
|
np->free_tx_count = TX_RING_SIZE; |
|
|
|
for (i = 0; i < TX_RING_SIZE; i++) { |
|
np->tx_ring[i].status = 0; |
|
/* do we need np->tx_ring[i].control = XXX; ?? */ |
|
np->tx_ring[i].next_desc = np->tx_ring_dma + |
|
(i + 1)*sizeof(struct fealnx_desc); |
|
np->tx_ring[i].next_desc_logical = &np->tx_ring[i + 1]; |
|
np->tx_ring[i].skbuff = NULL; |
|
} |
|
|
|
/* for the last tx descriptor */ |
|
np->tx_ring[i - 1].next_desc = np->tx_ring_dma; |
|
np->tx_ring[i - 1].next_desc_logical = &np->tx_ring[0]; |
|
} |
|
|
|
|
|
static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev) |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
unsigned long flags; |
|
|
|
spin_lock_irqsave(&np->lock, flags); |
|
|
|
np->cur_tx_copy->skbuff = skb; |
|
|
|
#define one_buffer |
|
#define BPT 1022 |
|
#if defined(one_buffer) |
|
np->cur_tx_copy->buffer = dma_map_single(&np->pci_dev->dev, skb->data, |
|
skb->len, DMA_TO_DEVICE); |
|
np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable; |
|
np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */ |
|
np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */ |
|
// 89/12/29 add, |
|
if (np->pci_dev->device == 0x891) |
|
np->cur_tx_copy->control |= ETIControl | RetryTxLC; |
|
np->cur_tx_copy->status = TXOWN; |
|
np->cur_tx_copy = np->cur_tx_copy->next_desc_logical; |
|
--np->free_tx_count; |
|
#elif defined(two_buffer) |
|
if (skb->len > BPT) { |
|
struct fealnx_desc *next; |
|
|
|
/* for the first descriptor */ |
|
np->cur_tx_copy->buffer = dma_map_single(&np->pci_dev->dev, |
|
skb->data, BPT, |
|
DMA_TO_DEVICE); |
|
np->cur_tx_copy->control = TXIC | TXFD | CRCEnable | PADEnable; |
|
np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */ |
|
np->cur_tx_copy->control |= (BPT << TBSShift); /* buffer size */ |
|
|
|
/* for the last descriptor */ |
|
next = np->cur_tx_copy->next_desc_logical; |
|
next->skbuff = skb; |
|
next->control = TXIC | TXLD | CRCEnable | PADEnable; |
|
next->control |= (skb->len << PKTSShift); /* pkt size */ |
|
next->control |= ((skb->len - BPT) << TBSShift); /* buf size */ |
|
// 89/12/29 add, |
|
if (np->pci_dev->device == 0x891) |
|
np->cur_tx_copy->control |= ETIControl | RetryTxLC; |
|
next->buffer = dma_map_single(&ep->pci_dev->dev, |
|
skb->data + BPT, skb->len - BPT, |
|
DMA_TO_DEVICE); |
|
|
|
next->status = TXOWN; |
|
np->cur_tx_copy->status = TXOWN; |
|
|
|
np->cur_tx_copy = next->next_desc_logical; |
|
np->free_tx_count -= 2; |
|
} else { |
|
np->cur_tx_copy->buffer = dma_map_single(&np->pci_dev->dev, |
|
skb->data, skb->len, |
|
DMA_TO_DEVICE); |
|
np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable; |
|
np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */ |
|
np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */ |
|
// 89/12/29 add, |
|
if (np->pci_dev->device == 0x891) |
|
np->cur_tx_copy->control |= ETIControl | RetryTxLC; |
|
np->cur_tx_copy->status = TXOWN; |
|
np->cur_tx_copy = np->cur_tx_copy->next_desc_logical; |
|
--np->free_tx_count; |
|
} |
|
#endif |
|
|
|
if (np->free_tx_count < 2) |
|
netif_stop_queue(dev); |
|
++np->really_tx_count; |
|
iowrite32(0, np->mem + TXPDR); |
|
|
|
spin_unlock_irqrestore(&np->lock, flags); |
|
return NETDEV_TX_OK; |
|
} |
|
|
|
|
|
/* Take lock before calling */ |
|
/* Chip probably hosed tx ring. Clean up. */ |
|
static void reset_tx_descriptors(struct net_device *dev) |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
struct fealnx_desc *cur; |
|
int i; |
|
|
|
/* initialize tx variables */ |
|
np->cur_tx = &np->tx_ring[0]; |
|
np->cur_tx_copy = &np->tx_ring[0]; |
|
np->really_tx_count = 0; |
|
np->free_tx_count = TX_RING_SIZE; |
|
|
|
for (i = 0; i < TX_RING_SIZE; i++) { |
|
cur = &np->tx_ring[i]; |
|
if (cur->skbuff) { |
|
dma_unmap_single(&np->pci_dev->dev, cur->buffer, |
|
cur->skbuff->len, DMA_TO_DEVICE); |
|
dev_kfree_skb_any(cur->skbuff); |
|
cur->skbuff = NULL; |
|
} |
|
cur->status = 0; |
|
cur->control = 0; /* needed? */ |
|
/* probably not needed. We do it for purely paranoid reasons */ |
|
cur->next_desc = np->tx_ring_dma + |
|
(i + 1)*sizeof(struct fealnx_desc); |
|
cur->next_desc_logical = &np->tx_ring[i + 1]; |
|
} |
|
/* for the last tx descriptor */ |
|
np->tx_ring[TX_RING_SIZE - 1].next_desc = np->tx_ring_dma; |
|
np->tx_ring[TX_RING_SIZE - 1].next_desc_logical = &np->tx_ring[0]; |
|
} |
|
|
|
|
|
/* Take lock and stop rx before calling this */ |
|
static void reset_rx_descriptors(struct net_device *dev) |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
struct fealnx_desc *cur = np->cur_rx; |
|
int i; |
|
|
|
allocate_rx_buffers(dev); |
|
|
|
for (i = 0; i < RX_RING_SIZE; i++) { |
|
if (cur->skbuff) |
|
cur->status = RXOWN; |
|
cur = cur->next_desc_logical; |
|
} |
|
|
|
iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring), |
|
np->mem + RXLBA); |
|
} |
|
|
|
|
|
/* The interrupt handler does all of the Rx thread work and cleans up |
|
after the Tx thread. */ |
|
static irqreturn_t intr_handler(int irq, void *dev_instance) |
|
{ |
|
struct net_device *dev = (struct net_device *) dev_instance; |
|
struct netdev_private *np = netdev_priv(dev); |
|
void __iomem *ioaddr = np->mem; |
|
long boguscnt = max_interrupt_work; |
|
unsigned int num_tx = 0; |
|
int handled = 0; |
|
|
|
spin_lock(&np->lock); |
|
|
|
iowrite32(0, ioaddr + IMR); |
|
|
|
do { |
|
u32 intr_status = ioread32(ioaddr + ISR); |
|
|
|
/* Acknowledge all of the current interrupt sources ASAP. */ |
|
iowrite32(intr_status, ioaddr + ISR); |
|
|
|
if (debug) |
|
printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n", dev->name, |
|
intr_status); |
|
|
|
if (!(intr_status & np->imrvalue)) |
|
break; |
|
|
|
handled = 1; |
|
|
|
// 90/1/16 delete, |
|
// |
|
// if (intr_status & FBE) |
|
// { /* fatal error */ |
|
// stop_nic_tx(ioaddr, 0); |
|
// stop_nic_rx(ioaddr, 0); |
|
// break; |
|
// }; |
|
|
|
if (intr_status & TUNF) |
|
iowrite32(0, ioaddr + TXPDR); |
|
|
|
if (intr_status & CNTOVF) { |
|
/* missed pkts */ |
|
dev->stats.rx_missed_errors += |
|
ioread32(ioaddr + TALLY) & 0x7fff; |
|
|
|
/* crc error */ |
|
dev->stats.rx_crc_errors += |
|
(ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16; |
|
} |
|
|
|
if (intr_status & (RI | RBU)) { |
|
if (intr_status & RI) |
|
netdev_rx(dev); |
|
else { |
|
stop_nic_rx(ioaddr, np->crvalue); |
|
reset_rx_descriptors(dev); |
|
iowrite32(np->crvalue, ioaddr + TCRRCR); |
|
} |
|
} |
|
|
|
while (np->really_tx_count) { |
|
long tx_status = np->cur_tx->status; |
|
long tx_control = np->cur_tx->control; |
|
|
|
if (!(tx_control & TXLD)) { /* this pkt is combined by two tx descriptors */ |
|
struct fealnx_desc *next; |
|
|
|
next = np->cur_tx->next_desc_logical; |
|
tx_status = next->status; |
|
tx_control = next->control; |
|
} |
|
|
|
if (tx_status & TXOWN) |
|
break; |
|
|
|
if (!(np->crvalue & CR_W_ENH)) { |
|
if (tx_status & (CSL | LC | EC | UDF | HF)) { |
|
dev->stats.tx_errors++; |
|
if (tx_status & EC) |
|
dev->stats.tx_aborted_errors++; |
|
if (tx_status & CSL) |
|
dev->stats.tx_carrier_errors++; |
|
if (tx_status & LC) |
|
dev->stats.tx_window_errors++; |
|
if (tx_status & UDF) |
|
dev->stats.tx_fifo_errors++; |
|
if ((tx_status & HF) && np->mii.full_duplex == 0) |
|
dev->stats.tx_heartbeat_errors++; |
|
|
|
} else { |
|
dev->stats.tx_bytes += |
|
((tx_control & PKTSMask) >> PKTSShift); |
|
|
|
dev->stats.collisions += |
|
((tx_status & NCRMask) >> NCRShift); |
|
dev->stats.tx_packets++; |
|
} |
|
} else { |
|
dev->stats.tx_bytes += |
|
((tx_control & PKTSMask) >> PKTSShift); |
|
dev->stats.tx_packets++; |
|
} |
|
|
|
/* Free the original skb. */ |
|
dma_unmap_single(&np->pci_dev->dev, |
|
np->cur_tx->buffer, |
|
np->cur_tx->skbuff->len, |
|
DMA_TO_DEVICE); |
|
dev_consume_skb_irq(np->cur_tx->skbuff); |
|
np->cur_tx->skbuff = NULL; |
|
--np->really_tx_count; |
|
if (np->cur_tx->control & TXLD) { |
|
np->cur_tx = np->cur_tx->next_desc_logical; |
|
++np->free_tx_count; |
|
} else { |
|
np->cur_tx = np->cur_tx->next_desc_logical; |
|
np->cur_tx = np->cur_tx->next_desc_logical; |
|
np->free_tx_count += 2; |
|
} |
|
num_tx++; |
|
} /* end of for loop */ |
|
|
|
if (num_tx && np->free_tx_count >= 2) |
|
netif_wake_queue(dev); |
|
|
|
/* read transmit status for enhanced mode only */ |
|
if (np->crvalue & CR_W_ENH) { |
|
long data; |
|
|
|
data = ioread32(ioaddr + TSR); |
|
dev->stats.tx_errors += (data & 0xff000000) >> 24; |
|
dev->stats.tx_aborted_errors += |
|
(data & 0xff000000) >> 24; |
|
dev->stats.tx_window_errors += |
|
(data & 0x00ff0000) >> 16; |
|
dev->stats.collisions += (data & 0x0000ffff); |
|
} |
|
|
|
if (--boguscnt < 0) { |
|
printk(KERN_WARNING "%s: Too much work at interrupt, " |
|
"status=0x%4.4x.\n", dev->name, intr_status); |
|
if (!np->reset_timer_armed) { |
|
np->reset_timer_armed = 1; |
|
np->reset_timer.expires = RUN_AT(HZ/2); |
|
add_timer(&np->reset_timer); |
|
stop_nic_rxtx(ioaddr, 0); |
|
netif_stop_queue(dev); |
|
/* or netif_tx_disable(dev); ?? */ |
|
/* Prevent other paths from enabling tx,rx,intrs */ |
|
np->crvalue_sv = np->crvalue; |
|
np->imrvalue_sv = np->imrvalue; |
|
np->crvalue &= ~(CR_W_TXEN | CR_W_RXEN); /* or simply = 0? */ |
|
np->imrvalue = 0; |
|
} |
|
|
|
break; |
|
} |
|
} while (1); |
|
|
|
/* read the tally counters */ |
|
/* missed pkts */ |
|
dev->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff; |
|
|
|
/* crc error */ |
|
dev->stats.rx_crc_errors += |
|
(ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16; |
|
|
|
if (debug) |
|
printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n", |
|
dev->name, ioread32(ioaddr + ISR)); |
|
|
|
iowrite32(np->imrvalue, ioaddr + IMR); |
|
|
|
spin_unlock(&np->lock); |
|
|
|
return IRQ_RETVAL(handled); |
|
} |
|
|
|
|
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/* This routine is logically part of the interrupt handler, but separated |
|
for clarity and better register allocation. */ |
|
static int netdev_rx(struct net_device *dev) |
|
{ |
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struct netdev_private *np = netdev_priv(dev); |
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void __iomem *ioaddr = np->mem; |
|
|
|
/* If EOP is set on the next entry, it's a new packet. Send it up. */ |
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while (!(np->cur_rx->status & RXOWN) && np->cur_rx->skbuff) { |
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s32 rx_status = np->cur_rx->status; |
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|
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if (np->really_rx_count == 0) |
|
break; |
|
|
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if (debug) |
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printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n", rx_status); |
|
|
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if ((!((rx_status & RXFSD) && (rx_status & RXLSD))) || |
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(rx_status & ErrorSummary)) { |
|
if (rx_status & ErrorSummary) { /* there was a fatal error */ |
|
if (debug) |
|
printk(KERN_DEBUG |
|
"%s: Receive error, Rx status %8.8x.\n", |
|
dev->name, rx_status); |
|
|
|
dev->stats.rx_errors++; /* end of a packet. */ |
|
if (rx_status & (LONGPKT | RUNTPKT)) |
|
dev->stats.rx_length_errors++; |
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if (rx_status & RXER) |
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dev->stats.rx_frame_errors++; |
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if (rx_status & CRC) |
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dev->stats.rx_crc_errors++; |
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} else { |
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int need_to_reset = 0; |
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int desno = 0; |
|
|
|
if (rx_status & RXFSD) { /* this pkt is too long, over one rx buffer */ |
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struct fealnx_desc *cur; |
|
|
|
/* check this packet is received completely? */ |
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cur = np->cur_rx; |
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while (desno <= np->really_rx_count) { |
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++desno; |
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if ((!(cur->status & RXOWN)) && |
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(cur->status & RXLSD)) |
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break; |
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/* goto next rx descriptor */ |
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cur = cur->next_desc_logical; |
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} |
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if (desno > np->really_rx_count) |
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need_to_reset = 1; |
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} else /* RXLSD did not find, something error */ |
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need_to_reset = 1; |
|
|
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if (need_to_reset == 0) { |
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int i; |
|
|
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dev->stats.rx_length_errors++; |
|
|
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/* free all rx descriptors related this long pkt */ |
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for (i = 0; i < desno; ++i) { |
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if (!np->cur_rx->skbuff) { |
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printk(KERN_DEBUG |
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"%s: I'm scared\n", dev->name); |
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break; |
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} |
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np->cur_rx->status = RXOWN; |
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np->cur_rx = np->cur_rx->next_desc_logical; |
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} |
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continue; |
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} else { /* rx error, need to reset this chip */ |
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stop_nic_rx(ioaddr, np->crvalue); |
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reset_rx_descriptors(dev); |
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iowrite32(np->crvalue, ioaddr + TCRRCR); |
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} |
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break; /* exit the while loop */ |
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} |
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} else { /* this received pkt is ok */ |
|
|
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struct sk_buff *skb; |
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/* Omit the four octet CRC from the length. */ |
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short pkt_len = ((rx_status & FLNGMASK) >> FLNGShift) - 4; |
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|
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#ifndef final_version |
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if (debug) |
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printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d" |
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" status %x.\n", pkt_len, rx_status); |
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#endif |
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|
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/* Check if the packet is long enough to accept without copying |
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to a minimally-sized skbuff. */ |
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if (pkt_len < rx_copybreak && |
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(skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) { |
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skb_reserve(skb, 2); /* 16 byte align the IP header */ |
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dma_sync_single_for_cpu(&np->pci_dev->dev, |
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np->cur_rx->buffer, |
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np->rx_buf_sz, |
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DMA_FROM_DEVICE); |
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/* Call copy + cksum if available. */ |
|
|
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#if ! defined(__alpha__) |
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skb_copy_to_linear_data(skb, |
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np->cur_rx->skbuff->data, pkt_len); |
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skb_put(skb, pkt_len); |
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#else |
|
skb_put_data(skb, np->cur_rx->skbuff->data, |
|
pkt_len); |
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#endif |
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dma_sync_single_for_device(&np->pci_dev->dev, |
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np->cur_rx->buffer, |
|
np->rx_buf_sz, |
|
DMA_FROM_DEVICE); |
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} else { |
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dma_unmap_single(&np->pci_dev->dev, |
|
np->cur_rx->buffer, |
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np->rx_buf_sz, |
|
DMA_FROM_DEVICE); |
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skb_put(skb = np->cur_rx->skbuff, pkt_len); |
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np->cur_rx->skbuff = NULL; |
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--np->really_rx_count; |
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} |
|
skb->protocol = eth_type_trans(skb, dev); |
|
netif_rx(skb); |
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dev->stats.rx_packets++; |
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dev->stats.rx_bytes += pkt_len; |
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} |
|
|
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np->cur_rx = np->cur_rx->next_desc_logical; |
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} /* end of while loop */ |
|
|
|
/* allocate skb for rx buffers */ |
|
allocate_rx_buffers(dev); |
|
|
|
return 0; |
|
} |
|
|
|
|
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static struct net_device_stats *get_stats(struct net_device *dev) |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
void __iomem *ioaddr = np->mem; |
|
|
|
/* The chip only need report frame silently dropped. */ |
|
if (netif_running(dev)) { |
|
dev->stats.rx_missed_errors += |
|
ioread32(ioaddr + TALLY) & 0x7fff; |
|
dev->stats.rx_crc_errors += |
|
(ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16; |
|
} |
|
|
|
return &dev->stats; |
|
} |
|
|
|
|
|
/* for dev->set_multicast_list */ |
|
static void set_rx_mode(struct net_device *dev) |
|
{ |
|
spinlock_t *lp = &((struct netdev_private *)netdev_priv(dev))->lock; |
|
unsigned long flags; |
|
spin_lock_irqsave(lp, flags); |
|
__set_rx_mode(dev); |
|
spin_unlock_irqrestore(lp, flags); |
|
} |
|
|
|
|
|
/* Take lock before calling */ |
|
static void __set_rx_mode(struct net_device *dev) |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
void __iomem *ioaddr = np->mem; |
|
u32 mc_filter[2]; /* Multicast hash filter */ |
|
u32 rx_mode; |
|
|
|
if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ |
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memset(mc_filter, 0xff, sizeof(mc_filter)); |
|
rx_mode = CR_W_PROM | CR_W_AB | CR_W_AM; |
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} else if ((netdev_mc_count(dev) > multicast_filter_limit) || |
|
(dev->flags & IFF_ALLMULTI)) { |
|
/* Too many to match, or accept all multicasts. */ |
|
memset(mc_filter, 0xff, sizeof(mc_filter)); |
|
rx_mode = CR_W_AB | CR_W_AM; |
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} else { |
|
struct netdev_hw_addr *ha; |
|
|
|
memset(mc_filter, 0, sizeof(mc_filter)); |
|
netdev_for_each_mc_addr(ha, dev) { |
|
unsigned int bit; |
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bit = (ether_crc(ETH_ALEN, ha->addr) >> 26) ^ 0x3F; |
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mc_filter[bit >> 5] |= (1 << bit); |
|
} |
|
rx_mode = CR_W_AB | CR_W_AM; |
|
} |
|
|
|
stop_nic_rxtx(ioaddr, np->crvalue); |
|
|
|
iowrite32(mc_filter[0], ioaddr + MAR0); |
|
iowrite32(mc_filter[1], ioaddr + MAR1); |
|
np->crvalue &= ~CR_W_RXMODEMASK; |
|
np->crvalue |= rx_mode; |
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iowrite32(np->crvalue, ioaddr + TCRRCR); |
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} |
|
|
|
static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
|
|
strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
|
strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info)); |
|
} |
|
|
|
static int netdev_get_link_ksettings(struct net_device *dev, |
|
struct ethtool_link_ksettings *cmd) |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
|
|
spin_lock_irq(&np->lock); |
|
mii_ethtool_get_link_ksettings(&np->mii, cmd); |
|
spin_unlock_irq(&np->lock); |
|
|
|
return 0; |
|
} |
|
|
|
static int netdev_set_link_ksettings(struct net_device *dev, |
|
const struct ethtool_link_ksettings *cmd) |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
int rc; |
|
|
|
spin_lock_irq(&np->lock); |
|
rc = mii_ethtool_set_link_ksettings(&np->mii, cmd); |
|
spin_unlock_irq(&np->lock); |
|
|
|
return rc; |
|
} |
|
|
|
static int netdev_nway_reset(struct net_device *dev) |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
return mii_nway_restart(&np->mii); |
|
} |
|
|
|
static u32 netdev_get_link(struct net_device *dev) |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
return mii_link_ok(&np->mii); |
|
} |
|
|
|
static u32 netdev_get_msglevel(struct net_device *dev) |
|
{ |
|
return debug; |
|
} |
|
|
|
static void netdev_set_msglevel(struct net_device *dev, u32 value) |
|
{ |
|
debug = value; |
|
} |
|
|
|
static const struct ethtool_ops netdev_ethtool_ops = { |
|
.get_drvinfo = netdev_get_drvinfo, |
|
.nway_reset = netdev_nway_reset, |
|
.get_link = netdev_get_link, |
|
.get_msglevel = netdev_get_msglevel, |
|
.set_msglevel = netdev_set_msglevel, |
|
.get_link_ksettings = netdev_get_link_ksettings, |
|
.set_link_ksettings = netdev_set_link_ksettings, |
|
}; |
|
|
|
static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
int rc; |
|
|
|
if (!netif_running(dev)) |
|
return -EINVAL; |
|
|
|
spin_lock_irq(&np->lock); |
|
rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL); |
|
spin_unlock_irq(&np->lock); |
|
|
|
return rc; |
|
} |
|
|
|
|
|
static int netdev_close(struct net_device *dev) |
|
{ |
|
struct netdev_private *np = netdev_priv(dev); |
|
void __iomem *ioaddr = np->mem; |
|
int i; |
|
|
|
netif_stop_queue(dev); |
|
|
|
/* Disable interrupts by clearing the interrupt mask. */ |
|
iowrite32(0x0000, ioaddr + IMR); |
|
|
|
/* Stop the chip's Tx and Rx processes. */ |
|
stop_nic_rxtx(ioaddr, 0); |
|
|
|
del_timer_sync(&np->timer); |
|
del_timer_sync(&np->reset_timer); |
|
|
|
free_irq(np->pci_dev->irq, dev); |
|
|
|
/* Free all the skbuffs in the Rx queue. */ |
|
for (i = 0; i < RX_RING_SIZE; i++) { |
|
struct sk_buff *skb = np->rx_ring[i].skbuff; |
|
|
|
np->rx_ring[i].status = 0; |
|
if (skb) { |
|
dma_unmap_single(&np->pci_dev->dev, |
|
np->rx_ring[i].buffer, np->rx_buf_sz, |
|
DMA_FROM_DEVICE); |
|
dev_kfree_skb(skb); |
|
np->rx_ring[i].skbuff = NULL; |
|
} |
|
} |
|
|
|
for (i = 0; i < TX_RING_SIZE; i++) { |
|
struct sk_buff *skb = np->tx_ring[i].skbuff; |
|
|
|
if (skb) { |
|
dma_unmap_single(&np->pci_dev->dev, |
|
np->tx_ring[i].buffer, skb->len, |
|
DMA_TO_DEVICE); |
|
dev_kfree_skb(skb); |
|
np->tx_ring[i].skbuff = NULL; |
|
} |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static const struct pci_device_id fealnx_pci_tbl[] = { |
|
{0x1516, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
|
{0x1516, 0x0803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, |
|
{0x1516, 0x0891, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, |
|
{} /* terminate list */ |
|
}; |
|
MODULE_DEVICE_TABLE(pci, fealnx_pci_tbl); |
|
|
|
|
|
static struct pci_driver fealnx_driver = { |
|
.name = "fealnx", |
|
.id_table = fealnx_pci_tbl, |
|
.probe = fealnx_init_one, |
|
.remove = fealnx_remove_one, |
|
}; |
|
|
|
static int __init fealnx_init(void) |
|
{ |
|
return pci_register_driver(&fealnx_driver); |
|
} |
|
|
|
static void __exit fealnx_exit(void) |
|
{ |
|
pci_unregister_driver(&fealnx_driver); |
|
} |
|
|
|
module_init(fealnx_init); |
|
module_exit(fealnx_exit);
|
|
|